JP5045934B2 - Information processing apparatus, emulation method and emulation program in information processing apparatus - Google Patents

Description

  The present invention relates to an information processing apparatus that emulates a predetermined program on a processor, an emulation method, and an emulation program.

  In general, in software emulation for realizing functions such as OS (Operating System) of another system on a computer system, the emulation is performed in units of one software instruction.

FIG. 15 is a schematic diagram schematically illustrating a software emulation execution process in a general computer system.
As shown in the drawing, each software instruction is stored in the OS SW instruction code area 106 in the order of instruction A to instruction B, instruction C, instruction D, instruction E,.
The instruction counter C01 indicates the storage address (address X) of the software instruction (instruction A) currently being executed (or executed in the future) on the memory, and the instruction word length of the software instruction is fixed to 4 bytes. The specified address (address) is updated in ascending order, such as address X + 4 when instruction A is completed, address X + 8 when instruction B is completed, address X + 12 when instruction C is completed, and so on. An instruction cycle is sequentially executed for each software instruction.

  Therefore, a fundamental improvement in the emulation speed cannot be expected unless the hardware performance of the computer system is enhanced, and it has been said that there is a certain limit to speeding up emulation by software processing.

Under such circumstances, an emulation method and a computer system capable of improving the emulation speed of the computer system regardless of the hardware performance have been proposed (for example, see Patent Document 1).
According to this emulation method or the like, in the case of a combination in which a plurality of target instructions can be processed in a batch, the plurality of target instructions created in advance are branched to a batch coding and the processing is executed according to the coding.
Therefore, it has been expected as a technology capable of improving the emulation speed while utilizing existing resources, and capable of rational and high-speed processing.

JP 2007-310546 A (page 1-8, FIG. 1)

However, in the emulation method described in Patent Document 1, the order control of the target instruction is not clearly shown, and in particular, the process related to rewriting and updating of the instruction counter (program counter) in the instruction cycle is not clear. .
For this reason, there is a possibility that a delay or the like due to duplicate processing of the same instruction occurs.
In addition, since a system that exclusively performs branch processing is employed, the algorithm is complicated, and the processing capability may be reduced.

  An object of the present invention is to provide an information processing apparatus, an emulation method, and an emulation program that solve the above-described problem in the instruction execution process and increase the speed of emulation.

  In order to achieve the above object, an information processing apparatus according to the present invention includes a SW extraction unit that extracts a plurality of software instructions that can be collectively executed from one or more software instructions, and a plurality of pieces extracted by the SW extraction unit. A combination unit configured to combine a plurality of software instructions to form a predetermined composite software instruction, and an execution control unit that emulates the composite software instruction or the software instruction on a predetermined processor based on a predetermined order. .

  The emulation method of the present invention is an emulation method for speeding up the emulation of software instructions, the step of extracting a plurality of software instructions that can be executed in a batch from one or more software instructions, The plurality of software instructions are combined to form a predetermined composite software instruction, and the composite software instruction or the software instruction is emulated on a predetermined processor based on a predetermined order.

  Furthermore, an emulation program of the present invention is an emulation program for speeding up the emulation in an information processing device that emulates a software instruction on a predetermined processor, and includes one or more computers constituting the information processing device. SW extracting means for extracting a plurality of software instructions that can be executed collectively from software instructions, and combining means for combining a plurality of software instructions extracted by the SW extracting means to constitute a predetermined composite software instruction; It is a program for causing the composite software instruction or the software instruction to function as execution control means for emulating on a predetermined processor based on a predetermined order.

According to the present invention, it is possible to accurately improve the emulation speed based on the combination of software instructions and an appropriate execution process.
It is also possible to speed up emulation while utilizing existing resources.

A preferred embodiment of the present invention will be described below with reference to FIGS.
Here, the information processing apparatus of the present embodiment described below is realized by processing, means, and functions executed by a computer according to instructions of a program (software). The program sends a command to each component of the computer to perform predetermined processing and functions as shown below. That is, each process and means in the information processing apparatus of the present embodiment is realized by specific means in which a program and a computer cooperate.
Note that all or part of the program is provided by, for example, a magnetic disk, optical disk, semiconductor memory, or any other computer-readable recording medium, and the program read from the recording medium is installed in the computer and executed. The The program can also be loaded and executed directly on a computer through a communication line without using a recording medium.

FIG. 1 is a functional block diagram showing a basic configuration of an information processing apparatus common to various embodiments of the present invention.
An information processing apparatus 1 shown in FIG. 1 is an information processing apparatus for operating software instructions on a processor, and includes an SW extraction unit 10, a combination unit 11, and an execution control unit 12.
The SW extraction means 10 extracts software instructions 13 that can be executed in a batch from one or more software instructions 13.
The compounding means 11 composes a predetermined composite software instruction 14 by compounding a plurality of software instructions 13 extracted by the SW extracting means 13.
Then, the execution control unit 12 selects the composite software instruction 14 configured by the composite unit 11 or the software instruction 13 not configured by the composite unit 11 based on a predetermined order, and causes the emulator 103 on the processor 104 to execute it. Is.

[First embodiment]
2 and 3 are block diagrams showing the basic configuration of the information processing apparatus according to the first embodiment of the present invention.
As shown in FIG. 2, the information processing apparatus 1 according to the present embodiment is information processing that processes software instructions by software emulation so that the software instructions can be operated on a general-purpose processor.
Specifically, the information processing apparatus 1 executes a processor (CPU: Central Processing Unit) 104 that executes and controls instructions according to a program, a memory 105 that stores programs and data necessary for processing by the processor 104, and a processor 104 An IO (Input Output) device 109 including an input unit for inputting commands and other data and an output unit for displaying the processing result of the processor 104 is configured.

The memory 105 is a semiconductor memory, a magnetic disk, an optical disk or other recording medium, and has various storage areas.
Specifically, the memory 105 includes an OS SW instruction code area (storage area of the present invention) 106 in which software instructions for the operating system 102 are stored, and a plurality of software instructions 13 included in the software instructions. A composite SW instruction code area (second storage area of the present invention) 107 for storing the composite software instruction 14 and an emulator memory area 108 for storing the emulation program (emulator 103).
The memory 105 also includes predetermined table storage areas (conversion tables T01 and T03 and a next IC (Instruction Counter) table T02 described later) used for execution control of the software instruction 13 and the composite software instruction 14.

The processor 104 reads the emulation program 103 stored in the emulator memory area 108, executes the emulation process according to the emulation program 103, and executes the process of the application program 101 while replacing the instruction of the operating system 102 with a predetermined instruction.
In particular, in the present embodiment, emulation of the software instruction 13 or the composite software instruction 14 is executed under execution control (execution control means 12) by the code analysis program 110.

  The code analysis program 110 searches and determines whether there is a software instruction 13 that can be converted into the composite software instruction 14 from the SW instruction code area 106 of the memory 105, and two or more convertible software instructions 13 are stored. If there are, they are extracted (SW extraction means 10), combined (compositing means 11), and an instruction to store in the composite SW instruction code area 107 is given to the processor 111.

In addition, the code analysis program 110 is normally operated on a dedicated processor 111 as shown in FIG. 2, but may take other forms.
For example, as shown in FIG. 3, an emulator and a code analysis program 110 may be mounted on one processor 112, and the code analysis program 110 may be operated using the processing idle time of the emulator 104.
With such a configuration, the processor 112 can be operated efficiently, so that the same effect as the information processing apparatus 1 shown in FIG. 2 can be obtained while effectively utilizing resources.
Therefore, when “processor” is hereinafter referred to, the shared processor 112 in the form of FIG. 3 is also included in this.

Here, a specific processing method of the code analysis program 110 will be described with reference to FIG.
FIG. 4 is a schematic diagram schematically showing how the code analysis program that runs on the information processing apparatus according to the present embodiment is controlled.
Note that the instruction counter (instruction counter of the present invention) C01 and the OS software instruction code area 106 have the same functions as those of a general information processing apparatus, and the basic processing process follows the flow shown in FIG. Is.
That is, based on the address specified by the instruction counter C01, the software instructions 13 are extracted one by one in order from the youngest address in the OS SW instruction code area 106 and executed (SW execution means of the present invention).
After execution of one software instruction 13, the designated address of the instruction counter C01 is updated to the next address and one instruction cycle is completed.

However, in this embodiment, the code analysis program 110 sequentially reads the software instructions 13 from the OS SW instruction code area 106, and analyzes and determines whether or not compounding is possible.
When it is determined that the composite is possible, the composite software instruction 14 obtained by the composite means is stored in the composite SW instruction code area 107 and executed as necessary (the composite SW execution of the present invention). means).
Also, in order to identify the original composite software instruction 13 and execute instructions in an appropriate order while avoiding duplication processing or the like, in the SW instruction code area 106 for OS of the software instruction 13 before the combination in advance. The address, the address in the composite SW instruction code area 107 of the composite software instruction 14 obtained by the composition, and the address to be designated next by the instruction counter C01 are registered in the conversion table T01 (the present invention). Table registration means).

  As shown in FIG. 4, in this embodiment, SW instruction A and SW instruction B are combined into a composite SW instruction A + B, and SW instruction D and SW instruction E are combined into a composite SW instruction D + E. In the table T01, in the first word, the storage address “X address” of the SW instruction A, the storage address “Y address” of the composite SW instruction A + B, and the storage address “X + 8” of the SW instruction to be specified next by the instruction counter C01 are stored. Is stored in the second word, the storage address “X + 12” of the SW instruction D, the storage address “Y + 4” of the composite SW instruction D + E, and the storage address “X + 20” of the SW instruction to be specified next by the instruction counter C01. "Will be registered.

When executing the software instruction 13, the processor 104 first searches the conversion table T01. If the same address as the designated address of the instruction counter C01 is registered in the “instruction counter” field, the processor 104 responds accordingly. The registered address data in the “Composite IC” column is taken out and used as the designated address of the composite instruction counter C02 (second instruction counter of the present invention).
Next, the processor 104 accesses the address designated by the composite instruction counter C02, retrieves the composite software instruction 14, and executes it.
On the other hand, when the same address as the designated address of the instruction counter C01 is not registered in the “instruction counter” column, the software instruction 13 at the designated address is extracted and executed.

After the composite software instruction 14 is executed, one instruction cycle is completed by setting the address data in the “next IC” column registered in association with each other on the conversion table T01 in the instruction counter C01. A new instruction cycle is started based on the next designated address of the instruction counter C01.
As a result, conventionally, the instruction A, the instruction B, the instruction C, the instruction D, the instruction D, and the instruction E are serially operated for each instruction, whereas the composite processing and execution process according to the present embodiment are performed. By the control, partly parallel processing with the instruction A + B, the instruction C, and the instruction D + E is performed, so that the emulation speed can be improved.

Next, the composite processing according to the present embodiment will be described in detail with reference to the drawings.
FIG. 5 is an image diagram for explaining the composite processing performed in the information processing apparatus according to the present embodiment.
As shown in FIG. 5, here, the LD instruction for storing the data stored in the SW instruction code area 106 of the memory 105 in the general-purpose register “GRx”, the general-purpose register “GRx”, and the general-purpose register “GRy” are added. An example in which two systems of EXE instructions stored in the general-purpose register “GRx” are combined will be described.
The general-purpose processor has two pipelines in the memory access system and one pipeline in the arithmetic system. The pipeline installation based on the register dependency is 1T, and the general-purpose register “GRx / GRy” is visible from the software. It is assumed that the register (SW visible register) is arranged in a local memory space that is not a software area.

As shown in the figure, at the 1T of the LD instruction, data is extracted from the memory space “MEM” in the SW instruction code area 106 and temporarily stored in the work register “WK1” in the processor.
In 2T, the contents of the work register “WK1” are stored in the general-purpose register “GRx” arranged in the local memory space.
At the 3T, that is, the 1T of the EXE instruction, the contents of the general-purpose register “GRx” and the general-purpose register “GRy” are read to the work registers “WK1” and “WK2” in the processor, respectively.
In this example, since the memory access system includes two pipelines, it is possible to execute two ld instructions simultaneously as shown in FIG.
At 4T, the values of the work register “WK1” and the work register “WK2” are added and stored in the work register “WK1”.
At 5T, the value of the work register “WK1” is stored in the general-purpose register “GRx”.
In the above example, the number of processes T for the LD instruction and the EXE instruction is 5T. However, the number of processes T depends on the number of pipelines of the general-purpose processor and the number of pipeline installations based on register dependency. May increase or decrease.

Next, an LD + EXE instruction that combines the LD instruction and the EXE instruction will be described.
At 1T, data is extracted from the memory space “MEM” of the SW instruction code area 106 and stored in the work register “WK1” in the processor.
The contents of the general-purpose register “GRy” are stored in the work register “WK2”.
In this example, two ld instructions can be executed at the same time, and these can be processed in parallel in 1T.
In 2T, the values of the work register “WK1” and the work register “WK2” are added and stored in the work register “WK1”.
At 3T, the value of the work register “WK1” is stored in the general-purpose register “GRx” arranged in the local memory space.

As a result, as shown in FIG. 5, the number of processes T of the combined instruction LD + EXE instruction is 3T, and 2T performance improvement can be achieved as compared with 5T before combining.
In this way, the emulation speed can be further increased by configuring the composite software instruction 14 in consideration of the number of pipelines of general-purpose processors, the number of T of pipeline installation, and the like.

Next, the processing procedure of the processor in the information processing apparatus of the first embodiment configured as described above will be described with reference to FIG.
FIG. 6 is a flowchart showing the processing procedure of the processor in the information processing apparatus according to the first embodiment of the present invention.
First, under the instruction of the code analysis program 110, the processor 111 searches and determines whether the address data designated by the instruction counter C01 is registered in the conversion table T01 (S501).
As a result, when it is determined that the designated address is not registered in the conversion table T01 (S502: NO), the processor 104, based on the instruction of the code analysis program 110, uses the software stored at the address designated by the instruction counter C01. The instruction 13 is extracted from the SW instruction code area 106 (S503).
The processor 104 executes the software instruction 13 fetched in step S503 (S504), and then updates the instruction counter C01 to the next address to complete one instruction cycle (S505).

On the other hand, when it is determined that the address data designated by the instruction counter C01 is registered in the conversion table T01 (S502: YES), the processor 104 registers the registered data in the conversion table T01 under the instruction of the code analysis program 110. The address data in the “Composite IC” column and the “Next IC” column are extracted from (S506).
Next, the processor 104 uses the address data in the “Composite IC” column extracted in Step S506 as the designated address of the composite instruction counter C02, and uses the composite software instruction 14 stored in the designated address as the code area 107 for the composite SW instruction. (S507).
The processor 104 then executes the composite software instruction 14 extracted in step S507 (S508). Finally, the instruction counter C01 is set at the address of “next IC” and one instruction cycle is completed (S509). ).

As described above, the information processing apparatus 1 according to the present embodiment includes the code analysis program 110, and the processor 104 accurately executes instruction processing under the control of the code analysis program 110. .
Specifically, the processor 104 is controlled to extract the software instruction 13 that can be combined from the SW instruction code area 106, combine it, and store it in the composite SW instruction code area 107.
Then, the processor 104 extracts the composite software instruction 14 from the composite SW instruction code area 107 and executes it as necessary.
For this reason, since a plurality of instructions can be processed in parallel instead of processing a single instruction serially, the processing time is shortened, and as a result, the emulation speed can be improved.

Further, according to the information processing apparatus 1 according to the present embodiment, the conversion table T01 is arranged in a predetermined area of the memory 105, and the code analysis program 110 controls the processor 104 based on the registration data of the conversion table T01. I have to.
Specifically, in the conversion table T01, in addition to the address of the original software instruction 13 used for the composition and the address of the composite software instruction 14 obtained by the composition, the address of the software instruction 13 to be executed next is included. Is registered.
When executing the software instruction 13, the specified value of the instruction counter C01 is compared with the registered data of the conversion table T01, and the instruction processing corresponding to the comparison result is selected and executed. The code analysis program 110 controls the processor 104.

For this reason, duplicate instruction processing and excessive branch processing are not generated, and the cause of the speed reduction is eliminated, thereby indirectly contributing to improvement of the emulation speed.
In particular, in the case of a general-purpose processor having a plurality of pipelines, the composite software instruction 14 is configured so as to make the most of the number of pipelines, and is registered on the conversion table T01, so that the parallelism of the pipelines can be increased. It is possible to further improve the emulation speed, such as being able to improve.

  Furthermore, since the code analysis program 110 and the conversion table T01 according to the present embodiment are software resources, the existing hardware can be used as it is, and the information processing apparatus 1 having excellent cost can be easily realized. It is possible.

[Second Embodiment]
Next, an information processing apparatus according to the second embodiment of the present invention will be described with reference to FIGS.
FIG. 7 is a schematic diagram schematically showing a control state of a code analysis program operating on the information processing apparatus according to the second embodiment of the present invention.
In this embodiment, the composite software instruction 14 obtained by the compounding means is not stored in the dedicated code area (composite SW instruction code area 107), but overwritten on the original SW instruction code area 106. This is different from the first embodiment.

That is, as shown in FIG. 7, the code analysis program 110 sequentially reads the SW instruction A, SW instruction B,... Instruction from the SW instruction code area 106, and analyzes / determines whether or not compounding is possible. To do.
When it is determined that the combination is possible, the composite software instruction 14 obtained by the combination means is overwritten and stored in the SW instruction code area 106 '. (In FIG. 7, the area 106 and the area 106 ′ are shown separately for convenience of explanation, but actually indicate the same memory space.)

As a result, the instruction word length (4 bytes) of the composite SW instruction is shorter than the instruction word length (8 bytes) before the compounding, so that if the normal sequential processing is performed, duplicate instruction processing will be performed. is not.
For example, in the case of the present embodiment, after execution of the composite SW instruction A + B, the SW instruction B is read again and an incorrect process (SW instruction B) is executed.
Therefore, in the present embodiment, the next IC table T02 is provided in order to accurately identify the head of the next instruction to be executed.
In this next IC table T02, the address of the original software instruction 13 used for decoding and the address of the software instruction 13 to be executed next are registered in association with each other. After the value of the counter C01 and the registered data in the next IC table T02 are collated, instruction execution is performed in an appropriate order without duplication processing.

In the example of the present embodiment, the SW instruction A and the SW instruction B are combined into a composite SW instruction A + B, and the X address is overwritten and stored.
In addition, the SW instruction D and the SW instruction E are combined into a composite SW instruction D + E, and are overwritten and stored at address X + 12.
Therefore, in the next IC table T02, the storage address “X address” of the composite SW instruction A + B and the storage address “X + 8 address” of the SW instruction to be specified next by the instruction counter C01 are registered in the first word. In the second word, the storage address “X + 12” of the composite SW instruction D + E and the storage address “X + 20” of the SW instruction to be specified next by the instruction counter C01 are registered.

Then, the processor 104 executes the software instruction 13 or the composite software instruction 14 stored at the instruction address of the instruction counter C01. The processor 104 searches the next IC table T02 and has the same address as the instruction address of the instruction counter C01. If the address is registered in the “instruction counter” field, the corresponding address data in the “next IC” field is extracted, and the instruction counter C01 is updated with the extracted address data after the instruction is executed. I am doing so.
Thus, one instruction cycle is completed, and a new instruction cycle is started based on the updated designated address in the instruction counter C01.
As described above, in general, instructions A, Instruction B, Instruction C, Instruction D, Instruction D, and Instruction E are sequentially processed one by one, whereas the composite processing according to this embodiment is performed. And by the execution process control, processing is performed in a reasonable and proper order with the instruction A + B, the instruction C, and the instruction D + E. As a result, the emulation speed can be improved.

Therefore, the processing procedure of the processor in the information processing apparatus according to the present embodiment will be described with reference to FIG.
FIG. 8 is a flowchart showing the processing procedure of the processor in the information processing apparatus according to the second embodiment of the present invention.
First, under the instruction of the code analysis program 110, the processor 111 searches and determines whether the address data designated by the instruction counter C01 is registered in the next IC table T02 (S701).
As a result, when it is determined that the designated address of the instruction counter C01 is not registered in the next IC table T02 (S702: NO), the processor 104 stores the designated address of the instruction counter C01 based on the instruction of the code analysis program 110. The software instruction 13 is taken out from the SW instruction code area 106 (S703).
Then, the processor 104 performs the execution process of the software instruction 13 fetched in S703 (S704), and then updates the instruction counter C01 to the next address and ends one instruction cycle (S705).

On the other hand, when it is determined that the address specified by the instruction counter C01 is registered in the next IC table T02 (S702: YES), the processor 104 registers the next IC table T02 under the instruction of the code analysis program 110. The address data in the “next IC” column is extracted from the data (S706).
Next, the processor 104 extracts the composite software instruction 14 stored at the designated address of the instruction counter C01 from the SW instruction code area 106 ′ (S707).
The processor 104 executes the composite software instruction 14 fetched in S707 (S708), and finally sets the address data in the “next IC” column fetched in step S706 as the next IC value of the instruction counter C01. One instruction cycle is completed (S709).

As described above, according to the information processing apparatus 1 of the present embodiment, unlike the first embodiment, a dedicated area (the composite SW instruction code area SW instruction code area 107) for storing the composite software instruction 14 is not provided. The composite software instruction 14 is overwritten and stored in the original SW instruction code area 106.
For this reason, not only can the storage area of the memory 105 be reduced, but there is no need to index the composite software instruction 14 as in the first embodiment, so overhead can be suppressed and efficient instruction processing can be performed.
That is, even in an aspect different from the first embodiment, it is possible to achieve the same effect as that of the above-described form, and it is also possible to exhibit other effects that enhance the function.

[Third embodiment]
Next, an information processing apparatus according to a third embodiment of the present invention will be described with reference to FIGS.
FIG. 9 is a schematic diagram schematically showing a state of control of the code analysis program operating on the information processing apparatus according to the third embodiment of the present invention.
In the present embodiment, the composite software instruction 14 obtained by the compounding means is overwritten and stored in the SW instruction code area 106 as in the second embodiment, but no table storage area for execution control is provided. This is different from the previous embodiment.

First, the code analysis program 110 sequentially reads the SW instruction A, SW instruction B,... Instruction from the SW instruction code area 106, and analyzes / determines whether or not compounding is possible.
When it is determined that the combination is possible, the composite software instruction 14 obtained by the combination means is overwritten and stored in the SW instruction code area 106 '. (In FIG. 9, the area 106 and the area 106 ′ are shown separately for convenience of explanation, but actually indicate the same memory space.)

As a result, the instruction word length (4 bytes) of the composite SW instruction is shorter than the instruction word length (8 bytes) before the compounding, so that if the normal sequential processing is performed, duplicate instruction processing will be performed. is not.
For example, in the case of the present embodiment, after execution of the composite SW instruction A + B, the SW instruction B is read again and an incorrect process (SW instruction B) is executed.
Therefore, in the present embodiment, a predetermined identification code is stored at an address that does not involve execution of the software instruction 13 in order to accurately identify the head of the instruction to be executed next.
In the example of the present embodiment, as shown in FIG. 9, an identification code “NOP (No Operation)” is stored in a corresponding address.
Therefore, under normal sequential processing, the SW instruction B is executed redundantly, resulting in a malfunction. However, by replacing the SW instruction B with “NOP”, the NOP instruction is executed after the composite SW instruction A + B is executed ( In fact, nothing is operated), and the next SW instruction C is fetched and executed.

Next, the processing procedure of the processor in the information processing apparatus according to the present embodiment will be described with reference to FIG.
FIG. 10 is a flowchart showing the processing procedure of the processor in the information processing apparatus according to the third embodiment of the present invention.
First, the processor 104 determines whether or not NOP is stored by accessing the address designated by the instruction counter C01 (S901).
As a result, when NOP is not stored at the designated address (S902: NO), the processor 104 takes out the software instruction 13 or the composite software instruction 14 stored at the address designated by the instruction counter C01 (S903).
The processor 104 then executes the instruction fetched in step S903 (S904), and then updates the instruction counter C01 to the next address and ends one instruction cycle (S905).

  On the other hand, when NOP is stored at the address designated by the instruction counter C01 (S902: YES), the processor 104 updates the designated address of the instruction counter C01 to the next value without performing the instruction execution processing ( S905).

As described above, according to the information processing apparatus 1 of this embodiment, the composite SW instruction code area 107 is not provided as in the second embodiment, but a table area for execution control in the processor 104 is not provided. I am doing so.
A predetermined identification code (NOP) is stored at an address where instruction execution is omitted, so that duplicate processing in sequential processing is directly prevented.
For this reason, the overhead relating to the storage area of the memory 105 and the instruction index is further suppressed, and more efficient instruction processing is possible.
That is, as in the information processing apparatus 1 according to the present embodiment, the same effects as those described above can be achieved even in a mode different from the first or second embodiment, and other effects of further enhancing the function can be achieved. It is possible.

[Fourth embodiment]
Next, an information processing apparatus according to the fourth embodiment of the present invention will be described with reference to FIGS.
FIG. 11 is a schematic diagram schematically showing a control state of a code analysis program operating on the information processing apparatus according to the fourth embodiment of the present invention.
In this embodiment, as in the second embodiment or the third embodiment, the composite software instruction 14 obtained by the composite means is overwritten and stored in the SW instruction code area 106.
However, unlike the first and second embodiments in that a table storage area for execution control is not provided, an address that does not involve instruction execution processing is not an identification code, but an address of an instruction to be executed next. It differs from the third embodiment in that data (next IC) is stored.

First, the code analysis program 110 sequentially reads the SW instruction A, SW instruction B,... Instruction from the SW instruction code area 106, and analyzes / determines whether or not compounding is possible.
When it is determined that the combination is possible, the composite software instruction 14 obtained by the combination means is overwritten and stored in the SW instruction code area 106 '. (In FIG. 11, the area 106 and the area 106 ′ are shown separately for convenience of explanation, but actually indicate the same memory space.)

As a result, the instruction word length (4 bytes) of the composite software instruction 14 is shorter than the instruction word length (12 bytes) before the combination, and therefore, if normal sequential processing is performed, duplicate instruction processing is performed. ,Not appropriate.
For example, in the case of the present embodiment, after the composite SW instruction A + B + C is executed, the SW instruction B and the SW instruction C are read again, and erroneous processing (SW instruction B and SW instruction C) is executed. .
For this reason, in this embodiment, in order to accurately identify the head of the next instruction to be executed, the address data (next IC) of the instruction to be executed next is assigned to the address where the execution of the software instruction 13 is not accompanied. I am trying to store it.
Therefore, under normal sequential processing, the SW instruction B and SW instruction C are executed redundantly, causing a problem. However, after the SW instruction B is replaced with the next IC value, the instruction is executed after the composite SW instruction A + B + C is executed. The value of the counter C01 is set to the next IC value (address X + 12), and the composite SW instruction D + E stored at the address X + 12 is taken out and executed.

Next, the processing procedure of the processor in the information processing apparatus according to the present embodiment will be described with reference to FIG.
FIG. 12 is a flowchart showing the processing procedure of the processor in the information processing apparatus according to the fourth embodiment of the present invention.
First, the processor 104 determines whether or not address data (IC value) is stored by accessing the address specified by the instruction counter C01 (S1101).
As a result, when it is determined that the IC value is not stored at the designated address (S1102: NO), the processor 104 takes out the software instruction 13 or the composite software instruction 14 stored at the address designated by the instruction counter C01. (S1103).
Then, the processor 104 executes the instruction fetched in step S1103 (S1104), and then updates the instruction counter C01 to the next address to complete one instruction cycle (S1105).

  On the other hand, if it is determined that the IC value is stored at the address specified by the instruction counter C01 (S1102: YES), the processor 104 does not execute the instruction execution process, and the IC is set as the specified address of the instruction counter C01. A value is set (S1106).

As described above, according to the information processing apparatus 1 of the present embodiment, the composite SW instruction code area 107 is not provided as in the second to fourth embodiments, and as in the third embodiment. A table storage area is not provided.
However, in order to prevent instruction duplication processing, the next IC value is stored at an address where instruction execution is omitted, and the third embodiment is different from the third embodiment in that the instruction counter C01 is directly controlled.
For this reason, the overhead relating to the storage area of the memory 105 and the instruction index is further suppressed, and more efficient instruction processing is possible.
As described above, according to the information processing apparatus according to the present embodiment, the same effects as those described above can be achieved even in a different aspect from the above-described embodiment, and other effects of enhancing the function can be achieved.

[Fifth embodiment]
Next, an information processing apparatus according to a fifth embodiment of the present invention will be described with reference to FIGS.
FIG. 13 is a schematic diagram schematically showing a state of control of the code analysis program operating on the information processing apparatus according to the fifth embodiment of the present invention.
In this embodiment, a predetermined table storage area is provided as in the first embodiment and the second embodiment described above, but differs in that the composite software instruction 14 obtained by the compounding means is stored in the table storage area.

First, the code analysis program 110 sequentially reads the SW instruction A, SW instruction B,... Instruction from the SW instruction code area 106, and analyzes / determines whether or not compounding is possible.
If it is determined that it can be combined, the combined software instruction 14 obtained by the combining means is stored in the conversion table T03.
Also, in the conversion table T03, the address of the original software instruction 13 and the address of the next instruction counter C01 used for the combination are registered in association with the composite software instruction 14 to be stored. At this time, the value of the instruction counter C01 and the registered data of the conversion table T03 are collated, and the instructions are executed in an appropriate order without duplication processing.

Specifically, in this embodiment, the SW instruction A and the SW instruction B are combined into a composite SW instruction A + B, and the SW instruction D and the SW instruction E are combined into a composite SW instruction D + E.
Therefore, in the conversion table T03, the composite SW instruction A + B is stored in the first word, and the first address “X address” of the original software instruction 13 and the storage address of the SW instruction to be specified next by the instruction counter C01 are stored. "X + 8 address" is registered, the composite SW instruction D + E is stored in the second word, and the first address "X + 12" of the original software instruction 13 and the SW instruction storage address to be designated next by the instruction counter C01 are stored. Register “X + 20”.

Then, the processor 104 executes the software instruction 13 or the composite software instruction 14 stored at the instruction address of the instruction counter C01. At this time, the processor 104 searches the conversion table T03 and specifies the specified address of the instruction counter C01. When the same address is registered in the “command counter” field, the address data in the “next IC” field registered correspondingly is extracted.
After execution of the instruction, one instruction cycle is completed by updating the instruction counter C01 with the address data in the “next IC” column extracted from the conversion table T03, and the designated address after the update in the instruction counter C01 is completed. Based on this, a new instruction cycle is started.

Next, the processing procedure of the processor in the information processing apparatus 1 of the fifth embodiment configured as described above will be described with reference to FIG.
FIG. 14 is a flowchart showing the processing procedure of the processor in the information processing apparatus according to the fifth embodiment of the present invention.
First, under the instruction of the code analysis program 110, the processor 111 searches and determines whether or not the data at the address specified by the instruction counter C01 is registered in the conversion table T03 (S1301).
As a result, when it is determined that the designated address of the instruction counter C01 is not registered in the conversion table T03 (S1302: NO), the processor 104 stores the address specified by the instruction counter C01 based on the instruction of the code analysis program 110. The executed software instruction 13 is taken out (S1303).
The processor 104 executes the software instruction 13 extracted in S1303 (S1304), finally updates the instruction counter C01 to the next address, and ends one instruction cycle (S1305).

On the other hand, when it is determined that the address specified by the instruction counter C01 is registered in the conversion table T03 (S1302: YES), the processor 104, based on the instruction of the code analysis program 110, uses the registered data in the conversion table T03. The composite software instruction 14 stored in the “composite instruction” column and the address data in the “next IC” column are extracted (S1306).
Next, the processor 104 performs an execution process of the composite software instruction 14 extracted in step S1306 (S1307).
Then, one instruction cycle is completed by setting the designated address of the instruction counter C01 to the address data in the “next IC” column extracted in step S1306 (S1308).

As described above, according to the information processing apparatus 1 of the present embodiment, it has the conversion table T03 and is different from the above-described embodiment in that the composited software instruction 13 is stored in this table area. .
That is, the conversion table T03 stores not only the address information contributing to the order control of the instruction processing but also the composite software instruction 14 in association with these pieces of information.
For this reason, regarding the execution of the composite software instruction 14, it is not necessary to index the instruction again, and the instruction can be directly executed, so that overhead can be suppressed.
As described above, according to the information processing apparatus according to the present embodiment, it is possible to achieve the same effects as those described above even by aspects different from those of the other embodiments described above, and it is also possible to achieve other effects that enhance the function. It has become.

The information processing apparatus according to the present invention has been described with reference to the preferred embodiment. However, the information processing apparatus according to the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the present invention. It goes without saying that implementation is possible.
For example, the information processing apparatus of the present invention is not limited to emulation processing, and can be applied to a wide general computer system.
In addition, the code area according to the present embodiment may be arranged in an external storage medium instead of being arranged in the memory, and may be transmitted / received via an electric communication line or the like as necessary.
As a result, the present invention can be realized in various forms, and a computer system excellent in expandability can be provided.

  The present invention can be suitably used for a computer system including an emulator.

It is the functional block diagram which showed the basic composition of the information processing apparatus corresponding to all embodiment of this invention. It is the 1st block diagram showing the basic composition of the information processor concerning a first embodiment of the present invention. It is the 2nd block diagram which showed the basic composition of the information processing apparatus which concerns on 1st embodiment of this invention. It is the schematic diagram which represented typically the mode of control of the code analysis program which operate | moves on the information processing apparatus which concerns on 1st embodiment of this invention. It is an image figure for demonstrating the compounding process performed in the information processing apparatus which concerns on 1st embodiment of this invention. It is the flowchart which showed the process sequence of the processor in the information processing apparatus which concerns on 1st embodiment of this invention. It is the schematic diagram which represented typically the mode of control of the code analysis program which operate | moves on the information processing apparatus which concerns on 2nd embodiment of this invention. It is the flowchart which showed the process sequence of the processor in the information processing apparatus which concerns on 2nd embodiment of this invention. It is the schematic diagram which represented typically the mode of control of the code analysis program which operate | moves on the information processing apparatus which concerns on 3rd embodiment of this invention. It is the flowchart which showed the process sequence of the processor in the information processing apparatus which concerns on 3rd embodiment of this invention. It is the schematic diagram which represented typically the mode of control of the code analysis program which operate | moves on the information processing apparatus which concerns on 4th embodiment of this invention. It is the flowchart which showed the process sequence of the processor in the information processing apparatus which concerns on 4th embodiment of this invention. It is the schematic diagram which represented typically the mode of control of the code analysis program which operate | moves on the information processing apparatus which concerns on 5th embodiment of this invention. It is the flowchart which showed the process sequence of the processor in the information processing apparatus which concerns on 5th embodiment of this invention. It is the schematic diagram which represented typically the execution process of the software emulation in a normal computer system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Information processing apparatus 10 SW extraction means 11 Compounding means 12 Execution control means 13 Software instruction 14 Composite software instruction 101 Application program 102 Operating system (OS)
103 emulator 104, 111, 112 processor 105 memory 106 SW instruction code area for OS 107 code area for compound SW instruction 108 memory area for emulator 109 IO device 110 code analysis program C01 instruction counter C02 compound instruction counter T01, T03 conversion Table T02 Next IC table

Claims (7)

SW execution means for taking out a software instruction to be executed from now stored in the storage address designated by the instruction counter from one or more software instructions stored in the storage area and executing emulation on the processor;
SW extraction means for extracting a plurality of software instructions that can be collectively executed from the one or more software instructions;
Compounding means for compounding the plurality of software instructions to form a predetermined compound software instruction;
Composite SW storage means for storing the composite software instruction in a second storage area;
From the composite software instructions stored in the second storage area, extract the composite software instruction to be executed which is stored at the second storage address designated by the second instruction counter and execute the emulation. A composite SW execution means for
Table registration means for registering table data indicating an execution process of the software instruction and the composite software instruction;
Execution control means for executing the emulation of the software instruction or the composite software instruction according to an execution process registered in the table data,
The table registration means includes
The storage address of the composite software instruction to be executed in the second storage area, the storage address of the first software instruction constituting the composite software instruction in the storage area, and the storage area of the software instruction to be executed next First table data associated with storage addresses is registered as the table data,
The execution control means includes
If the same storage address as the storage address designated by the instruction counter is not registered in the first table data, the software instruction stored at the storage address is extracted from the storage area and the emulation is performed. Let it run
When the same storage address as the storage address designated by the instruction counter is registered in the first table data, the storage address of the composite software instruction registered in association with the storage address Update the storage address specified by the second instruction counter, extract the composite software instruction stored in the updated storage address from the second storage area, execute the emulation, and execute the emulation. The information processing apparatus updates the storage address designated by the instruction counter with the storage address of a software instruction to be executed next registered in association with the storage address. The composite SW storage means
The composite software instruction constituted by the compounding means is stored in the storage area instead of the first software instruction constituting the composite software instruction,
The table registration means includes
The registered second table data associated storage address in the composite software the storage area of the software instructions to be executed stored addresses and the next in the storage area of instructions exclusively as the table data,
The execution control means includes
When the same storage address as the storage address designated by the instruction counter is not registered in the second table data, the software instruction stored at the storage address is exclusively extracted from the storage area and When emulation is executed and the same storage address as the storage address specified by the instruction counter is registered in the second table data, the composite software instruction stored in the storage address is exclusively Take out from the storage area and execute the emulation, and after executing the emulation, by the storage address in the storage area of the software instruction to be executed next registered in association with the storage address in the second table data Before the instruction counter specifies The information processing apparatus according to claim 1, wherein updating the storage address. The composite SW storage means
The composite software instruction constituted by the compounding means is stored in the storage area in place of the first software instruction constituting the composite software instruction, and a predetermined identification code for preventing duplicate processing is Store in the storage area in place of the software instruction other than the head constituting the software instruction,
The execution control means includes
When software instructions or composite software instructions are stored at the storage address designated by the instruction counter , they are exclusively extracted to execute the emulation, and the identification code is assigned to the storage address designated by the instruction counter. 3. The information processing according to claim 1, wherein the storage address designated by the instruction counter is exclusively updated to the storage address of a software instruction to be executed next. apparatus. The composite SW storage means
The composite software instruction constituted by the compounding means is stored in the storage area in place of the first software instruction constituting the composite software instruction, and is specified next to the storage address for storing the composite software instruction. In the storage address, the storage address of the software instruction to be executed after execution of the emulation for the composite software instruction is stored in the storage area,
The execution control means includes
Wherein when the instruction counter software instructions or composite software instructions to the storage address is specified is stored exclusively, removed these to execute the emulation, the instruction counter software instructions or the storage address specified by When the composite software instruction is not stored, the storage address designated by the instruction counter is updated exclusively by the storage address of the software instruction to be executed next stored in the storage address. Item 4. The information processing device according to any one of Items 1 to 3. The table registration means includes
Corresponding the composite software instruction constituted by the compounding means, the storage address of the first software instruction constituting the composite software instruction in the storage area, and the storage address of the software instruction to be executed next in the storage area a third table data registered exclusively as the table data,
The execution control means includes
If the same storage address as the storage address designated by the instruction counter is not registered in the third table data, the software instruction stored at the storage address is exclusively extracted from the storage area and When the storage address identical to the storage address designated by the instruction counter is registered in the third table data, the third table data is exclusively associated with the storage address. The composite software instruction registered in step S3 is taken out and the emulation is executed. After the emulation is executed, the storage address specified by the instruction counter is registered in association with the storage address in the third table data. Next software life to be executed The information processing apparatus of any one of claims 1 to 4, characterized in that updating the storage address in the storage area. An emulation method for executing emulation of software instructions,
A SW execution step for fetching a software instruction to be executed from now stored in a storage address designated by an instruction counter from one or more software instructions stored in the storage area and executing emulation on the processor;
A SW extraction step of extracting a plurality of software instructions that can be collectively executed from the one or more software instructions;
A compounding step of compounding the plurality of software instructions to form a predetermined compound software instruction;
A composite SW storing step of storing the composite software instruction in a second storage area;
From the composite software instructions stored in the second storage area, extract the composite software instruction to be executed which is stored at the second storage address designated by the second instruction counter and execute the emulation. A composite SW execution step,
A table registration step of registering table data indicating an execution process of the software instruction and the composite software instruction;
An execution control step for executing the emulation of the software instruction or the composite software instruction in accordance with an execution process registered in the table data,
The table registration step includes:
The storage address of the composite software instruction to be executed in the second storage area, the storage address of the first software instruction constituting the composite software instruction in the storage area, and the storage area of the software instruction to be executed next First table data associated with storage addresses is registered as the table data,
The execution control step includes:
If the same storage address as the storage address designated by the instruction counter is not registered in the first table data, the software instruction stored at the storage address is extracted from the storage area and the emulation is performed. Let it run
When the same storage address as the storage address designated by the instruction counter is registered in the first table data, the storage address of the composite software instruction registered in association with the storage address Update the storage address specified by the second instruction counter, extract the composite software instruction stored in the updated storage address from the second storage area, execute the emulation, and execute the emulation. An emulation method comprising: updating the storage address designated by the instruction counter with the storage address of a software instruction to be executed next registered in association with the storage address. Computer
SW execution means for taking out a software instruction to be executed from now stored in a storage address designated by an instruction counter from one or more software instructions stored in the storage area and executing emulation on the processor;
SW extraction means for extracting a plurality of software instructions that can be collectively executed from the one or more software instructions;
Compounding means for compounding the plurality of software instructions to form a predetermined compound software instruction;
Composite SW storage means for storing the composite software instruction in a second storage area;
From the composite software instructions stored in the second storage area, extract the composite software instruction to be executed which is stored at the second storage address designated by the second instruction counter and execute the emulation. Composite SW execution means
Table registration means for registering table data indicating an execution process of the software instruction and the composite software instruction, and execution control for executing the emulation of the software instruction or the composite software instruction in accordance with the execution process registered in the table data Function as a means,
In the table registration means,
The storage address of the composite software instruction to be executed in the second storage area, the storage address of the first software instruction constituting the composite software instruction in the storage area, and the storage area of the software instruction to be executed next First table data associated with storage addresses is registered as the table data,
In the execution control means,
If the same storage address as the storage address designated by the instruction counter is not registered in the first table data, the software instruction stored at the storage address is extracted from the storage area and the emulation is performed. Let it run
When the same storage address as the storage address designated by the instruction counter is registered in the first table data, the storage address of the composite software instruction registered in association with the storage address Update the storage address specified by the second instruction counter, extract the composite software instruction stored in the updated storage address from the second storage area, execute the emulation, and execute the emulation. An emulation program that updates the storage address designated by the instruction counter with the storage address of a software instruction to be executed next registered in association with the storage address.

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