JP5050725B2 - Manufacturing method of build-up printed wiring board - Google Patents

Description

  The present invention relates to a build-up printed wiring board and a method for manufacturing the same. In particular, a multilayer printed wiring board having a fine conductor pattern with a conductor wiring width of 25 μm or less is marketed at a low cost, and the adhesion strength of the conductor wiring layer is improved on the thermosetting insulating resin layer, thereby improving the connection reliability. The present invention relates to an improved build-up printed wiring board and a method for manufacturing the same.

  Conventionally, in the multilayer printed wiring board, in order to improve the adhesion strength between the thermosetting insulating resin layer and the conductor wiring layer, the interface between the copper foil conductor wiring layer and the thermosetting insulating resin layer is roughened, The improvement of the adhesiveness by the anchor effect was aimed at.

  However, in recent years, in the high frequency region, a signal delay problem has been raised due to the skin effect caused by the roughness of the copper wiring surface. In order to cope with high frequency such as a signal delay problem, a low profile (arithmetic average roughness Ra = 3 μm or less) of the interface roughness between the conductor wiring layer and the thermosetting insulating resin layer surface is required. The arithmetic average roughness Ra is measured by a method defined in JIS-B0601-1994. Here, the arithmetic average roughness Ra means that the roughness curve is folded from the center line and expressed by a value obtained by dividing the area obtained by the roughness curve and the center line by the length L.

  Further, in response to demands for higher functionality, miniaturization, weight reduction, and the like for electronic devices, there are increasing demands for higher density and thinner multilayer printed wiring boards incorporated therein. One of multilayer printed wiring boards that meet these requirements is a build-up method. The build-up method is a method of repeating a thermosetting insulating resin layer coat and chemical copper plating. However, in general, the adhesion between the thermosetting insulating resin layer and the conductor wiring layer is low. In particular, in order to achieve high-density wiring, it is required to narrow the conductor wiring width and finer the conductor wiring pitch, and the reliability of the adhesion strength between the extremely narrow conductor wiring layer and the thermosetting insulating resin layer is required. It has become a big problem.

  A commercially available thermosetting insulating resin layer generally contains silica as a filler to suppress thermosetting shrinkage and improve strength. Usually, the thermosetting insulating resin layer is swollen with an oxidizing agent such as a permanganate solution prepared to be strongly alkaline, a part of the filler is dissolved, and the surface of the thermosetting insulating resin layer is roughened. The adhesion strength is maintained by the mechanical anchor effect with the conductor wiring layer by plating.

  Here, it is generally said that the 90 ° peel strength is a minimum of 5.9 N / cm as a standard for reliable adhesion strength of conductive wiring. On the other hand, for example, when the swelling roughening treatment is not performed with a commercially available thermosetting insulating resin layer containing a silica filler, the arithmetic average roughness Ra is 0.2 μm, which is a very smooth surface. When chemical copper plating is performed on this thermosetting insulating resin layer that does not swell and roughen, there is a portion where the catalyst is poorly adhered and the copper plating does not precipitate, or because of the internal stress of the chemical copper plating film during plating. The part may be lifted or peeled off. Thus, when electroless plating is performed on a very smooth thermosetting insulating resin layer, a measure for improving the adhesion strength is required.

  In Patent Document 1, a mixture of heat-resistant particles having an average particle diameter of 2 μm to 10 μm and heat-resistant particles having an average particle diameter of 2 μm soluble in an insulating resin that is hardly soluble in an oxidant, or an average particle By mixing heat-resistant particles with a diameter of 2 μm to 10 μm and pseudo particles of heat-resistant particles with an average particle diameter of 2 μm, a concave portion is provided in the insulating resin layer after the oxidant treatment, and the adhesion is improved by the mechanical anchor effect. ing.

  However, if the interface between the thermosetting insulating resin layer and the conductor wiring layer is uneven as described above, the conductor embedded in the recess of the thermosetting insulating resin layer in the subsequent patterning process of the conductor wiring layer. A part of the wiring layer tends to remain as a residue, and a defect that shorts adjacent conductor patterns occurs.

  Patent Document 2 describes that the adhesion strength between the thermosetting insulating resin layer and the conductor wiring layer is improved by using a silane coupling agent. In this patent document 2, a silane coupling agent treatment is performed on the copper foil surface of the inner layer, and a resin having an unsaturated double bond such as an uncured epoxy resin is coated on the copper foil treated with the silane coupling agent. The adhesive strength is exhibited by thermosetting.

  Thus, the copper foil and the silane coupling agent can be easily coupled. However, on the other hand, the silane coupling effect is not exerted on the resin surface having no unsaturated double bond, and sufficient adhesion strength cannot be obtained even if the conductor wiring layer is formed after that. The conventional build-up method is a method of copper plating as a conductor wiring layer on an insulating resin layer with few unsaturated double bonds, so that there is a problem that adhesion strength cannot be obtained only by the conventional silane coupling method.

  As described above, in general, in order to improve the adhesion strength between the thermosetting insulating resin layer and the conductor wiring layer, the swelling coarseness by a permanganate solution or the like prepared in the thermosetting insulating resin layer with strong alkalinity is provided. Then, a seed layer having a thickness of several μm is formed by chemical copper plating. Further, using a photosensitive resist, a desired conductor wiring pattern is exposed and developed to form a resist pattern, and then an electric potential is applied to the chemical copper plating seed layer exposed from the resist pattern to perform electrolytic copper plating. . Further, an unnecessary resist pattern is stripped with an alkaline solution, and a conductor wiring pattern formed by electrolytic copper plating on the seed layer of chemical copper plating is obtained.

  Here, the chemical copper plating exposed from the patterned electrolytic copper plating in a process generally referred to as flash etching or quick etching (hereinafter referred to as “flash etching”) considered in the present invention. Etch out the seed layer completely.

  In the swelling and roughening step of the thermosetting insulating resin layer performed in the pre-process of this flash etching step, the adhesion strength is improved by improving the roughening of the surface of the thermosetting insulating resin layer and the leakage of the plating solution. Aiming for an effect. However, there is a problem that copper plated in the concave portion of the roughened thermosetting insulating resin layer tends to remain as a residue and a short circuit occurs between adjacent conductor wiring patterns. For this reason, generally in flash etching, the etching time of the chemical copper plating layer is promoted, or the conductor formed by this electrolytic copper plating is selected by selecting an etching solution in which the chemical copper plating is easier to dissolve than the electrolytic copper plating. The chemical copper plating layer exposed between the wiring patterns is completely etched out by flash etching to prevent a short circuit with the adjacent conductor wiring pattern.

  Also, under conditions where the etching of the electrolytic copper plating layer is easy to proceed depending on the flash etching conditions, the chemical copper plating just below the conductor wiring pattern is necessary if the conductor wiring pattern width is narrow or the etching of the chemical copper plating layer is easy to proceed. There was a problem that etching to the layer progressed (undercut), and the adhesion strength of the conductor wiring decreased.

In particular, in the fine conductor wiring pattern having a conductor wiring width of 25 μm or less studied in the present invention, since the replacement of the electrolytic copper plating pattern with a fresh flash etching solution is poor, the etching rate becomes slow, and the electrolytic copper plating Since only this etching proceeds, there is a problem that the conductor wiring pattern becomes thin. In addition, when a portion where the gap between the conductor wiring pattern and the conductor wiring pattern is wide is mixed, there is a problem that this portion has an undercut in the chemical copper plating and a decrease in adhesion strength is observed. In the next manufacturing process, when the thermosetting insulating resin layer is further built up, when the outermost solder resist is coated, or when contacting the workpiece during handling or handling, the conductor wiring pattern that caused the undercut is There is a problem that the conductor wiring pattern is peeled off or falls down to cause a short circuit or an open defect.
Japanese Patent Laid-Open No. 2-188992 Japanese Patent No. 3505135

  The present invention provides an inexpensive and highly reliable build-up printed wiring board that minimizes thinning of the conductor wiring width during flash etching, has high adhesion strength with the insulating resin layer, and does not cause defects, and a method for manufacturing the same. Is to provide.

The invention according to claim 1 of the present invention, providing a substrate provided with inner conductor wiring pattern having a desired shape on both sides of the core layer, forming an insulating resin layer having a desired shape on the both surfaces of the substrate Then, the roughening treatment is performed on the insulating resin layer, irregularities are formed on the insulating resin layer, and conductive wiring seed layers are formed on both surfaces of the insulating resin layer so as to fill the irregular surface of the insulating resin layer. and, on the both surfaces of the conductor wiring seed layer to form a plating resist having a desired shape, to form an outer layer conductor wiring pattern on the non-formation portion of the plating resist having a desired shape, the conductor wiring at temperatures et etching liquid the corrosion potential of the seed layer and the outer layer conductor wiring patterns keep each separately measured, the said conductor wiring seed layer and the outer layer conductor wiring patterns to be formed into a desired shape, when performing selective etching The corrosion potential of the outer layer conductor wiring pattern has a higher etchant temperature than the corrosion potential of the conductor wiring seed layer, and is lower than the corrosion potential of the outer layer conductor wiring pattern and higher than the corrosion potential of the conductor wiring seed layer. Applying a potential to the outer layer conductor wiring pattern portion, etching the conductor wiring seed layer portion that is exposed from the outer layer conductor wiring pattern, and etching of the conductor wiring seed layer is performed immediately below the outer layer conductor wiring pattern. At the time of completion, an unnecessary potential lower than the corrosion potential of the outer layer conductor wiring pattern and the conductor wiring seed layer is applied, and the unnecessary conductor wiring seed layer portion remaining in the irregularities on the surface of the insulating resin outside the outer layer conductor wiring pattern For manufacturing a build-up printed wiring board characterized by etching out

  According to the present invention, an inexpensive and highly reliable build-up printed wiring board that minimizes thinning of the conductor wiring width during flash etching, has high adhesion strength with the insulating resin layer, and does not cause defects, and its A manufacturing method can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the embodiments, the same constituent elements are denoted by the same reference numerals, and redundant description among the embodiments is omitted.

  The object of the present invention is to minimize the etching of the outer layer conductor wiring pattern 7 (electrolytic copper plating) portion during flash etching, and to perform chemical copper plating of the conductor wiring seed layer 5 regardless of the wiring pitch of the conductor wiring pattern 8 or the like. , Uniformly flash-etching.

  As shown in FIGS. 1A to 1D and FIGS. 2A to 2C, it is a method for manufacturing a build-up printed wiring board according to an embodiment of the present invention. First, as shown in FIG. 1A, the core layer 1, the inner layer conductor wiring pattern 2 formed on both surfaces of the core layer 1, and the insulating resin layer 3 are formed on the inner layer conductor wiring pattern 2.

  Examples of the resin used for the core layer 1 and the insulating resin layer 3 include, for example, epoxy resins, phenol resins, polyimide resins, unsaturated polyester resins, polyphenylene ether resins alone, modified products, mixtures, and the like These resins include those containing fillers such as silica and glass fibers, but the present invention is not limited to these.

  As the material of the insulating resin layer 3 according to the embodiment of the present invention, paste-like ink or dry film can be used, but the present invention is not limited to these. The insulating resin layer 3 is coated on the copper wiring pattern layer on which the inner conductor wiring pattern 2 is formed by applying the insulating resin layer 3 supplied with paste-like ink to a coating method such as screen printing, dip coating, or spin coating. It can be coated and pre-baked. Moreover, a dry film can be bonded together using a vacuum laminator so that bubbles are not caught in the copper wiring pattern layer. Here, the insulating resin layer 3 is thermally cured by baking at 180 ° C. for 30 minutes. The copper wiring pattern layer is the inner conductor wiring pattern 2.

  Next, as shown in FIG. 1B, a via hole 4 for connection is formed in the insulating resin layer 3. Although not shown here, a through hole that penetrates the core layer 1 and the insulating resin layer 3 with a drill may be formed.

  Next, the smear generated at the time of forming the via hole 4 is removed by immersion in a heated alkaline aqueous solution (desmear treatment). Next, a connection via between the outer layer conductor wiring pattern 7 and the previously formed inner layer conductor wiring pattern 2 is formed by copper plating by a semi-additive method. There is no polarity on the surface of the insulating resin layer 3 and the leakage of the water-soluble copper plating solution is poor, but the leakage is improved to some extent by desmear treatment, but the effect of roughening the surface is low, and the insulating resin The arithmetic average roughness Ra of the surface of the layer 3 is maintained at 0.5 μm or less.

  Next, as shown in FIG. 1C, after conducting chemical copper plating pretreatment (catalyst formation), a conductor wiring seed layer 5 having a thickness of 1 μm at the maximum is formed on the surface of the insulating resin layer 3 by chemical copper plating. can do. The disadvantage of chemical copper plating is its slow deposition rate and poor industrial mass productivity. For this reason, the electroless plating thickness is desired to be as thick as possible, but in-plane film thickness variation occurs in the mass production process. Therefore, in the embodiment of the present invention, the conductor wiring seed layer 5 of 0.5 μm to 1.0 μm is formed. To do.

  Next, as shown in FIG. 1D, a plating resist 6 of an outer layer conductor wiring pattern 7 having a desired shape is formed on the conductor wiring seed layer 5.

  Next, as shown in FIG. 2A, copper plating is performed to a film thickness having a desired shape by electrolytic copper plating to form an outer layer conductor wiring pattern 7.

  Next, as shown in FIG. 2B, the plating resist 6 of the outer conductor wiring pattern 7 is peeled off.

  Next, as shown in FIG. 2 (C), flash etching is performed at a flash etching solution temperature and a flash etching solution component condition in which the corrosion potentials of chemical copper plating and electrolytic copper plating are aligned, and a desired shape is obtained. An outer layer conductor wiring pattern 7 having the following is formed. Here, the chemical copper plating may be referred to as a conductor wiring seed layer 5, and the electrolytic copper plating may be referred to as an outer layer conductor wiring pattern 7.

  Finally, the insulating resin layer 3 is cured by post-baking at 180 ° C. for 60 minutes.

  As shown in FIG. 3, the corrosion potentials of the chemical copper plating and the electrolytic copper plating are reversed depending on the processing temperature at the processing temperature at the time of the flash etching. Sometimes. By utilizing this processing temperature, chemical copper plating and electrolytic copper plating can be selectively etched, and a copper residue is not generated, and a fine wiring pattern can be selectively produced.

  Since the corrosion potential of electrolytic copper plating is higher and noble than chemical copper plating in a relatively low temperature region, a potential higher than the corrosion potential of chemical copper plating and lower than the corrosion potential of electrolytic copper plating is applied to the electrolytic copper plating portion. By applying, etching of electrolytic copper plating can be prevented and chemical copper plating can be selectively etched.

  In order to improve the adhesion strength between the insulating resin layer 3 and the conductor wiring seed layer 5, the insulating resin layer 3 is subjected to swelling roughening treatment with a permanganate solution or the like prepared in a strong alkalinity. The shape is such that the surface of the insulating resin layer 3 is filled. For this reason, when the chemical copper plating is flash-etched, the chemical copper plating independently exists in a stepping stone shape in the uneven holes on the surface of the insulating resin layer 3.

  When the etching of the chemical copper plating is completed up to just below the electrolytic copper plating pattern, by applying a potential lower than the corrosion potential of the electrolytic copper plating and the chemical copper plating, the electrolytic copper plating of the conductor wiring pattern 8 and the chemical copper immediately below it are applied. Etching of the plating is prevented, and the stepping stone-like chemical copper plating remaining in the uneven holes on the surface of the insulating resin 3 outside the conductor wiring pattern 8 is continuously etched.

  By etching out the chemical copper plating outside the conductor wiring pattern 8 in this way, it is possible to prevent a short circuit due to a stepping stone-like chemical copper plating residue and ion migration between the fine wiring patterns.

EXAMPLES Hereinafter, the present invention will be specifically described with reference to examples, but the present invention is not limited to this description.

  As shown in FIG. 1 (A), the core layer 1 has a product name “MCL-E-679F” manufactured by Hitachi Chemical Co., Ltd. as a glass-epoxy insulating resin substrate having inner-layer conductor wiring patterns 2 provided on both sides. Was used. The product name “HBI-200B” manufactured by Taiyo Ink Manufacturing Co., Ltd. was applied on both surfaces of the core layer 1 with a roll coater and baked at 180 ° C. for 30 minutes to form the insulating resin layer 3. At this time, the thickness of the coated insulating resin layer 3 was about 50 μm.

Next, as shown in FIG. 1B, a laser via hole 4 having a diameter of 90 μm was formed with a CO ₂ laser by aligning a predetermined via pattern with the formed insulating resin layer 3. Further, it was immersed in a 5% sodium hydroxide solution at 60 ° C. for 5 minutes to perform desmear treatment. Here, the arithmetic average roughness Ra of the insulating resin layer 3 was 0.2 μm.

  Next, as a 250 g / L pre-dip solution, it is immersed in a product name “PD-301” manufactured by Hitachi Chemical Co., Ltd., and a product name “HS-202B” manufactured by Hitachi Chemical Co., Ltd. is used as a sensitizer. Immersion treatment was performed.

  Next, as shown in FIG.1 (C), the conductor wiring seed layer 5 was formed by carrying out chemical copper plating for 20 minutes using the product name "CUST-201" by Hitachi Chemical.

Here, as shown in FIG. 1 (D), a photosensitive dry film resist having a thickness of 25 μm, a product name “RY-3325SG” manufactured by Hitachi Chemical Co., Ltd. is bonded onto the conductor wiring seed layer 5 and desired. A photomask for the outer layer conductor wiring pattern 7 to be mounted is placed, exposed at 100 mJ / cm ₂ and developed with a 0.8% sodium carbonate solution at 30 ° C. to form a plating resist 6 of the desired outer layer conductor wiring pattern 7 did.

Next, as shown in FIG. 2A, electrolytic copper plating was performed on the non-formed portion of the plating resist 6 under the following conditions to form an outer layer conductor wiring pattern 7 that was 20 μm thick electrolytic copper.
(Electrolytic plating aqueous solution)
Sulfuric acid 180g / L
Copper sulfate 80g / L
Additive (Kaparaside GL, manufactured by Atotech Japan) 1mL / L
(Electrolytic plating aqueous solution)
Current density 1A / dm ₂
Time 40 minutes Temperature Room temperature

  Further, as shown in FIG. 2B, the plating resist 6 was peeled and removed by dipping in a 5% NaOH aqueous solution at 60 ° C.

  As shown in FIG. 2C, the etching solution temperature is set at 26.0 ° C. to etch out the conductor wiring seed layer 5 exposed from under the peeled plating resist 6, and the surface of the outer layer wiring pattern 7 is corroded. An electric potential of 120 mV was applied, and etching was performed with a sulfuric acid monohydrogen peroxide-based flash etching solution.

  When the conductor wiring seed layer 5 was etched up to the outer layer conductor wiring pattern 7, a corrosion potential was applied to 100 mV, and the conductor wiring seed layer 5 embedded in the uneven surface hole was etched out. Here, a wiring pattern 8 having a two-layer structure composed of the conductor wiring seed layer 5 and the outer layer conductor wiring pattern 7 was formed.

  Undercuts were not observed in the conductor wiring having a conductor width of 20 μm thus obtained, and its strength was measured to be 12.36 mN. When this was converted into 1 cm width, it was 6.18 N / cm, indicating a sufficient strength.

Comparative example

  As in the example, as shown in FIG. 1 (A), the core layer 1 is a glass-epoxy insulating resin substrate provided with inner-layer conductor wiring patterns 2 on both sides. “MCL-E-679F” was used. The product name “HBI-200B” manufactured by Taiyo Ink Manufacturing Co., Ltd. was applied on both surfaces of the core layer 1 with a roll coater and baked at 180 ° C. for 60 minutes to form the insulating resin layer 3. At this time, the thickness of the coated insulating resin layer 3 was about 50 μm.

Next, as shown in FIG. 1B, a laser via hole 4 having a diameter of 90 μm was formed with a CO ₂ laser by aligning a predetermined via pattern with the formed insulating resin layer 3. Further, it was immersed in a 5% sodium hydroxide solution at 60 ° C. for 5 minutes to perform desmear treatment. Here, the arithmetic average roughness Ra of the insulating resin layer 3 was 0.2 μm.

  Next, as a 250 g / L pre-dip solution, it is immersed in a product name “PD-301” manufactured by Hitachi Chemical Co., Ltd., and a product name “HS-202B” manufactured by Hitachi Chemical Co., Ltd. is used as a sensitizer. Immersion treatment was performed.

  Next, as shown in FIG.1 (C), the conductor wiring seed layer 5 was formed by carrying out chemical copper plating for 20 minutes using the product name "CUST-201" by Hitachi Chemical.

Here, as shown in FIG. 1 (D), a photosensitive dry film resist having a thickness of 25 μm, a product name “RY-3325SG” manufactured by Hitachi Chemical Co., Ltd. is bonded onto the conductor wiring seed layer 5 and desired. A photomask for the outer layer conductor wiring pattern 7 to be mounted is placed, exposed at 100 mJ / cm ₂ and developed with a 0.8% sodium carbonate solution at 30 ° C. to form a plating resist 6 of the desired outer layer conductor wiring pattern 7 did.

Next, as shown in FIG. 2A, electrolytic copper plating was performed on the non-formed portion of the plating resist 6 under the following conditions to form an outer layer conductor wiring pattern 7 that was 20 μm thick electrolytic copper.
(Electrolytic plating aqueous solution)
Sulfuric acid 180g / L
Copper sulfate 80g / L
Additive (Kaparaside GL, manufactured by Atotech Japan) 1mL / L
(Electrolytic plating aqueous solution)
Current density 1A / dm ₂
Time 40 minutes Temperature Room temperature

  Further, as shown in FIG. 2B, the plating resist 6 was peeled and removed by dipping in a 5% NaOH aqueous solution at 60 ° C.

  As shown in FIG. 2C, in order to etch out the conductor wiring seed layer 5 exposed from under the peeled plating resist 6, the etching solution temperature is set to 35.0 ° C. and the surface of the outer layer wiring pattern 7 is corroded. An electric potential of 120 mV was applied, and etching was performed with a sulfuric acid monohydrogen peroxide-based flash etching solution.

  When the conductor wiring seed layer 5 was etched up to the outer layer conductor wiring pattern 7, a corrosion potential was applied to 100 mV, and the conductor wiring seed layer 5 embedded in the uneven surface hole was etched out. Here, a wiring pattern 8 having a two-layer structure composed of the conductor wiring seed layer 5 and the outer layer conductor wiring pattern 7 was formed.

  Undercuts were not observed in the conductor wiring having a conductor width of 20 μm obtained in this way, and when the strength was measured, it was easily peeled off to 4.86 mN. When this was converted into 1 cm width, it was 2.43 N / cm and almost no strength was observed.

(A)-(D) are schematic structure sectional drawings which show a part of process of the manufacturing method of the buildup printed wiring board of this invention. (A)-(C) are schematic structure sectional drawings which show a part of process of the manufacturing method of the buildup printed wiring board of this invention. It is a figure which shows each corrosion potential of a conductor wiring seed layer and an outer layer conductor wiring pattern at the process temperature at the time of flash etching.

Explanation of symbols

1 Core layer 2 Inner layer conductor wiring pattern 3 Insulating resin layer 4 Via hole 5 Conductor wiring seed layer (chemical copper plating)
6 Plating resist 7 Outer layer conductor wiring pattern (Electrolytic copper plating)
8 Wiring pattern

Claims (1)

Prepare a substrate provided with an inner layer conductor wiring pattern having a desired shape on both sides of the core layer,
Forming an insulating resin layer having a desired shape on both surfaces of the substrate;
Conducting swelling roughening treatment on the insulating resin layer, forming irregularities on the insulating resin layer, and forming a conductor wiring seed layer on both sides of the insulating resin layer so as to fill the irregular surface of the insulating resin layer And
Forming a plating resist having a desired shape on both sides of the conductor wiring seed layer;
Forming an outer layer conductor wiring pattern in a non-formation portion of the plating resist having a desired shape ;
The corrosion potential of the conductor wiring seed layer at a temperature of d etching liquid and said outer conductor wiring patterns respectively measured separately advance, and said outer conductor wiring pattern and the conductive wiring seed layer to form a desired shape When the etching is selectively performed, the corrosion potential of the outer layer conductor wiring pattern has a higher etchant temperature than the corrosion potential of the conductor wiring seed layer, and is lower than the corrosion potential of the outer layer conductor wiring pattern. Applying a potential higher than the corrosion potential of the wiring seed layer to the outer layer conductor wiring pattern portion, etching the conductor wiring seed layer portion formed exposed from the outer layer conductor wiring pattern,
When the etching of the conductor wiring seed layer is completed immediately below the outer layer conductor wiring pattern, a potential lower than the corrosion potential of the outer layer conductor wiring pattern and the conductor wiring seed layer is applied, and an insulating resin outside the outer layer conductor wiring pattern A method for manufacturing a build-up printed wiring board, comprising etching out unnecessary conductive wiring seed layer portions remaining in the surface irregularities .

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