JP5056489B2 - Insulation reliability evaluation structure of printed circuit board interlayer connection circuit and its insulation reliability evaluation test method - Google Patents

Description

  The present invention relates to an insulation reliability evaluation structure of a printed wiring board interlayer connection circuit portion and an insulation reliability evaluation test method using the same. More specifically, an insulation reliability evaluation structure effective for conducting an electromigration test of an interlayer connection circuit portion formed in a narrow position where the inter-wall insulation distance between through vias is 0.1 mm or less, and insulation using the same The present invention relates to a reliability evaluation test method.

In recent years, with the improvement in performance and miniaturization of electronic devices, there has been an increasing demand for precision in circuit design of printed circuit boards.
Along with such refinement, a fine pitch circuit design of a printed circuit board and a narrow pitch design such as a via are required, and high insulation reliability of the circuit board is also required.
As an example of such a substrate, a glass epoxy laminate using glass cloth or the like as a raw material can be given. However, when this substrate is employed, glass filaments are present in the resin, which is an insulator, and CAF (Conductive Anodic Filament) occurs along the fibers from the anode toward the cathode, which may cause insulation deterioration. .
Therefore, an insulation reliability evaluation test method for evaluating whether or not a substrate used for an electronic device or the like does not cause such insulation deterioration has been proposed.

In general, when evaluating the insulation reliability of the printed wiring board interlayer connection circuit portion with respect to the copper-clad laminate, the insulation reliability evaluation structure of the printed wiring board interlayer connection circuit as shown in FIGS. Hereinafter, an insulation structure is measured by applying a voltage to the wiring under a moisture absorption environment set to an appropriate humidity and temperature.
8 is a perspective plan view of the conventional evaluation structure, FIG. 9 is a cross-sectional view of the evaluation structure corresponding to the d-section position line shown in FIG. 8, and FIG. 10 is the e-section position shown in FIG. 11 is a cross-sectional view of the evaluation structure corresponding to the line, and FIG. 11 is a cross-sectional view of the evaluation structure corresponding to the f cross-section position line shown in FIG.

The conventional evaluation structure will be described with reference to these drawings. As can be seen from the perspective plan view of the evaluation structure shown in FIG. 8, the upper first conductor layer 11 (solid line portion) and the lower first structure are shown. Wirings for electric circuits (hereinafter referred to as electric wirings) respectively provided on the two conductor layers 12 (chain line portions) (hereinafter also referred to as outer layer conductor layers 11 and 12) are through vias. Through a conductor layer 15 provided on the inner wall of 14, a serial chain wiring is provided in parallel. When this evaluation structure is seen in FIGS. 9 and 10, it has an internal insulating layer 10, and electric wiring is provided on the first conductor layer 11 on one side and the second conductor layer 12 on the other side, respectively. The provided copper-clad laminate is provided with a through via 14 for an interlayer connection circuit having the conductor layer 15. As a result, each electrical wiring provided in the outer conductor layers 11 and 12 is connected to the through via 14. A chain wiring in series is formed via As shown in FIG. 11, the series chain wirings are provided in parallel while maintaining the inter-wall insulation distance H between the through vias.
In this conventional evaluation structure manufacturing method, a through via 14 is formed in the copper-clad laminate, a conductor layer is formed on the inner wall and the outer conductor layer of the through via 14 by plating or the like, and then the outer conductor is formed. An etching-resistant resist layer (not shown) is formed on the layer, baked, developed, formed into a predetermined pattern, and then subjected to processes such as etching, peeling, etc. It may also be referred to as an outer layer circuit). Reference numerals 16 and 17 are portions to be terminals.
In this outer conductor layer etching process, in order to prevent the conductor layer 15 provided on the inner wall of the through via 14 from being etched, when the outer layer circuit is patterned on the resist layer formed on the outer conductor layer, the through layer 14 is not penetrated. A method of masking the entrance of the via 14 is employed.
In such an embodiment, the land 13 having a diameter larger than the opening diameter of the through via 14 is formed in the connection portion of the interlayer connection circuit in the outer layer circuit, but the nearest land line provided in the adjacent serial chain wiring is formed. When the insulation distance H between the walls between the through vias 14 can be set to about 0.15 mm to 0.5 mm, the insulation reliability can be evaluated by carefully drilling holes when producing the printed wiring board.
However, with the recent refinement, if it is attempted to evaluate the insulation reliability when the insulation distance H between the walls is narrower, it becomes difficult to secure the insulation distance at the land 13 portion.

On the other hand, for example, Patent Document 1 and Patent Document 2 have been proposed as a method of manufacturing a landless through hole in which no land is provided on the surface layer.
These manufacturing methods require an advanced printing alignment technique for reliably connecting the through-hole and the outer layer circuit, and it has been difficult to easily produce an evaluation structure with these manufacturing methods.

  In order to increase the accuracy of the insulation reliability test, the outer layer circuit portion is covered with a solder resist layer to suppress insulation deterioration other than the interlayer connection circuit portion caused by condensation or surface contamination. However, with this method, if the insulation reliability of the solder resist is inferior to that of the substrate, or if the compatibility between the solder resist and the substrate is not appropriate, a high-accuracy test will affect the insulation reliability test results. The result is not obtained.

Japanese Patent No. 2583365 JP-A-8-288644

  Even if the insulation reliability evaluation test of the interlayer connection circuit portion in the evaluation structure is narrower than before, for example, the insulation distance between adjacent vias of 0.1 mm or less, high accuracy and high It is an object of the present invention to provide an evaluation structure capable of performing a reliable insulation evaluation test, and an evaluation test method using the same.

  The inventor sets the width of the chain wiring to be equal to or smaller than the diameter of the through via provided in the chain wiring, provides a surface insulating layer made of prepreg on the outer conductive layer, and ends of the conductive layer provided on the inner wall of the through via It has been found that an evaluation structure having an inner layer side of the surface insulating layer can achieve the object. The present invention has been completed based on such findings.

That is, the present invention
1. A plurality of electrical wirings are formed on the first conductor layer on one side of the copper-clad laminate having an insulating layer inside, and a plurality of electrical wirings are formed on the second conductor layer on the other side. A series chain wiring in which the electrical wiring of the first conductor layer and the second conductor layer of the inner layer circuit-containing substrate provided with the surface insulating layer is alternately connected through through vias having a conductor layer on the inner wall. A printed wiring board interlayer connection circuit evaluation structure formed, wherein each electric wiring width connected to the through via is equal to or smaller than the diameter of the through via, and a conductor layer provided on an inner wall of the through via An insulating reliability evaluation structure of a printed wiring board interlayer connection circuit portion, wherein the end portion of the printed wiring board is on the inner layer side of the surface of the surface insulating layer,
2. 2. The print according to 1 above, wherein an insulation distance between walls of a through via provided in the serial chain wiring and a nearest through via provided in an adjacent serial chain wiring is 0.03 mm to 0.1 mm. Insulation reliability evaluation structure of wiring board interlayer connection circuit part,
3. Insulation reliability evaluation structure of printed wiring board interlayer connection circuit part according to 1 or 2, wherein the diameter of the through via is 0.15 mm or less,
4). The printed wiring board interlayer according to any one of the above items 1 to 3, wherein the inner insulating layer includes a glass cloth, and the thickness of the glass cloth is 0.05 mm or less, and the insulating layer thickness is 0.1 mm or less. Insulation reliability evaluation structure of connection circuit section,
5. The printed wiring board interlayer according to any one of the above 1 to 4, wherein the surface insulating layer includes a glass cloth, the insulating layer has a thickness of 0.1 mm or less, and the glass cloth has a thickness of 0.05 mm or less. Insulation reliability evaluation structure of connection circuit section,
6). The chain arrangement is formed by alternately connecting a positive electrode and a negative electrode of a power source to a plurality of series chain wires of the insulation reliability evaluation structure according to any one of the above 1 to 5, and applying a voltage under moisture absorption conditions. Insulation reliability evaluation test method for printed circuit board interlayer connection circuit part, characterized by measuring moisture absorption insulation resistance between,
7). The insulation reliability evaluation test method for a printed wiring board interlayer connection circuit portion according to the above 6, which measures insulation deterioration due to CAF,
It is about.

  The present invention provides an evaluation structure capable of performing a high-accuracy and high-reliability insulation evaluation test even when the insulation distance between adjacent through via walls adjacent to each other is narrower than before, for example, 0.1 mm or less. And an evaluation test method using the same.

The present invention will be described with reference to the drawings.
First, FIG. 1 is a diagram for explaining terms in the present invention. In the present invention, the insulation distance between walls is the insulation distance between inner walls when drilling (H in FIG. 1), and the diameter of the hole is The diameter of a drill hole (through via) (M in FIG. 1). Furthermore, the pitch interval in the present invention is the distance between the centers of the holes when drilling (N in FIG. 1).
2-7 is a figure which shows the evaluation structure of this invention.
2 is a perspective plan view of the evaluation structure of the present invention, FIG. 3 is a cross-sectional view of the evaluation structure of the present invention corresponding to the a cross-section position line shown in FIG. 2, and FIG. 4 is a b cross-section shown in FIG. 5 is a cross-sectional view of the evaluation structure of the present invention corresponding to the position line, FIG. 5 is a cross-sectional view of the evaluation structure of the present invention corresponding to the c-section position line shown in FIG. 2, and FIG. 7 and 7 are partial sectional perspective views of FIG.
The evaluation structure of the present invention will be described with reference to the perspective plan view of FIG. 2. The electrical wiring provided on the first conductor layer 4 on the upper side indicated by the solid line part and the second on the lower side indicated by the chain line part. The electrical wiring provided in the conductor layer 5 forms a chain wiring in series via the through via 6 having the conductor layer 7 on the inner wall, and these are provided in parallel. In the present invention, each electric wiring width of the first conductor layer 4 and the second conductor layer 5 (hereinafter, sometimes referred to as outer conductor layers 4 and 5) is equal to or less than the diameter of the through via 6. .
When the evaluation structure of the present invention is viewed from the cross-sectional views of FIGS. 3 and 4, electrical wiring is provided on the outer conductor layers 4 and 5 of the inner insulating layer 1 of the copper-clad laminate, and the outer conductor layers 4 and 5 are The upper part is covered with a surface insulating layer 2 made of prepreg. The electric wiring forms a series chain wiring connected by the through via 6.
Furthermore, in the structure of the present invention, as shown in FIG. 5, serial chain wirings are provided in parallel while maintaining an inter-wall insulating distance H between through vias. As a result, it is possible to perform an insulation evaluation test in this portion by alternately connecting different types of power supplies to the respective series chain wirings during the evaluation test.
FIG. 6 is an enlarged view of a circled portion in FIG. 3, and the end portion of the conductor layer 7 provided on the inner wall of the through via 6 is on the inner layer side by a distance L from the surface 3 of the surface insulating layer 2. . As this distance L,
It is preferably about 1/3 to 2/3 of the thickness of the surface insulating layer and is usually about 20 to 40 μm, but is not limited thereto.
By providing the end portion of the conductor layer 7 provided on the inner wall of the through via on the inner layer side from the surface 3 of the surface insulating layer 2, it is possible to prevent the influence of condensation and surface contamination without providing a solder resist layer. Can do.
From FIG. 7, which is a partial sectional perspective view of FIG. 3, the electrical wiring of the outer conductor layers 4 and 5 is provided so as to form a serial chain wiring via a through via 6 having the conductor layer 7 on the inner wall. I understand that. It can also be seen that the end portion of the conductor layer 7 provided on the inner wall of the through via 6 is on the inner layer side of the surface 3 of the surface insulating layer 2.

In the present invention, as shown in FIGS. 3 and 4, the inner layer circuit-containing substrate in which the surface insulating layer 2 made of prepreg is provided on the upper layer of the copper-clad laminate in which the electric wiring is formed on the outer conductor layers 4 and 5. On the other hand, the through via 6 having the conductor layer 7 is formed on the inner wall, and the electric wirings of the outer conductor layers 4 and 5 are connected by the conductor layer 7 provided on the inner wall of the through via 6. The width of each electric wiring can be made equal to or smaller than the diameter of the through via 6, thereby facilitating landless connection. As a result, the minimum insulation distance between a plurality of serial chain wirings becomes the insulation distance H between adjacent vias as it is, so that an interlayer connection circuit having H of 0.03 to 0.1 mm can be formed. become.
When the insulation distance H between the walls is within this range, the electric wirings of the outer conductor layers 4 and 5 can be formed relatively easily, and it is possible to accurately evaluate the insulation deterioration due to CAF.
Further, if the diameter of the through via 6 is preferably 0.15 mm or less, the through via can be formed with high hole position accuracy, and the above-described insulation distance H between the walls can be easily secured. .
In the present invention, the surface insulating layer 2 made of prepreg is provided on the outer layer circuit layer, and the end portion of the conductor layer 7 provided on the inner wall of the through via 6 is more than the surface 3 of the surface insulating layer 2. By providing only the distance L on the inner layer side, it is not necessary to provide a solder resist layer for preventing dew condensation and surface contamination, and it is possible to suppress the occurrence of insulation deterioration factors other than CAF. As described above, the distance L is preferably about 1/3 to 2/3 of the thickness of the surface insulating layer and is usually about 20 to 40 μm. The procedure for providing this distance L will be described below.
As described above, after the through via 6 is provided, the entire inner layer circuit-containing substrate is plated. As a result, the conductor layer 7 is formed on the inner wall of the through via 6 and the surface insulating layer 2. Then, the inside of the through via 6 is filled with an etching resistant filling agent, and the substrate is heated to fill the filling agent. Is cured. Next, both surfaces of the substrate are polished so that the surface of the conductor layer on the surface insulating layer 2 and the end of the filling agent are made flat by polishing, and then etched with an etching agent such as a ferric chloride solution. Remove the layer. At this time, the conductor layer on the surface insulating layer 2 is etched from the surface, whereas side etching is added to the etching from the surface at the interface between the filling agent in the through via 6 and the conductor layer 7. Therefore, etching proceeds in the direction of the inner wall of the through via 6. For this reason, at the stage where all the conductor layers on the surface insulating layer 2 are etched, the etching depth of the conductor layer 7 in the portion in contact with the hole filling agent becomes deeper than the surface 3 of the surface insulating layer 2, resulting in penetration The end portion of the conductor layer 7 provided on the inner wall of the via 6 is formed on the inner layer side of the surface 3 of the surface insulating layer 2.
This distance L is such that the thickness of the surface insulating layer 2 is 5 to 15 μm when the surface of the conductor layer on the surface insulating layer 2 and the end of the hole-filling agent are polished to the same plane by using a leveling machine or the like. Can be controlled.

In the evaluation structure of the present invention, the laminated plate for the copper-clad laminate is made of woven fabric or paper such as glass cloth or felt, and thermosetting resin such as epoxy resin, polyimide resin, phenol resin, or melanin resin. Laminates containing prepregs can be used.
Moreover, the same thing as the above can also be employ | adopted for the prepreg used for the surface insulating layer 2 used by this invention. In particular, when measuring the influence of CAF, it is preferable to use the same resin composition as that of the internal insulating layer as the resin used for the prepreg of the surface insulating layer in order to eliminate other influencing factors as much as possible.
Only one such laminate or prepreg may be used, or a plurality of such laminates or prepregs may be laminated if necessary.
Examples of the preferable laminate include a glass epoxy laminate and a glass composite laminate.
When the thickness of the glass cloth of these laminated plates and prepregs is 0.05 mm or less, and the thickness of each insulating layer is 0.1 mm or less, when the through via 6 is provided, the glass cloth is separated from the wall surface of the through via 6. This is preferable because cracks generated at the interface with the thermosetting resin can be reduced and the occurrence of insulation failure due to permeation such as plating when forming the interlayer connection circuit can be suppressed.
By adopting a laminate including the surface insulating layer, it is possible to measure insulation deterioration due to CAF in particular. In particular, when measuring insulation degradation due to CAF, the evaluation structure of the present invention has a prepreg on the surface insulating layer for the reasons that 1) the result can be obtained quickly and 2) the influence of the thickness of the substrate is small. Yes.

Next, an evaluation test method using the evaluation structure of the present invention will be described.
As shown in FIGS. 2 to 4, power supply connection terminals 8 and 9 are alternately provided at one end of each chain wiring end provided in the inner layer of the evaluation structure of the present invention. Therefore, after exposing them, the positive or negative pole of the power source is connected to the terminal of any one of the chain wirings. Next, the negative pole or positive pole of the power supply is connected to the terminal of the serial chain wiring adjacent to the serial chain wiring. In this way, normally, an inverse power supply is connected to every series of chain wirings constituting the inner layer circuit for each adjacent chain wiring.
Next, a voltage is applied from this power source, and the time during which the insulation resistance value is below a certain value is measured. From the result, the lifetime of the evaluation structure subjected to the test can be calculated.
In the evaluation test, the evaluation test atmosphere is a moisture absorption condition so that the deterioration acceleration condition is satisfied. Specifically, a steady humidification test such as a temperature of 85 ° C. and a humidity of 85% RH or 40 ° C. and 90 to 95% RH is adopted. Furthermore, the semiconductor mounting substrate can employ a high accelerated life test (HAST) such as a temperature of 110 to 130 ° C. and a humidity of 85% RH assuming an evaluation test of a semiconductor device.

  As described above, the evaluation structure of the present invention is a sufficiently practical evaluation structure even if it is an interlayer connection circuit portion having an inter-wall insulation distance H of 0.03 to 0.1 mm between through vias. It is possible to perform an insulation reliability evaluation test using the above, particularly an insulation deterioration performance test by CAF with high accuracy and high reliability.

  EXAMPLES The present invention will be specifically described below with reference to examples, but the present invention is not limited to these examples.

Example 1
Inside, 100 parts by mass of cresol novolac type epoxy resin (trade name YDCN703 of Toto Kasei Co., Ltd.) and 64 parts by mass of bisphenol A type epoxy resin (trade name Epocoat 828 of Japan Epoxy Resin Co., Ltd.) and bisphenol A type novolak resin (Dainippon) Ink Chemical Industries, Ltd., trade name VH-4150) consisting of 94 parts by mass of halogen-free epoxy resin composition consisting of 0.8 parts by mass of 2-ethyl-4-methylimidazole and one glass cloth having a thickness of 0.05 mm. Using a copper-clad laminate including an insulating layer (thickness 0.07 mm), an etching-resistant resist layer (not shown) is formed on the outer conductor layer, baked, developed, and formed into a predetermined pattern Then, after passing through processes such as etching and peeling, a pitch interval of 0.1 mm is provided on one side of the laminate. 0.15 mm, length 1 mm, the electrical wiring of the chain linear first conductor layer having a thickness of 0.018 mm, in parallel to a plurality formed in walls insulation distance 0.05 mm. In addition, when through vias having conductors are provided on the inner wall as shown in FIGS. 2 to 4 on the other different surface, the electric wirings of these outer conductor layers are connected to each other to form a serial chain wiring. In the same manner as the electrical wiring of the first conductor layer, a plurality of electrical wirings of the second conductor layer were formed in parallel with the wiring of the first conductor layer.
Next, on each upper layer of the electric wiring of the outer conductor layer, each prepreg made of the halogen-free epoxy resin composition and a glass cloth having a thickness of 0.05 mm is laminated as a surface insulating layer, and the electric wiring of the outer conductor layer is An inner layer circuit-containing substrate to be an inner layer was produced.
Next, a through via (diameter of 0.1 mm) for connecting each electric wiring of the outer layer conductor layer is provided on the inner layer circuit-containing substrate so that the insulation distance between walls is 0.05 mm, and then plated. A conductor layer (thickness 0.02 mm) was formed on the inner wall surface of the through via and the surface insulating layer surface.
Next, using a squeegee, the through-via was filled with an etching-resistant filling agent (manufacturer name: Clariant Japan, trade name: AZ10XT), and then the substrate was heated to cure the filling agent. Next, both surfaces of the substrate were polished so that the conductor layer on the surface insulating layer and the end portion of the filling agent were flush with each other. At that time, the distance from the surface of the surface insulating layer to the surface of the conductor layer on the surface insulating layer was adjusted to 10 μm using a leveling machine. Thereafter, etching was carried out with a ferric chloride solution to remove the surface conductor layer. As a result, the conductor layer end portion of the inner wall of the through via was formed on the inner layer side of 20 μm from the surface of the surface insulating layer.
Thereafter, the hole filling agent was removed with a stripping solution (manufacturer name: Clariant Japan, product name: AZ remover), and each electric wiring of the outer layer conductor layer was alternately connected via through vias having a conductor layer on the inner wall. An evaluation structure in which series chain wiring is formed was produced.

Example 2
An evaluation structure was produced in the same manner as in Example 1 except that the inter-wall insulation interval between through vias of a plurality of serial chain wirings was set to 0.075 mm.

Example 3
An evaluation structure was produced in the same manner as in Example 1 except that the inter-wall insulation interval between through vias of a plurality of serial chain wirings was set to 0.1 mm.

Example 4
Copper-clad laminate is 100 parts by mass of cresol novolac type epoxy resin (trade name YDCN703 of Toto Kasei Co., Ltd.) and 135 parts by mass of tetrabromobisphenol A type epoxy resin (trade name Epiclin 153 of Dainippon Ink & Chemicals, Inc.) and bisphenol. Bromine-containing epoxy resin composition consisting of 94 parts by mass of type A novolac resin (trade name VH-4150, Dainippon Ink and Chemicals, Inc.) and 0.8 parts by mass of 2-ethyl-4-methylimidazole (bromine content 20% by mass) ) And one glass cloth having a thickness of 0.05 mm, and the surface insulating layer formed on each electric wiring of the outer conductor layer is composed of the bromine-containing epoxy resin composition and a glass having a thickness of 0.05 mm. An evaluation structure was produced in the same manner as in Example 1 except that the prepreg was made of one cloth.

Example 5
The copper-clad laminate was changed to the one containing the bromine-containing epoxy resin composition and one glass cloth having a thickness of 0.05 mm, and the surface insulating layer formed on each electric wiring of the outer conductor layer was replaced with the bromine-containing epoxy. An evaluation structure was produced in the same manner as in Example 2 except that the prepreg was composed of a resin composition and one glass cloth having a thickness of 0.05 mm.

Example 6
The copper-clad laminate was changed to the one containing the bromine-containing epoxy resin composition and one glass cloth having a thickness of 0.05 mm, and the surface insulating layer formed on each electric wiring of the outer conductor layer was replaced with the bromine-containing epoxy. An evaluation structure was produced in the same manner as in Example 3 except that the prepreg was changed to a resin composition and one glass cloth having a thickness of 0.05 mm.

Comparative Example 1
Inside, 100 parts by mass of cresol novolac type epoxy resin (trade name YDCN703 of Toto Kasei Co., Ltd.) and 64 parts by mass of bisphenol A type epoxy resin (trade name Epocoat 828 of Japan Epoxy Resin Co., Ltd.) and bisphenol A type novolac resin (Dainippon) Ink Chemical Industries, Ltd., trade name VH-4150) consisting of 94 parts by mass of halogen-free epoxy resin composition consisting of 0.8 parts by mass of 2-ethyl-4-methylimidazole and 3 pieces of glass cloth having a thickness of 0.05 mm. A plurality of through vias (diameter: 0.1 mm) are formed in parallel at a predetermined position in a copper-clad laminate with an insulating layer thickness of 0.21 mm so that the insulation distance between the walls is 0.1 mm, and then through vias are plated. A metal conductor layer having a thickness of 0.02 mm was formed on the wall surface and the surface of the copper-clad laminate. Next, an etching-resistant resist layer is formed on the outer conductor layer, baked and developed to form a predetermined pattern, and after masking the through-via entrance, the copper is subjected to etching, peeling, and the like. On one surface of the laminated laminate, the through-via is parallel to the wiring width of 0.1 mm, the land diameter of 0.15 mm, and the distance between the adjacent via vias of the nearest chain wiring is 0.05 mm. In the same manner as in Example 1, an electrical wiring of a chain-line-shaped first conductor layer was formed so as to be connected, and the other surface of the copper-clad laminate was also alternately connected through through vias in the same manner as described above. An electric wiring of the second conductor layer was formed so as to form a series chain wiring, and an evaluation structure body of an outer layer circuit connection type was produced.

Comparative Example 2
It is formed so that the insulation distance between the walls between the through vias of adjacent series chain wirings is 0.15 mm, and the lands of the through vias of the chain wiring are arranged in parallel with an insulation distance of 0.1 mm and connected to the through vias. An evaluation structure that is an outer layer circuit connection type was produced in the same manner as in Comparative Example 1 except that it was formed as described above.

Exposing the terminals of the evaluation structures of Examples 1 to 6 and Comparative Examples 1 and 2 manufactured as described above, applying a voltage of 6 V by alternately connecting the positive and negative electrodes of the electrodes, The moisture absorption insulation resistance between the chain wires was measured with an insulation resistance meter under the moisture absorption conditions of a humidity of 85% RH and a temperature of 110 ° C.
The results are shown in the column of insulation deterioration start time and insulation deterioration state in Table 1. In addition, the determination of insulation deterioration was made such that the moisture absorption insulation resistance value was 10 ⁶ Ω or less.

  As can be seen from the results of the comparative examples in Table 1, the insulation distance between the walls was 0.15 mm (the minimum insulation distance between the lands was 0.1 mm). At 1 mm (minimum insulation distance between lands of 0.05 mm), insulation deterioration due to dendrite occurred in the land portion of the first conductor circuit after 73 hours had passed. On the other hand, in Examples 1 to 3 in which the same halogen-free resin as that in the comparative example constitutes the inner insulating layer, the insulation deterioration did not occur until 500 hours even when the insulation distance between the walls was 0.05 to 0.1 mm. Moreover, when the insulating layer is an example of a halogen-containing resin, in Example 4 where the insulation distance between walls is 0.05 mm, insulation deterioration occurs due to CAF after 165 hours, and the insulation distance between walls is 0.075 mm. In Example 5, the insulation deterioration due to CAF occurred when 346 hours passed, and in Example 6 where the insulation distance between the walls was 0.1 mm, the insulation deterioration caused by CAF occurred after 480 hours. From these facts, it is confirmed that the present invention is suitable for evaluating the level of CAF generated in the interlayer connection circuit portion, and it is confirmed that there is a difference in the ease of CAF generation between the halogen-free resin and the halogen-containing resin. did it. In addition, it was confirmed that the present invention hardly causes an insulation deterioration factor other than CAF as in Comparative Example 1.

As described above, the present invention provides a surface insulating layer made of a prepreg on the outer conductor layer, wherein the width of the electric wiring connected to the through via provided in the serial chain wiring serving as an electric circuit is equal to or smaller than the diameter of the through via. And the end of the conductor layer provided on the inner wall of the through via is an evaluation structure that is on the inner layer side of the surface of the surface insulating layer. The insulation distance between the walls between the vias can be set to a very small value, for example, 0.1 mm or less. In addition, since the surface insulating layer made of prepreg is provided on the upper layer of the copper-clad laminate, the solder resist layer is provided. There is no need to form. Further, since the end portion of the conductor layer on the inner wall of the through via is provided on the inner layer side with respect to the surface of the surface insulating layer, the evaluation test is not affected by condensation or surface contamination.
As a result, in the insulation reliability evaluation test using the evaluation structure of the present invention, insulation deterioration due to CAF can be evaluated with high accuracy and high reliability.

The figure explaining the terminology of the present invention Perspective plan view of insulation reliability evaluation structure of printed wiring board interlayer connection circuit of the present invention Sectional drawing of the insulation reliability evaluation structure of the printed wiring board interlayer connection circuit applicable to a cross-section position line shown in FIG. Sectional drawing of the insulation reliability evaluation structure of the printed wiring board interlayer connection circuit applicable to b cross-section position line shown in FIG. Sectional drawing of the insulation reliability evaluation structure of the printed wiring board interlayer connection circuit applicable to c cross-section position line shown in FIG. Enlarged view of ○ in Figure 2 Partial cross-sectional perspective view of FIG. Perspective plan view of insulation reliability evaluation structure of printed wiring board interlayer connection circuit of conventional example Sectional drawing of the insulation reliability evaluation structure of the printed wiring board interlayer connection circuit applicable to d cross-section position line shown in FIG. Sectional drawing of the insulation reliability evaluation structure of the printed wiring board interlayer connection circuit applicable to e cross-section position line shown in FIG. Sectional drawing of the insulation reliability evaluation structure of the printed wiring board interlayer connection circuit applicable to the f cross-section position line shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Inner insulating layer 2 of copper clad laminated board 2 Surface insulating layer 3 Surface insulating layer surface 4 First conductor layer 5 Second conductor layer 6 Through-via 7 Conductor layer 8 Terminal 9 Terminal a Position side line of chain wiring on the positive side b Chain wiring sectional view position line on the negative side c Penetration via on the positive side, narrow pitch section sectional view of the through via on the negative side 10 Inner insulating layer 11 First conductor layer 12 Second conductor layer 13 Land 14 Through-via 15 Conductor layer 16 Terminal 17 Terminal d Chain wiring cross-sectional view position line e on the positive side Chain wiring cross-sectional view position line f on the negative side Through-via on the positive side, narrow pitch section cross-section of the through via on the negative side Figure position line

Claims (7)

  A plurality of electrical wirings are formed on the first conductor layer on one side of the copper-clad laminate having an insulating layer inside, and a plurality of electrical wirings are formed on the second conductor layer on the other side. A series chain wiring in which the electrical wiring of the first conductor layer and the second conductor layer of the inner layer circuit-containing substrate provided with the surface insulating layer is alternately connected through through vias having a conductor layer on the inner wall. A printed wiring board interlayer connection circuit evaluation structure formed, wherein each electric wiring width connected to the through via is equal to or smaller than the diameter of the through via, and a conductor layer provided on an inner wall of the through via An insulating reliability evaluation structure for a printed wiring board interlayer connection circuit section, wherein an end of the printed wiring board is on the inner layer side of the surface of the surface insulating layer.   The inter-wall insulation distance between a through via provided in the series chain wiring and a nearest through via provided in an adjacent series chain wiring is 0.03 mm to 0.1 mm. Insulation reliability evaluation structure of printed circuit board interlayer connection circuit section.   The insulation reliability evaluation structure for a printed wiring board interlayer connection circuit part according to claim 1 or 2, wherein the diameter of the through via is 0.15 mm or less.   The printed wiring board according to claim 1, wherein the inner insulating layer includes a glass cloth, and the thickness of the glass cloth is 0.05 mm or less, and the insulating layer thickness is 0.1 mm or less. Insulation reliability evaluation structure of interlayer connection circuit.   5. The printed wiring board according to claim 1, wherein the surface insulating layer includes a glass cloth, the insulating layer has a thickness of 0.1 mm or less, and the glass cloth has a thickness of 0.05 mm or less. Insulation reliability evaluation structure of interlayer connection circuit.   The chain of the insulation reliability evaluation structure according to any one of claims 1 to 5, wherein a positive electrode and a negative electrode of a power source are alternately connected to each other, and a voltage is applied under a moisture absorption condition, thereby the chain. An insulation reliability evaluation test method for a printed wiring board interlayer connection circuit portion, characterized by measuring a hygroscopic insulation resistance between wirings.   The insulation reliability evaluation test method for printed wiring board interlayer connection circuit portions according to claim 6, wherein the insulation deterioration due to CAF is measured.

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