JP5061480B2 - Semiconductor memory device and method for manufacturing semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, in particular, a semiconductor memory device using a floating gate and a tunnel oxide film, and a method for manufacturing the semiconductor memory device.

  In a nonvolatile semiconductor memory device having a floating gate, high-speed writing / erasing, long-term information retention and low power consumption are required. As one means for satisfying these requirements, a memory structure (DTM) using a direct tunnel current has been studied (for example, see Patent Documents 1-3 below).

Conventionally, in a memory using a direct tunnel current, an insulating film for separating a floating gate from a conductive path between a source and a drain is formed thinner than a normal gate oxide film and is called a tunnel insulating film. When a floating gate is formed on such a thin tunnel insulating film, in order to store information, that is, the charge in the floating gate for a long time, the impurity concentration in the floating gate is made lower than a predetermined value, and the floating gate is depleted. It was proposed to do.
JP 2000-150680 A JP 2001-168213 A JP 2002-16155 A JP 2000-219275 A Japanese Patent Laid-Open No. 10-312972 Japanese Patent Publication No. 06-020117 JP 2004-282100 A JP 59-125648 A Japanese Patent No. 3339361

  It has been predicted to some extent that depletion of the floating gate results in an increase in the resistance value of the floating gate and slightly deteriorates the writing speed and the erasing speed. On the other hand, depletion of the floating gate has a great effect of improving the retention characteristics, and therefore depletion of the floating gate has been promoted.

  However, it has been found that when the depletion progresses, the deterioration of the erasing speed becomes more significant than the writing speed. In addition, it has been found that as depletion progresses, variation in threshold values of transistors increases. Therefore, an object of the present invention is to suppress the deterioration of the erase speed and the variation of the threshold value while proceeding with depletion.

  The present invention employs the following means in order to solve the above problems. That is, the present invention includes a first insulating film formed on a substrate, a floating gate formed on the first insulating film, into which hydrogen atoms are introduced, and formed in the substrate on both sides of the floating gate. A source region and a drain region, a second insulating film covering the floating gate, a control gate formed separately from the floating gate via the second insulating film, and at least the floating gate and the control gate And a protective film covering the upper layer.

  According to the present invention, since hydrogen atoms are introduced into the floating gate, the hydrogen atoms can be trapped in the carrier trap formed by the material constituting the floating gate. As a result, the resistance of the floating gate can be reduced.

  The present invention also provides a first insulating film formed on a substrate, a floating gate formed on the first insulating film, and a source region and a drain region formed in the substrate on both sides of the floating gate. A second insulating film covering the floating gate, a control gate formed separately from the floating gate via the second insulating film, and a protective film covering at least the upper layer of the floating gate and the control gate The floating gate may be a semiconductor memory device formed of polycrystalline silicon having a plurality of grain sizes.

  According to the present invention, since the floating gate is formed of polycrystalline silicon having a plurality of grain sizes, it is possible to reduce the threshold fluctuation of the voltage to be supplied to the control gate in order to form the conductive path. According to the present invention, since the floating gate is formed of polycrystalline silicon having a plurality of grain sizes, the number of particle interfaces or the surface area can be reduced.

  According to the present invention, it is possible to suppress deterioration in the erasing speed and variation in threshold values of a semiconductor memory device while depletion is progressing.

A semiconductor memory device according to the best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described below with reference to the drawings. The configuration of the following embodiment is an exemplification, and the present invention is not limited to the configuration of the embodiment.
<Outline of invention>
FIG. 1 shows a cross-sectional structure of a nonvolatile semiconductor memory device (hereinafter simply referred to as a semiconductor device) having a floating gate with a direct tunnel structure. The semiconductor device includes a semiconductor substrate (corresponding to the substrate of the present invention) 1, a source 2 and a drain 3 formed on the semiconductor substrate 1, and a semiconductor substrate region (where a conductive path is formed between the source 2 and the drain 3). An insulating film 4 (also referred to as a channel region) (corresponding to the first insulating film of the present invention), a floating gate 5 formed on the insulating film 4, and an insulating film 6 covering the periphery of the floating gate 5 (the present invention) 2), an oxide film cap 7 covering the upper portion of the floating gate 5, a control gate 8 formed by being separated from the floating gate 5 by the insulating film 6, and a side wall of the control gate 8 being covered. And a protective film 10 covering the surface of the semiconductor device including the oxide film cap 7, the control gate 8 and the sidewall 9. The configuration and manufacturing method of such a semiconductor device are described in detail in Japanese Patent Laid-Open No. 2000-150680, Japanese Patent Laid-Open No. 2001-168213, and Japanese Patent Laid-Open No. 2002-16155 by the present applicant. Is omitted, and a characteristic configuration will be described.

  As shown in FIG. 1, an extremely thin insulating film 4 (thickness of about 1 to 3 nm) is formed on the upper layer of the channel region between the source 2 and the drain 3. Since the insulating film 4 is thin, when a voltage is applied between the control gate 8 and the source 2 / drain 3, carriers in the channel region between the source 2 and the drain 3 penetrate the insulating film 4 and pass through the floating gate 5. Injected into. For this reason, the insulating film 4 is also called a tunnel insulating film.

  When carriers are injected into the floating gate 5, the threshold value of the transistor changes, so that it is possible to determine the presence or absence of carrier injection. Therefore, information can be stored depending on whether or not carriers are injected into the floating gate 5.

In the semiconductor device of the present embodiment, the impurity concentration of the floating gate 5 is set low (about 5 × 10 ¹⁹ cm ⁻³ or less) as in the case of Japanese Patent Laid-Open No. 2002-16155, and is depleted. By depletion, the carrier injected into the floating gate 5, that is, the retention of information for a long time is achieved.

FIG. 2 shows an outline of a method for manufacturing a semiconductor device having a direct tunnel structure. A semiconductor device having a direct tunnel structure is generally manufactured by (1) forming an element isolation structure and (2) implanting impurities into a well region and performing the following steps in a normal CMOS logic manufacturing process.
-Impurities are implanted into the channel region. This impurity is implanted for the purpose of adjusting the threshold value of the transistor.
A thin insulating film 4 (thickness of about 1 to 3 nm) is formed on the channel region.
A polysilicon film to be the floating gate 5 is formed on the element isolation structure and the insulating film 4.
A gate structure including the floating gate 5 is formed.
An insulating film 6 that covers the floating gate 5 is formed, and a control gate 8 is formed outside the insulating film 6.
After that, after passing through the same process as a normal CMOS logic process, a protective film 10 of a silicon nitride film is formed by plasma CVD. Furthermore, in this embodiment, annealing is performed after the protective film 10 is formed.

FIG. 3 shows the relationship between the impurity concentration of polysilicon and the resistance value. As shown in FIG. 3, when the impurity concentration is a predetermined value or less, for example, 5 × 10 ¹⁹ cm ⁻³ or less, polysilicon (graph indicated by reference symbol Poly-Si) has a single crystal silicon (reference symbol Bulk-Si). Compared with the graph shown), the resistance value increases rapidly.

  Therefore, when the depletion of the floating gate 5 made of polysilicon progresses, the specific resistance of the polysilicon increases rapidly as in FIG. For this reason, depletion becomes one of the causes of deteriorating the erase speed of the nonvolatile semiconductor memory device having the floating gate 5.

  The present embodiment proposes a configuration of a semiconductor device that reduces an increase in the specific resistance of polysilicon even when the floating gate 5 is depleted, and a method for manufacturing such a semiconductor device. In order to reduce the specific resistance, the present applicant paid attention to the grain boundary of polysilicon.

  FIG. 4 shows a physical model of the grain boundary. FIG. 4 is an enlarged view of the polysilicon floating gate 5 on the substrate 1 and the insulating film 4 described in FIG. Here, the grain boundary refers to the interface between the crystal grains of polysilicon. The grain boundary has a potential barrier that traps electrons.

However, the present applicant has conceived that by trapping hydrogen atoms in the grain boundary, the trapping of electrons can be reduced, and as a result, the specific resistance of polysilicon can be reduced. That is, when hydrogen atoms are implanted into the grain boundary, Si—H bonds are formed, and the number of dangling bonds of silicon that traps electrons decreases. In this embodiment, a large amount (about 5 × 10 ¹⁹ cm ⁻³ or more) of hydrogen atoms is injected into polysilicon to reduce the trapping of electrons at the grain boundary, and the specific resistance of the depleted floating gate 5 is reduced. To do.

  In this embodiment, in order to supply hydrogen atoms to the floating gate 5, Si—N (silicon nitride film) used as the protective film 10 in FIG. 1 is used. A silicon nitride film formed by plasma CVD contains a large number of hydrogen atoms. Therefore, after forming the silicon nitride film, the semiconductor device is annealed at a predetermined temperature for a predetermined time, so that hydrogen atoms are supplied from the silicon nitride film to the floating gate 5. The hydrogen atoms supplied to the floating gate 5 are terminated (trapped) in the form of atoms at the grain boundary. By supplying a large number of hydrogen atoms to the grain boundary, the number of electrons trapped in the grain boundary is reduced, and the specific resistance of the polysilicon, that is, the floating gate 5 is reduced.

Compared with the case where atomic hydrogen is implanted by annealing from a silicon nitride film, even if hydrogen or deuterium is supplied by annealing in an H ₂ or D ₂ atmosphere, the trap is sufficiently high in concentration. Hydrogen or deuterium cannot be injected.

  In the present embodiment, the resistance of the floating gate 5 is further reduced by introducing a process for increasing the grain size of polysilicon. As is apparent from FIG. 4, when the grain size of the polysilicon is increased, the number of grains is reduced and the surface area of the grains is also reduced. In other words, the probability of electrons being trapped can be reduced by increasing the particle size and reducing the boundary location or the surface area of the boundary. Thus, the specific resistance of the floating gate 5 can be reduced by increasing the grain size of the polysilicon.

  However, when the particle size is increased, there arises a problem that variation in threshold value increases. Therefore, in the present embodiment, polysilicon having a small particle size is formed in the vicinity of the insulating film 4, while polysilicon having a large particle size is formed in the upper layer to suppress variation in threshold value.

<< First Embodiment >>
In the first embodiment, an example of a configuration of a semiconductor device and a method of manufacturing the semiconductor device in which the specific resistance of the floating gate 5 is reduced by injecting atomic hydrogen into the floating gate 5 will be described.

The semiconductor device shown in FIG. 1 is manufactured by forming the floating gate 5 so that the impurity (for example, P, As) concentration is lower than 5 × 10 ¹⁹ cm ⁻³ . Atomic hydrogen is implanted into this semiconductor device under the condition that the hydrogen concentration is higher than the impurity concentration. As a specific procedure, annealing is performed after the protective film 10 (silicon nitride film) is formed. The silicon nitride film is a silicon nitride film formed by plasma-excited active nitrogen and nitrogen-containing molecules (so-called plasma CVD). Heat treatment (sintering) conditions are from 400 ° C to 4
It is about 50 ° C. and 10 min to 30 min. In this process, the silicon nitride film is generated according to the following formula, and therefore contains a large amount of hydrogen.
Reaction formula: SiH ₄ + NH ₃ => SiN + (H ₂ ) + (N ₂ )
As a result, as shown in FIG. 4, atomic hydrogen is terminated at the grain boundary. FIG. 5 shows a change in specific resistance when a plasma nitride film is used. In FIG. 5, AS Depo indicates a material on which polysilicon containing arsenic having a concentration of 5 × 10 ¹⁹ cm ⁻³ is deposited. The specific resistance in this case is about 1.5 ohm · cm.

  P-Sin + 400C 10 min indicates a material obtained by forming a silicon nitride film on the polysilicon material and annealing at 400 degrees Celsius for 10 minutes. In this case, the specific resistance is reduced to about 0.12 ohm · cm.

  Similarly, P-Sin + 450C 30 min indicates a material annealed at 450 degrees Celsius for 30 minutes. In this case, the specific resistance is reduced to about 0.13 ohm · cm.

FIG. 6 shows a SIMS (Secondary Ion Mass Spectrometry) profile at that time. The secondary ion mass spectrometer configures the sample by accelerating the primary ions, irradiating the sample surface, and analyzing the mass of charged particles (secondary ions) out of the particles that have jumped out by sputtering. It is a device that identifies the elemental component to be used.

FIG. 6 is a result of analyzing the components of the surface with a secondary ion mass spectrometer, along with the step of scraping the surface of the material consisting of polysilicon, oxide film (SiO ₂ ), and silicon substrate showing the characteristics of FIG. is there.

In FIG. 6, the horizontal axis indicates the depth of the material surface. A range indicated by an arrow A is a range where polysilicon is formed. A range indicated by an arrow B is a range where an oxide film (SiO ₂ ) is formed. Further, an arrow C is a region of the silicon substrate. The data in FIG. 6 is an analysis result of a semiconductor device used for experimentally examining the impurity concentration and atomic hydrogen concentration of polysilicon, and the insulating film is not formed thin enough to allow a direct tunnel current to flow. .

In FIG. 6, the graph indicated by reference numeral 100 measured in polysilicon (the region indicated by arrow A) is the hydrogen atom concentration. The hydrogen atom concentration is about 3 × 10 ²⁰ cm ^{−3 in the} vicinity of the polysilicon surface. The hydrogen atom concentration decreases as it goes deeper from the surface into the polysilicon film. At the deepest position (about 130 nm) in the polysilicon, the hydrogen atom concentration is about 2 × 10 ¹⁹ cm ⁻³ .

Moreover, the graph of the code | symbol 101 has shown distribution of the arsenic which is an impurity in polysilicon. As shown in FIG. 5, the arsenic concentration also decreases as it advances deeper from the surface into the polysilicon film. The arsenic concentration is about 4 × 10 ¹⁹ cm ⁻³ near the polysilicon surface. Further, at the deepest position (about 130 nm) in the polysilicon, the arsenic concentration is about 1 × 10 ¹⁸ cm ⁻³ . As described above, in the sample in which the specific resistance shown in FIG. 5 is obtained, the hydrogen atom concentration exceeds the arsenic concentration over the entire range of the polysilicon film.

<Manufacturing process>
7 to 9 show the manufacturing process of the semiconductor device according to the present embodiment. First, the silicon substrate 1 is doped with boron at an acceleration energy of 10 keV and a dose of 1e12 to 1e13 cm ⁻² . This is channel dope for transistor threshold adjustment.

  Next, an insulating film 4 is formed on the entire surface of the silicon substrate 1 with a silicon oxide film having a thickness of about 1 to 3 nm by a thermal oxidation method.

Next, a 150 nm-thickness polysilicon film to be the floating gate 5 is formed on the insulating film 4 by CVD (Chemical Vapor Deposition) ((3-1) Poly-Si deposition). .

Next, n-type impurities such as phosphorus and arsenic are introduced into the polysilicon film by ion implantation. For example, when phosphorus is implanted, ion implantation is performed with an acceleration energy of 20 keV and a dose of 5e13 × 4 (direction) cm ⁻² ((3-2) gate implantation). Then, the n-type impurity is activated by heat treatment. By the heat treatment, n-type impurities are diffused, and the concentration of the n-type impurities in the polysilicon is about 5 × 10 ¹⁹ cm ⁻³ .

  Next, a 100 nm-thickness silicon oxide film to be the oxide film cap 7 is formed on the polysilicon film surface by thermal oxidation ((3-3) oxide film cap).

  Next, a gate pattern is formed on the silicon oxide film with a photoresist by photolithography. Then, from the oxide film cap 7 to the surface of the silicon substrate 1 is etched using the photoresist as a mask, leaving the gate pattern ((3-4) gate etching). As a result, patterns of the oxide film 4, the floating gate 5 and the oxide film cap 7 are formed.

  Next, an oxide film having a thickness of 5 nm is formed on the entire surface of the silicon substrate 1 by thermal oxidation ((4) Gate oxidation in FIG. 8).

  Next, an impurity-doped polysilicon film to be the control gate 8 is formed to a thickness of 100 nm on the entire surface of the silicon substrate 1 by the CVD method. Furthermore, activation annealing is performed under heat treatment conditions of 1000 degrees Celsius and 10 seconds. Next, the polysilicon film is anisotropically etched to form the control gate 8 ((5) control gate (CG) formation).

Next, an n-type impurity such as arsenic is introduced by ion implantation at an acceleration energy of 5 keV and a dose of 1e14 × 4 (direction) cm ⁻² ((6) LDD (Light Doped Drain) implantation). As a result, an extension source / drain structure is formed near the surface of the silicon substrate 1.

  Next, a 100 nm-thickness silicon oxide film to be the sidewalls 9 is formed on the entire surface of the silicon substrate 1 by the CVD method. Next, the silicon oxide film is anisotropically etched. As a result, sidewalls 9 are formed on the side surfaces of the control gate 8 ((7) sidewall formation).

Next, an n-type impurity such as arsenic is implanted by ion implantation with an acceleration energy of 20 keV and a dose of 5e14 × 4 (direction) cm ⁻² . Further, activation annealing is performed at 1000 degrees Celsius for 10 seconds. Thereby, the source 2 / drain 3 are formed ((8) SD injection).

Next, as a cover structure, a silicon oxide film of 100 nm is formed by CVD ((9) oxide film (LTO (low temperature oxide) deposition in FIG. 9) and plasma CVD.
Thus, a silicon nitride film 9 is deposited to a thickness of 100 nm ((10) silicon nitride film deposition).

  Next, annealing is performed at a temperature of about 400 degrees Celsius to about 450 degrees Celsius for 10 minutes to 30 minutes. By this annealing, atomic hydrogen is supplied from the silicon nitride film 9 to the floating gate 5.

Through such a process, atomic hydrogen exceeding a high concentration, for example, 5 × 10 ¹⁹ cm ⁻³ is supplied to the polysilicon floating gate 5 depleted to an impurity concentration of 5 × 10 ¹⁹ cm ⁻³ or less. can do. Since atomic hydrogen is trapped on the grain boundary, the possibility that electrons serving as carriers are trapped can be reduced. As a result, an increase in the specific resistance of the depleted floating gate 5 can be suppressed, information can be retained for a long time, and an increase in erase time can be suppressed.

  That is, from the viewpoint of a physical phenomenon, when electrons are trapped in the grain boundary of polysilicon, a potential barrier between the grains and the grain boundary (a barrier when electrons pass through) increases. As a result, the specific resistance increases. This is because when the impurity concentration of polysilicon becomes low, the number of active electrons present in the grains decreases, so that the effect becomes noticeable.

  The semiconductor device shown in this embodiment traps a large amount of atomic hydrogen instead of electrons in the grain boundary, thereby lowering the potential barrier and suppressing the decrease in the number of active electrons in the grain. As a result, the specific resistance is reduced as compared with the case where atomic hydrogen is not injected. In order to trap a large amount of atomic hydrogen, annealing after the silicon nitride film is formed is effective.

<< Second Embodiment >>
In the first embodiment, by annealing after the silicon nitride film is formed, atomic hydrogen is trapped in the polysilicon grain boundary constituting the floating gate 5, and the specific resistance of the depleted floating gate 5 is reduced. In addition, the structure of the semiconductor device and the manufacturing method thereof have been described.

  In the present embodiment, the structure of the semiconductor device in which the specific resistance of the floating gate 5 is reduced by controlling the grain size of the polysilicon that constitutes the floating gate 5 (formation of two polysilicon layers having different grain sizes) and its A manufacturing method will be described. The outline of the other configuration and the manufacturing method is the same as that of the first embodiment. Therefore, the same constituent elements are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted. Further, the drawings in FIGS. 1 to 9 are referred to as necessary.

  FIG. 10 shows the structure of the grains contained in the floating gate 5 of the semiconductor device according to this embodiment. As shown in FIG. 10, in this embodiment, the polysilicon is constituted by two layers. The first polysilicon layer formed on the insulating film 4 is formed by CVD so that the grain size is a normal size.

  The second polysilicon layer formed on the first polysilicon layer is first made amorphous, and then annealed to make the grain size larger than the grain size of the first polysilicon layer. To do. Since the grain size is controlled under the CVD temperature condition (in this embodiment, 600 degrees Celsius), an oxide film is sandwiched between the first polysilicon and the second polysilicon. Furthermore, the specific resistance reduction effect may be further increased by implanting atomic hydrogen similar to that in the first embodiment.

  FIG. 11 is a result of experimentally determining a change in specific resistance when the grain size is increased. In FIG. 7, the horizontal axis indicates the dose of polysilicon (single layer). The vertical axis indicates the specific resistance of polysilicon.

  In FIG. 11, the graph indicated by Poly-Si indicates the specific resistance of polysilicon formed by the CVD method under the condition of 590 degrees 39 minutes. The graph indicated by A-Si shows the specific resistance when amorphous silicon formed under the condition of 500 degrees 55 minutes is annealed (600 degrees Celsius, 18 hours, 1000 degrees 20 seconds). ing. By converting amorphous silicon into polycrystalline silicon having a large grain size by annealing, the specific resistance is greatly reduced regardless of whether the impurity is P or As.

  FIG. 12 shows a method for manufacturing the semiconductor device of this embodiment. Similar to the first embodiment (FIG. 8), the silicon substrate 1 is subjected to (1) channel doping and (2) gate oxide film formation (becomes the insulating film 4).

Next, 20 to 30 nm of polysilicon 51 doped with impurities at a low concentration (5 × 10 ¹⁹ cm ⁻³ or less) to be the first layer of the floating gate 5 is formed by a CVD method ((3-1) Doped Poly). -Si deposition).

Next, an extremely thin oxide film 52 (thickness of about 1 nm) is formed on the polysilicon 51 by thermal oxidation ((3-2) oxide film (very thin)).

Next, an amorphous silicon 53 doped with an impurity at a low concentration (5 × 10 ¹⁹ cm ⁻³ or less) is deposited on the oxide film 52 to a thickness of 150 nm. ((3-3) Doped a-Si deposition).

Next, an oxide film to be the oxide film cap 7 is formed by a thermal oxidation method with a film thickness of 100 nm ((3-4) oxide film cap). Next, in order to crystallize the amorphous silicon 53, annealing at 600 degrees Celsius for 18 hours and 1000 degrees Celsius for 20 seconds is performed ((3-5) crystallization annealing). Further, gate etching is performed as in the first embodiment (FIG. 8). Since the subsequent procedure is the same as that in FIGS. 8 and 9 of the first embodiment, the procedure is omitted. In this way, approximately 20-3
A first polysilicon layer having a particle size of 0 nm is formed, and a second polysilicon layer having a particle size of approximately 100 to 150 nm is formed thereon.

  As described above, by increasing the grain size of the polysilicon in the polysilicon, the number of grain boundaries and hence the surface area can be reduced, and the number of electrons trapped in the grain boundary can be reduced. As a result, the specific resistance of the floating gate 5 is reduced by increasing the number of active electrons in the grain.

  However, if the particle size is large, it causes variation in the threshold value of the transistor. Therefore, as shown in FIG. 11, two layers of polysilicon are used, and the particle size near the interface of the insulating film 4 is a normal floating gate. And increase the particle size only in the upper layer. If the particle size is large, the positional relationship of the floating gates facing the channel region between the source 2 and the drain 3 with the insulating film 4 interposed therebetween varies. For example, in some cases, the polysilicon grain boundary is located on the channel region boundary (the end of the source 2 and the end of the drain 3), and in some cases, the vicinity of the center of the grain is located on the boundary. . When the positional relationship of polysilicon with respect to the channel region boundary is different, the electric field strength formed in the channel region by the carriers of the floating gate 5 changes. As a result, the threshold value varies depending on the positional relationship.

  As described in the present embodiment, it is possible to suppress the threshold variation due to the grain size of the polysilicon by using two layers of polysilicon.

<Others>
This embodiment includes the following aspects of the invention (referred to as supplementary notes).
(Appendix 1)
A first insulating film formed on the substrate;
A floating gate formed on the first insulating film and introduced with hydrogen atoms;
A source region and a drain region formed in the substrate on both sides of the floating gate;
A second insulating film covering the floating gate;
A control gate formed separately from the floating gate via the second insulating film;
And a protective film covering at least an upper layer of the floating gate and the control gate. (1)
(Appendix 2)
The semiconductor memory device according to appendix 1, wherein the protective film is a silicon nitride film. (2)
(Appendix 3)
A first insulating film formed on the substrate;
A floating gate formed on the first insulating film;
A source region and a drain region formed in the substrate on both sides of the floating gate;
A second insulating film covering the floating gate;
A control gate formed separately from the floating gate via the second insulating film;
A protective film covering at least the upper layer of the floating gate and the control gate,
The floating gate is a semiconductor memory device formed of polycrystalline silicon having a plurality of grain sizes. (3) (Appendix 4)
The semiconductor memory device according to appendix 3, wherein the floating gate is introduced with hydrogen atoms.
(Appendix 5)
The floating gate includes a first layer made of polycrystalline silicon having a first grain size and a second layer made of polycrystalline silicon having a second grain size larger than the first grain size. Or the semiconductor memory device according to 4.
(Appendix 6)
Forming a first insulating film on the semiconductor substrate;
Forming a floating gate on the first insulating film;
Forming a second insulating film covering the floating gate;
Forming a control gate by separating from the floating gate through the second insulating film;
Forming a source region and a drain region in the substrate on both sides of the floating gate;
Forming a silicon nitride film covering at least the upper layer of the floating gate and the control gate;
And a step of supplying hydrogen atoms from the silicon nitride film to the floating gate by performing a heat treatment at a predetermined temperature for a predetermined time. (4)
(Appendix 7)
Forming a first insulating film on the semiconductor substrate;
Forming a floating gate made of polycrystalline silicon on the first oxide film; and
Forming a second insulating film covering the floating gate;
Forming a control gate by separating from the floating gate through the second insulating film;
Forming a source region and a drain region in the substrate on both sides of the floating gate;
Forming a protective film covering at least the upper layer of the floating gate and the control gate, and
In the floating gate forming step, the floating gate is formed by controlling the grain size of the polycrystalline silicon. (5)
(Appendix 8)
The floating gate forming step forms a first layer made of polycrystalline polysilicon having a first grain size,
The method of manufacturing a semiconductor memory device according to appendix 7, wherein a second layer made of polycrystalline polysilicon having a second grain size larger than the first grain size is formed on the first layer.
(Appendix 9)
The semiconductor according to appendix 7 or 8, wherein the protective film is a silicon nitride film, and hydrogen atoms are supplied from the silicon nitride film to the floating gate by performing a heat treatment at a predetermined temperature for a predetermined time after the protective film forming step. A method for manufacturing a storage device.

It is a figure which shows the cross-section of the semiconductor device which has a floating gate of a direct tunnel structure. It is a figure which shows the outline | summary of the manufacturing method of the semiconductor device of a direct tunnel structure. It is a figure which shows the relationship between the impurity concentration of a polysilicon, and resistance value. It is a figure which shows the physical model of a grain boundary. It is a figure which shows the change of a specific resistance when a silicon nitride film is used. It is a figure which shows the analysis result by the secondary ion mass spectrometer of the semiconductor device which inject | poured atomic hydrogen. FIG. 6 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is a diagram (part 2) illustrating a manufacturing process of the semiconductor device according to the first embodiment; FIG. 8 is a diagram (No. 3) for illustrating a manufacturing step of the semiconductor device according to the first embodiment; It is a figure which shows the structure of the grain of the floating gate 5 of the semiconductor device which concerns on 2nd Embodiment. Results of experimental changes in resistivity when the grain size increases It is a figure which shows the manufacturing process of the semiconductor device which concerns on 2nd Embodiment.

Explanation of symbols

1 Silicon substrate 2 Source 3 Drain 4 Insulating film (tunnel insulating film)
5 Floating gate 6 Insulating film 7 Oxide film cap 8 Control gate 9 Side wall 10 Protective film (silicon nitride film)

Claims (3)

A first insulating film having a thickness of 3 nm or less formed on the substrate;
A floating gate formed of polycrystalline silicon having an impurity concentration of 5 × 10 ¹⁹ cm ⁻³ or less on the first insulating film and introduced with hydrogen atoms;
A source region and a drain region formed in the substrate on both sides of the floating gate;
A second insulating film covering the floating gate;
A control gate formed separately from the floating gate via the second insulating film;
And a protective film covering at least an upper layer of the floating gate and the control gate.   The semiconductor memory device according to claim 1, wherein the protective film is a silicon nitride film. Forming a first insulating film having a thickness of 3 nm or less on a semiconductor substrate;
Forming a floating gate on the first insulating film with polycrystalline silicon having an impurity concentration of 5 × 10 ¹⁹ cm ⁻³ or less;
Forming a second insulating film covering the floating gate;
Forming a control gate by separating from the floating gate through the second insulating film;
Forming a source region and a drain region in the substrate on both sides of the floating gate;
Forming a silicon nitride film covering at least the upper layer of the floating gate and the control gate;
And a step of supplying hydrogen atoms from the silicon nitride film to the floating gate by performing a heat treatment at a predetermined temperature for a predetermined time.

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