JP5061833B2 - Voltage abnormality detector - Google Patents

Description

  The present invention relates to a voltage abnormality detection device, and is particularly suitable for application to an AC power supply system represented by a constant commercial power supply type uninterruptible power supply.

An AC power supply system is equipped with an uninterruptible power supply that monitors whether the power system has an abnormal voltage and supplies power from a battery to a load when an abnormal voltage is detected (Patent Document 1).
FIG. 7 is a block diagram showing a schematic configuration of an AC power supply system to which the uninterruptible power supply is applied.
In FIG. 7, a power system 1 is connected to a load 4 via a changeover switch 2, and a power converter 7 that converts direct current to alternating current by a switching operation is connected via an AC reactor 8. The change-over switch 2 can be constituted by a mechanical switch or a semiconductor switch. Here, a battery 5 that supplies a DC voltage is connected to the power converter 7, and a control circuit 13 that controls the switching operation of the power converter 7 is connected via a gate drive unit 9.

Also, a DC voltage detector 6 that detects the DC voltage of the battery 5, a current detector 3 that detects a current supplied to the load 4, a current detector 11 that detects a current output from the power converter 7, and a power system An AC voltage detector 12 that detects the AC voltage output from 1 and an AC voltage detector 10 that detects the AC voltage output from the power converter 7 are provided.
When the system is normal, the power generated in the power system 1 is supplied to the load 4 via the changeover switch 2, and when the power system 1 becomes an abnormal voltage, the changeover switch 2 is opened and the power converter 7 Electric power is supplied to the load 4.

Here, when the system is normal, the power converter 7 operates as a current control type converter referred to as an interconnection operation mode, and the DC voltage of the battery 5 is detected by the DC voltage detector 6 so as to become a constant voltage. To control. Further, harmonic compensation and power factor compensation are performed while detecting the load current with the current detector 3 and observing the self-current with the current detector 11. When the system is abnormal, the power converter 7 operates as a voltage control type converter called a self-sustaining operation mode, converts the DC power of the battery 5 into AC power, and supplies power to the load 4 via the AC reactor 8. Supply.
Here, in order to monitor whether or not the power system 1 has an abnormal voltage, the control circuit 13 is provided with a voltage abnormality detection device 13a, and the AC voltage detected by the AC voltage detector 12 is detected as a voltage abnormality. It is output to the device 13a (Patent Document 2).

FIG. 8 is a block diagram showing a schematic configuration of a conventional voltage abnormality detection device, and FIG. 9 is a diagram showing a voltage abnormality determination method in the conventional voltage abnormality detection device.
In FIG. 8, the voltage abnormality detection device 13 a includes a PLL circuit 14 that generates a signal having an oscillation frequency synchronized with a reference frequency, and an upper limit value calculation circuit that calculates an upper limit value of the AC voltage detected by the AC voltage detector 12. 15, a lower limit calculation circuit 16 for calculating the lower limit value of the AC voltage detected by the AC voltage detector 12, and a comparator 17a for comparing the detected value of the AC voltage detected by the AC voltage detector 12 with the upper limit value. , A comparator 17b that compares the detected value of the AC voltage detected by the AC voltage detector 12 with the lower limit value, an upper and lower limit abnormality determination circuit 18 that determines the sign of the upper limit value and the lower limit value of the AC voltage, and the upper limit value and the lower limit A voltage abnormality determination circuit 19 is provided for determining the validity of the comparison results by the comparators 17a and 17b based on the sign of the value.

  The AC voltage detected by the AC voltage detector 12 is input to the PLL circuit 14 and the comparators 17a and 17b. Then, a signal synchronized with the AC voltage detected by the AC voltage detector 12 is generated by the PLL circuit 14 and is output to the upper limit value calculation circuit 15 and the lower limit value calculation circuit 16. Then, the upper limit calculation circuit 15 and the lower limit calculation circuit 16 respectively generate an upper limit value and a lower limit value by shifting the level of the signal output from the PLL circuit 14 up and down, respectively, to the comparators 17a and 17b. Output each.

  The comparators 17 a and 17 b compare the detected value of the AC voltage detected by the AC voltage detector 12 with the upper limit value and the lower limit value, respectively, and output the comparison result to the voltage abnormality determination circuit 19. The upper limit value and the lower limit value generated by the upper limit value calculation circuit 15 and the lower limit value calculation circuit 16, respectively, are input to the upper / lower limit abnormality determination circuit 18, and the upper / lower limit abnormality determination circuit 18 has the same upper limit value and lower limit value. It is determined whether the code is different from the sign, and the determination result is output to the voltage abnormality determination circuit 19.

The voltage abnormality determination circuit 19 determines that the voltage is abnormal when the detected value of the AC voltage is not less than the upper limit value or not more than the lower limit value, and the upper limit value and the lower limit value have the same sign, and the detected value of the AC voltage is Even if the upper limit value and the lower limit value are different from each other even when the upper limit value is equal to or higher than the lower limit value (intervals T1, T2, T3 in FIG. 9), it is determined as a detection error.
Japanese Patent No. 3406835 JP 2006-10435 A

However, in the voltage abnormality detection device 13a of FIG. 8, even if the detected value of the AC voltage is not less than the upper limit value or not more than the lower limit value, if the upper limit value and the lower limit value are different signs, it is determined as a detection error. Voltage abnormality cannot be detected near the zero cross. For this reason, when a short circuit between the lines occurs in the single-phase circuit, the detection of the voltage abnormality is delayed, and the load 4 may be damaged.
Moreover, in a system with a large line impedance, the voltage distortion becomes large. Therefore, in order to prevent erroneous detection, increasing the upper limit value and the lower limit value, the greater the delay in detecting the voltage abnormality, there is a problem that in the event of actual system fault can not be protected load 4 It was.
Therefore, an object of the present invention is to provide a voltage abnormality detection device that can detect a voltage abnormality even in the vicinity of the zero cross and can suppress a delay in detection of the voltage abnormality even when the voltage distortion is large. It is to be.

In order to solve the above-described problem , according to the voltage abnormality detection device according to claim 1 , the current output from the power converter that converts the DC voltage into AC is based on a signal synchronized with the voltage of the power system. Coordinate conversion means for calculating an effective current output from the power converter by converting to a dq-axis component, and a capacitance smaller than the capacitance of the DC capacitor of the actual DC circuit based on the effective current a virtual DC capacitor voltage calculating means for calculating the voltage of the virtual DC capacitor, when the voltage of the virtual DC capacitor exceeds a limit value, and characterized in that it comprises an abnormality determination circuit for determining a voltage abnormality of the power system To do.

According to the voltage abnormality detection device of claim 2, the voltage of the virtual DC capacitor is calculated only in the interconnection operation mode, and the initial value is an actual DC voltage when switching to the interconnection operation mode. It is characterized by being.

According to the voltage abnormality detection device of claim 3 , the virtual DC capacitor voltage calculation means uses the value obtained by multiplying the effective current calculated by the coordinate conversion means by a limiter, so that the virtual DC capacitor The voltage is calculated.
The voltage abnormality detection device according to claim 4 further includes a voltage abnormality determination circuit that determines a voltage abnormality of the power system based on a detected value of the voltage of the power system.

As described above, according to the present invention, it becomes possible to determine a voltage abnormality regardless of the sign of the upper limit value and the lower limit value of the AC voltage, and even if the instantaneous value of the AC voltage changes greatly, the upper limit When the value and lower limit are not increased, it is possible to prevent erroneous determination of voltage abnormality, and it is possible to detect voltage abnormality even in the vicinity of the zero cross and when voltage distortion is large In this case, it is possible to suppress the delay in detecting the voltage abnormality.
In addition, the voltage of the virtual DC capacitor is calculated based on the effective current output from the power converter, and the voltage abnormality of the power system is judged from the voltage of the virtual DC capacitor. Thus, before the output voltage drops, voltage fluctuation can be detected from the voltage output by the power converter, and an open power failure at light load can be detected.

Hereinafter, a voltage abnormality detection device according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a schematic configuration of the voltage abnormality detection device according to the first embodiment of the present invention.
In FIG. 1, the voltage abnormality detection device is provided with a PLL circuit 14, an upper limit value calculation circuit 15, a lower limit value calculation circuit 16, a comparator 17a, a comparator 17b, and a comparator 17a, as in the configuration of FIG. , 17b, the logical sum circuit 101 that takes the logical sum of the outputs, the confirmation timer 20 that measures the time when the output of the logical sum circuit 101 is active, When the value is equal to or greater than the confirmation time limit value 23, the time determination circuit 21 that determines that the voltage of the power system 1 is abnormal, and the biaxial voltage that determines the voltage abnormality of the power system 1 based on the dq axis component of the voltage of the power system 1 A logical sum circuit 102 is provided for taking the logical sum of the outputs of the abnormality detection circuit 22 and the time determination circuit 21 and the output of the biaxial voltage abnormality detection circuit 22.

  The AC voltage detected by the AC voltage detector 12 is input to the PLL circuit 14, the comparators 17 a and 17 b, and the biaxial voltage abnormality detection circuit 22. Then, a signal synchronized with the AC voltage detected by the AC voltage detector 12 is generated by the PLL circuit 14 and output to the upper limit value calculation circuit 15, the lower limit value calculation circuit 16 and the biaxial voltage abnormality detection circuit 22. . Then, the upper limit calculation circuit 15 and the lower limit calculation circuit 16 respectively generate an upper limit value and a lower limit value by shifting the level of the signal output from the PLL circuit 14 up and down, respectively, to the comparators 17a and 17b. Output each.

  Then, the comparators 17a and 17b respectively compare the detected value of the AC voltage detected by the AC voltage detector 12 with the upper limit value and the lower limit value, and send the comparison result to the confirmation timer 20 via the OR circuit 101. Output. The confirmation timer 20 measures the time when the detected value of the AC voltage is equal to or higher than the upper limit value or lower limit value, and the time determination circuit 21 determines that the detected value of the AC voltage is equal to or higher than the upper limit value or lower limit value. When the time is equal to or greater than the confirmation time limit value 23, it is determined that the voltage of the power system 1 is abnormal, and the determination result is output to the OR circuit 102.

  The biaxial voltage abnormality detection circuit 22 converts the alternating voltage detected by the alternating voltage detector 12 into a dq axis component based on the signal output from the PLL circuit 14, and either of the dq axis components is converted. When the value becomes greater than or equal to the upper limit value or less than the lower limit value, it is determined that the voltage of the power system 1 is abnormal, and the determination result is output to the OR circuit 102. The logical sum circuit 102 outputs a voltage abnormality signal when a voltage abnormality is detected by either the time determination circuit 21 or the biaxial voltage abnormality detection circuit 22.

FIG. 2 is a block diagram showing a schematic configuration of the biaxial voltage abnormality detection circuit of FIG.
In FIG. 2, the biaxial voltage abnormality detection circuit 22 converts the AC voltage detected by the AC voltage detector 12 into a dq axis component based on the reference signals (cos θ, sin θ) output from the PLL circuit 14. Coordinate converter 109, first-order lag filters 29a and 29b for filtering the dq-axis component obtained by coordinate converter 109, and d-axis component obtained by coordinate converter 109 for lower limit 30 and upper limit 31, respectively. By comparing the q-axis component obtained by the abnormality determination circuit 104 and the coordinate converter 109 for determining the abnormality of the power system 1 with the lower limit value 32 and the upper limit value 33, the abnormality of the power system 1 is compared. Is provided with a logical sum circuit 103 that takes the logical sum of the abnormality determination circuit 105 and the abnormality determination circuits 104 and 105.

The coordinate converter 109 receives the AC voltage detected by the AC voltage detector 12 and the internal synchronization signal 28 output from the PLL circuit 14. The coordinate converter 109 Based on the internal synchronization signal 28 output from the PLL circuit 14, the AC voltage detected by the AC voltage detector 12 is converted into a dq-axis component and output to the first-order lag filters 29a and 29b, respectively.
If the AC voltage detected by the AC voltage detector 12 is V _uv , V _vw , V _wu , and the dq axis components are V _d and V _q , respectively, the dq axis components V _d and V _q are expressed by the following equations. Can be represented.

  Then, the dq axis components obtained by the coordinate converter 109 are respectively filtered by the first-order lag filters 29a and 29b, and then output to the abnormality determination circuits 104 and 105, respectively. Then, the abnormality determination circuit 104 compares the d-axis component that has passed through the first-order lag filter 29a with the upper limit value 31 and the lower limit value 30, and when the d-axis component becomes the upper limit value 31 or more or the lower limit value 30 or less, the power system 1 And the determination result is output to the OR circuit 103. In addition, the abnormality determination circuit 105 compares the q-axis component that has passed through the first-order lag filter 29b with the upper limit value 33 and the lower limit value 32, and when the q-axis component becomes the upper limit value 33 or more or the lower limit value 32 or less, the power system 1 And the determination result is output to the OR circuit 103. Then, the logical sum circuit 103 outputs a voltage abnormality signal to the logical sum circuit 102 when the abnormality determination circuit 104 or 105 detects a voltage abnormality.

  Thereby, it becomes possible to determine the voltage abnormality regardless of the sign of the upper limit value and the lower limit value of the AC voltage detected by the AC voltage detector 12, and even if the instantaneous value of the AC voltage changes greatly, Without increasing the upper limit value and the lower limit value, it is possible to prevent erroneous determination of voltage abnormality, and it is possible to detect voltage abnormality even in the vicinity of the zero cross, and voltage distortion is large. Even in this case, it is possible to suppress the delay in detecting the voltage abnormality.

FIG. 3 is a block diagram showing a schematic configuration of the voltage abnormality detection device according to the second embodiment of the present invention.
In FIG. 3, the voltage abnormality detection device is provided with a PLL circuit 14, an upper limit value calculation circuit 15, a lower limit value calculation circuit 16, a two-axis voltage abnormality detection circuit 22 and an AC voltage detection as in the configuration of FIG. Subtractors 106 and 107 for subtracting the upper limit value and the lower limit value from the AC voltage detected by the subtractor 12, respectively, code determination circuits 24a and 24b for determining the signs of the subtraction results by the subtractors 106 and 107, and the subtractors 106, An abnormality determination circuit 27a for determining a voltage abnormality of the power system 1 by comparing the integration results of the integrators 25a and 25b and the integrators 25a and 25b with the abnormality determination values 26a and 26b, respectively. 27b, a logical sum circuit 108 that takes the logical sum of the outputs of the abnormality determination circuits 27a and 27b and the output of the biaxial voltage abnormality detection circuit 22. It is provided.

  The AC voltage detected by the AC voltage detector 12 is input to the PLL circuit 14, the subtractors 106 and 107, and the biaxial voltage abnormality detection circuit 22. Then, a signal synchronized with the AC voltage detected by the AC voltage detector 12 is generated by the PLL circuit 14 and output to the upper limit value calculation circuit 15, the lower limit value calculation circuit 16 and the biaxial voltage abnormality detection circuit 22. . Then, the upper limit calculation circuit 15 and the lower limit calculation circuit 16 respectively generate an upper limit value and a lower limit value by shifting the level of the signal output from the PLL circuit 14 up and down, respectively. Output each.

  Then, the subtractors 106 and 107 subtract the upper limit value and the lower limit value from the detected value of the AC voltage detected by the AC voltage detector 12, respectively, and the subtraction results are sign determination circuits 24a and 24b and an integrator 25a, To 25b. The sign determination circuits 24a and 24b determine the signs of the subtraction results obtained by the subtractors 106 and 107, respectively, and reset the integrators 25a and 25b when the inputs of the integrators 25a and 25b become negative. The integrators 25a and 25b integrate the subtraction results from the subtractors 106 and 107, respectively, and output the integration results to the abnormality determination values 27a and 27b, respectively.

The abnormality determination values 27a and 27b compare the integration results obtained by the integrators 25a and 25b with the abnormality determination values 26a and 26b, respectively, and the integration results obtained by the integrators 25a and 25b exceed the abnormality determination values 26a and 26b, respectively. Is determined as a voltage abnormality in the power system 1 and the determination result is output to the OR circuit 108.
The biaxial voltage abnormality detection circuit 22 converts the alternating voltage detected by the alternating voltage detector 12 into a dq axis component based on the signal output from the PLL circuit 14, and either of the dq axis components is converted. When the value becomes greater than or equal to the upper limit value or less than the lower limit value, it is determined that the voltage of the power system 1 is abnormal, and the determination result is output to the OR circuit 108. The logical sum circuit 108 outputs a voltage abnormality signal when a voltage abnormality is detected by any of the abnormality determination circuits 27a and 27b or the biaxial voltage abnormality detection circuit 22.

FIG. 4 is a block diagram showing a schematic configuration of an AC power supply system to which the voltage abnormality detection device according to the third embodiment of the present invention is applied, and FIG. 5 shows the voltage abnormality detection device according to the third embodiment of the present invention. It is a block diagram which shows schematic structure.
The AC power supply system of FIG. 4, in addition to the configuration of the AC power supply system of FIG. 7, stack current detector 1 13a for detecting the current in the power converter 7 side is provided by the AC filter.

In FIG. 5, the voltage abnormality detection device includes a PLL circuit 114 that generates a signal having an oscillation frequency synchronized with the reference frequency, and a reference signal (cos θ, sin θ) generated by the PLL circuit 114. By converting the current detected by the stack current detector 1 13a into a dq axis component, the coordinate converter 120 that calculates the effective current output from the power converter 7 is calculated by the coordinate converter 120. A limiter 121 that limits a value smaller than the overshoot amount of the effective current, a gain element 123 that integrates a value obtained by multiplying the inverse of the capacity of the virtual capacitor by −1 with the output of the limiter 121, and an output from the upper limiter 125 are delayed. An adder 135 for adding the output from the time delay element 124 and the gain element 123 to the output from the time delay element 124 An upper limit limiter 125 for limiting the output from the adder 135 with the value detected by the detector 6 as an upper limit value, and a comparison for detecting an open power failure by comparing the output from the upper limit limiter 125 with the voltage drop detection level 133 132, a sequencer 134 that controls switching between the interconnection operation mode and the independent operation mode of the power converter 7, and a voltage abnormality detection circuit 122 that determines a voltage abnormality of the power system 1 based on a detected value of the voltage of the power system 1. A logical sum circuit 136 that takes the logical sum of the output of the comparator 132 and the output of the voltage abnormality detection circuit 122 is provided. As the voltage abnormality detection circuit 122, the configuration of FIG. 1 or FIG. 3 can be used.

The AC voltage detected by the AC voltage detector 12 is input to the PLL circuit 114 and the voltage abnormality detection circuit 122. A signal synchronized with the AC voltage detected by the AC voltage detector 12 is generated by the PLL circuit 114 and output to the coordinate converter 120. The coordinate converter 120, the active current to convert the sensed current in stack current detector 1 13a generated reference signal in the PLL circuit 114 (cosθ, sinθ) to the dq-axis component based on the Calculate and output to the limiter 121. Incidentally, the alternating current detected by stack current detector 1 13a iu, iv, iw, Id , respectively dq-axis component and the Iq, dq-axis component Id, Iq can be expressed by the following equation, d The shaft component Id becomes an effective current output from the power converter 7.

After the active current Id calculated by the coordinate converter 120 is subjected to limit by the limiter 121, the value obtained by multiplying by -1 the inverse of the capacity of the virtual capacitor is accumulated in the gain element 123, the adder It is output to 135.
Assuming that the active current Id has a positive direction in which the energy stored in the DC capacitor of the power converter 7 is discharged to the power system 1 , the effective current Id is negative when the DC capacitor and the battery 5 are charged. However, in some cases, it may become positive due to control overshoot. Therefore, by limiting the effective current Id calculated by the coordinate converter 120 by the limiter 121, it is possible to avoid erroneous detection during charging. it can.

  Next, when the output from the gain element 123 is input to the adder 135, it is added to the output from the time delay element 124 and is limited to a value detected by the DC voltage detector 6 by the upper limiter 125. After that, the comparator 132 compares with the voltage drop detection level 133. If the output from the upper limiter 125 is equal to or lower than the voltage drop detection level 133, it is determined that the power failure is an open power failure, and the determination result is output to the OR circuit 136.

  Note that the initial value of the time delay element 124 is the actual DC voltage detected by the DC voltage detector 6 at that time when it is determined by the signal output from the sequencer 134 that the self-sustaining operation mode has been switched to the interconnection operation mode. Can be a value. Further, the voltage abnormality detection circuit 122 determines the voltage abnormality of the power system 1 based on the detected value of the voltage of the power system 1, and outputs the determination result to the OR circuit 136. Then, when a voltage abnormality is detected by either the comparator 132 or the voltage abnormality detection circuit 122, the logical sum circuit 136 outputs a voltage abnormality signal.

As a result, the voltage of the virtual DC capacitor is calculated based on the effective current I _d output from the power converter 7, and the voltage abnormality of the power system 1 is determined from the voltage of the virtual DC capacitor, so that the actual DC Before the output voltage drops due to the voltage drop, voltage fluctuation can be detected from the voltage output from the power converter 7, and an open power failure at light load can be detected.

FIG. 6 is a diagram illustrating the relationship between the virtual capacitor voltage and the actual DC voltage. The virtual DC capacitor is a virtual DC capacitor having a capacitance smaller than that of the actual DC circuit. Thus, in FIG. 6, in the open power failure at light loads, the voltage of the virtual DC capacitor is reduced faster than the actual DC voltage, by using the voltage of the virtual DC capacitor, actually DC voltage decreases output Voltage fluctuations can be detected before the voltage drops.
In the above-described embodiment, the method of calculating the effective current Id from the AC current output from the power converter 7 has been described. However, the effective current Id may be calculated from the DC voltage of the battery 5.

It is a block diagram which shows schematic structure of the voltage abnormality detection apparatus which concerns on 1st Embodiment of this invention. It is a block diagram which shows schematic structure of the biaxial voltage abnormality detection circuit of FIG. It is a block diagram which shows schematic structure of the voltage abnormality detection apparatus which concerns on 2nd Embodiment of this invention. It is a block diagram which shows schematic structure of the alternating current power supply system with which the voltage abnormality detection apparatus which concerns on 3rd Embodiment of this invention is applied. It is a block diagram which shows schematic structure of the voltage abnormality detection apparatus which concerns on 3rd Embodiment of this invention. It is a figure which shows the relationship between a virtual capacitor voltage and an actual DC voltage. It is a block diagram which shows schematic structure of the alternating current power supply system with which an uninterruptible power supply device is applied. It is a block diagram which shows schematic structure of the conventional voltage abnormality detection apparatus. It is a figure which shows the determination method of the voltage abnormality in the conventional voltage abnormality detection apparatus.

Explanation of symbols

13a Stack current detector 14, 114 PLL circuit 15 Upper limit value calculation circuit 16 Lower limit value calculation circuit 17a, 17b, 132 Comparator 20 Confirmation timer 21 Time determination circuit 22 Two-axis voltage abnormality detection circuit 24a, 24b Sign determination circuit 25a, 25b Integrator 29a, 29b Primary delay filter 101, 102, 103, 108, 136 OR circuit 27a, 27b, 104, 105 Abnormality determination circuit 106, 107 Subtractor 109, 120 Coordinate converter 121 Limiter 122 Voltage abnormality detection circuit 123 Gain element 124 Time delay element 125 Upper limit limiter 134 Sequencer 135 Adder

Claims (4)

Coordinates for calculating the effective current output from the power converter by converting the current output from the power converter that converts DC voltage into AC into dq-axis components based on a signal synchronized with the voltage of the power system Conversion means;
Based on the effective current, virtual DC capacitor voltage calculation means for calculating the voltage of the virtual DC capacitor having a capacitance smaller than the capacitance of the DC capacitor of the actual DC circuit ;
A voltage abnormality detection device comprising: an abnormality determination circuit that determines that the voltage of the electric power system is abnormal when the voltage of the virtual DC capacitor exceeds a lower limit value. 2. The voltage abnormality detection device according to claim 1, wherein the voltage of the virtual DC capacitor is calculated only in the interconnection operation mode, and an initial value thereof is an actual DC voltage when the operation mode is switched to the interconnection operation mode. . The virtual DC capacitor voltage calculating means, by using a value obtained by multiplying the limiter enabling current calculated by the coordinate transformation unit, according to claim 1 or 2, characterized in that to calculate the voltage of the virtual DC capacitor The voltage abnormality detection apparatus of description. The voltage abnormality detection device according to any one of claims 1 to 3 , further comprising a voltage abnormality determination circuit that determines a voltage abnormality of the power system based on a detected value of the voltage of the power system.

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