JP5064665B2 - Pressure detection device - Google Patents

Description

The present invention relates to a pressure detection device including a pressure sensor applied to, for example, an automobile.

Conventionally, a semiconductor pressure sensor disclosed in the following Patent Document 1 has been proposed as this type of pressure detection device. In this semiconductor pressure sensor, a cross-shaped piezoresistive element is provided in a diaphragm portion of a semiconductor substrate, and one adjacent protrusion is used as a current supply terminal, and the other adjacent protrusion is used as a voltage detection terminal. A constant current is passed, and the voltage drop caused by this is detected by the output of the voltage detection terminal to measure the test pressure.
JP-A-60-1000047

  By the way, in the semiconductor pressure sensor described above, the output of the voltage detection terminal can be obtained simply by providing the cross-shaped piezoresistive element on the diaphragm portion of the semiconductor substrate without considering the plane orientation and crystal axis direction of the crystal lattice. There is a problem that it is difficult to obtain properly.

In view of the above, the present invention provides a pressure detection device including a pressure sensor that has been devised to form a radial piezoresistive element to ensure an appropriate detection output in order to deal with the above-described problems. With the goal.

In solving the above-described problem, the pressure detection device according to the present invention, according to the description of claim 1,
A pressure sensor comprising a semiconductor substrate (50) and a pressure detection element having a piezoresistive element (60) formed in a pressure receiving portion for receiving pressure in the semiconductor substrate;
A pressing member (90) for applying a load to the pressure receiving portion, and a pressure detecting device comprising:
The piezoresistive element has a piezoresistive element whose absolute value of the piezoresistive coefficient is greater than the half value between the minimum value and the maximum value on the midpoint portion (65) and the plane orientation (110) or a plane orientation equivalent to this plane orientation. An even number of resistive element portions (61 to 64) extending in a radial shape from the midpoint portion so as to include a crystal axis direction as a coefficient as one radial direction ;
The resistance element portion is formed so as to intersect at the midpoint portion .

As described above, the piezoresistive element includes the midpoint portion so as to include , as one radial direction, a crystal axis direction having a plane orientation (110) or a plane orientation equivalent to this plane orientation and a large absolute value of the piezoresistance coefficient. It has an even number of resistor elements formed in a radial shape that intersects at the midpoint portion .

  Therefore, when the piezoresistive element receives pressure, a large amount of change in the resistance value occurs in the piezoresistive element in the crystal axis direction where the absolute value of the piezoresistive coefficient is large.

  As a result, the detection output of the pressure sensor representing the pressure can be appropriately obtained by using such a resistance value change amount.

  The crystal axis direction in which the absolute value of the piezoresistance coefficient is large means that the piezo is greater than the half value between the minimum value and the maximum value of the absolute value of the piezoresistance coefficient in the plane orientation (110) or a plane orientation equivalent to this plane orientation. It means a crystal axis direction that becomes a resistance coefficient, and preferably a crystal axis direction <110> or a crystal axis direction equivalent to this crystal axis direction.

According to a second aspect of the present invention, there is provided a pressure detection device according to the present invention.
Before SL pressure voltage applying means for applying the two adjacent element unit each sequentially voltages adjacent to each other among the even number of the resistance element of the detection element (110,120~150, + Vcc) and,
Control means (100 ) having averaging means (160 to 163, 170 to 173, 180, 181 and 190) for averaging each midpoint voltage generated at the midpoint portion for each voltage application by the voltage application means ) .

  Thus, a voltage is sequentially applied to each of the adjacent resistance element portions adjacent to each other among the even number of resistance element portions of the pressure detection element, and the piezoresistance coefficient of each of the adjacent resistance element portions is applied for each voltage application. Each of the midpoint voltages generated at the midpoint portion is averaged based on the amount of change in the resistance value generated in the resistance element portion along the crystal axis direction having a large absolute value.

  Therefore, even if the above-described midpoint potential varies due to the pressure applied to the piezoresistive element in a biased manner, the above-described variation is absorbed by averaging the midpoint voltages. Thus, an appropriate averaged output is obtained as a detection result of the pressure.

According to a third aspect of the present invention, there is provided a pressure detection device according to the present invention.
A pressure sensor comprising a semiconductor substrate (50) and a pressure detection element having a piezoresistive element formed in a pressure receiving portion that receives pressure in the semiconductor substrate;
A pressing member for applying a load to the pressure receiving portion;
A pressure detecting device comprising a control means (100) ,
The piezoresistive element has a crystal orientation in which the absolute value of the piezoresistance coefficient is larger than the half value between the minimum value and the maximum value in the plane orientation (110) or a plane orientation equivalent to this plane orientation, and the crystal axis direction you characterized in that it is formed in a cross shape so as to conform to both the perpendicular crystal orientation.

  As described above, the piezoresistive element is aligned along both the plane orientation (110) or the crystal axis direction which has this plane orientation and has a large absolute value of the piezoresistance coefficient, and the crystal axis direction perpendicular to the crystal axis direction. It is formed in a cross shape.

  Therefore, when the piezoresistive element receives pressure, a large amount of change in the resistance value occurs in the piezoresistive element in the crystal axis direction where the absolute value of the piezoresistive coefficient is large. At this time, no change in resistance value occurs in the piezoresistive element in the crystal axis direction perpendicular to the crystal axis direction in which the absolute value of the piezoresistance coefficient is large.

  As a result, the detection output of the pressure sensor representing the pressure can be obtained more appropriately by using the resistance value change amount as described above.

Further, according to the third aspect of the present invention,
The semiconductor substrate is an n-type silicon substrate or an SOI substrate,
The piezoresistive element is formed of a p-type semiconductor material,
The crystal axis direction having a piezoresistance coefficient larger than the half value of the minimum value and the maximum value of the absolute value of the piezoresistance coefficient and the crystal axis direction perpendicular to the crystal axis direction are the crystal axis direction <110> or A crystal axis direction equivalent to the crystal axis direction and a crystal axis direction <100> or a crystal axis direction equivalent to the crystal axis direction.

By comprising in this way, said effect is further improved. In addition, the heat resistance is further improved by forming the semiconductor substrate with an SOI substrate. As a result, improvement in heat resistance and improvement in the above-described effects can be synergistically ensured.

Furthermore , according to the description of claim 3 , a pressure detection device according to the present invention is provided.
The piezoresistive element of the pressure detecting element has a midpoint portion (65) and four resistance element portions (61 to 64) extending in a cross shape from the midpoint portion,
The control means (100)
Voltage application means (110, 120 to 150, + Vcc) for applying a voltage to each of the adjacent resistance element portions adjacent to each other among the four resistance element portions of the pressure detection element;
And an averaging means (160 to 163, 170 to 173, 180, 181 and 190) for averaging each midpoint voltage generated at the midpoint portion each time voltage is applied by the voltage applying means. To do.

  As described above, a voltage is sequentially applied to each of the adjacent resistance element portions adjacent to each other among the four resistance element portions of the pressure detection element, and the piezoresistance coefficient of the both adjacent resistance element portions is applied for each voltage application. Each of the midpoint voltages generated at the midpoint portion is averaged based on the amount of change in the resistance value generated in the resistance element portion along the crystal axis direction having a large absolute value.

  Therefore, even if variation occurs in each of the above-described midpoint potentials due to the pressure applied to the piezoresistive element, by averaging each of the midpoint voltages, the variation is absorbed, The averaged output can be obtained as an appropriate value.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

Hereinafter, each embodiment of the present invention will be described with reference to the drawings.
(First embodiment)
1 and 4 show a first embodiment of a pressure detection device according to the present invention, and this pressure detection device is used, for example, to detect a pressure generated in a combustion chamber of an internal combustion engine mounted on an automobile. It is done.

  As shown in FIG. 1, the pressure detection device includes a pressure sensor, and this pressure sensor is mounted on the cylinder head 10 of the internal combustion engine. The pressure sensor includes a cylindrical casing 20, and the casing 20 is inserted into the through-hole portion 11 of the cylinder head 10 at its thin peripheral wall portion 21 and extends into the combustion chamber of the internal combustion engine. I'm out.

  Further, the housing 20 has a diaphragm 22, and this diaphragm 22 is provided at the distal end portion of the thin peripheral wall portion 21 and constitutes the bottom wall of the housing 20. The casing 20 is seated on the outer peripheral portion of the through-hole portion 11 of the cylinder head 10 via the ring-shaped gasket 12 at the thick peripheral wall portion 23. The housing 20 is formed of a metal material including the diaphragm 22.

  The pressure sensor includes a disk-shaped pedestal 30, a glass plate 40, a semiconductor substrate 50, a resistance element 60, a protective film 70, and a glass plate 80 as shown in FIG. 1 or FIG.

  The pedestal 30 is made of an electrically insulating material, and the pedestal 30 is coaxially fitted in the axially intermediate portion within the thin peripheral wall portion 21 of the housing 20. Note that the pedestal 30 may be formed of a metal material. In this case, it is desirable to perform an insulation process between the terminals described later.

  The glass plate 40 is coaxially fixed to the pedestal 30 from the surface side, and the glass plate 40 plays a role of reducing the distortion effect from the pedestal 30.

  The semiconductor substrate 50 is made of an n-type silicon substrate having a plane orientation (110) as a pressure receiving surface, and the semiconductor substrate 50 is bonded to the surface of the glass plate 40 at the back surface.

  The resistance element 60 is configured by a p-type semiconductor formed in a cross shape on the surface of the semiconductor substrate 50 by diffusion of impurities (for example, boron). That is, as shown in FIG. 2, the resistance element 60 is configured by extending each of the resistance element portions 61 to 64 from the intersection part 65 in a cross shape with the intersection part 65 as a center.

  Accordingly, the two resistive element portions 61 and 63 extend linearly in opposite directions from the crossing portion 65, while the two resistive element portions 62 and 64 are orthogonal to the two resistive element portions 61 and 63. In addition, they extend linearly in opposite directions from the crossover portion 65.

  In the first embodiment, both resistance element portions 61 and 63 are formed along the crystal axis direction <100> on the pressure-receiving surface of the n-type silicon substrate. The two resistance element portions 62 and 64 are formed along the crystal axis direction <110> on the pressure-receiving surface of the n-type silicon substrate.

  Here, the crossover portion 65 includes a midpoint portion between both resistance element portions 61 and 62, a midpoint portion between both resistance element portions 62 and 63, a midpoint potential between both resistance element portions 63 and 64, and both resistance elements. A midpoint potential between the parts 64 and 61 is formed. In addition, each resistance element part 61-64 has the same resistance value (henceforth resistance value R), when not receiving the pressure so that it may mention later.

  Further, as shown in FIG. 2, the resistance element 60 includes electrode pads 66 to 69, and the electrode pads 66 and 68 are formed on the surface of the semiconductor substrate 50 with the resistance element portions 61 and 63. It is formed integrally with each extending end. The electrode pads 67 and 69 are formed integrally with the extended end portions of the two resistance element portions 62 and 64 on the surface of the semiconductor substrate 50.

  The protective film 70 is provided on the surface of the semiconductor substrate 50 so as to cover the resistance element 60 except for the electrode pads 66 to 69.

  Here, in the first embodiment, as described above, an n-type silicon substrate having a plane orientation (110) as the pressure receiving surface is employed as the semiconductor substrate 50, and the resistance element 60 is disposed on the pressure receiving surface of the n-type silicon substrate. The grounds for adopting the configuration of forming a cross shape along the crystal axis direction <100> and the crystal axis direction <110> will be described.

  That is, when a resistance element made of a p-type semiconductor is formed in the plane orientation (110) and pressure is applied in a direction perpendicular to the plane orientation, how does the dependence of the piezoresistance coefficient of the resistance element in the crystal axis direction change? The change in the piezoresistance coefficient is maximized in the crystal axis direction <110> as shown by the graph 1 in FIG. 3, but in the crystal axis direction <100>, the crystal axis direction changes. It was confirmed that it was negligibly small compared to <110>.

  Therefore, according to the dependency of the piezoresistance coefficient in the crystal axis direction, it is understood that the resistance element 60 changes in resistance value in both the resistance element portions 62 and 64 when subjected to pressure. Then, it was found that the pressure can be appropriately detected by applying a voltage to the resistance element 60 as will be described later on the assumption that the piezoresistance coefficient depends on the crystal axis direction.

  Therefore, in the first embodiment, as described above, the resistive element 60 is formed in a cross shape along the crystal axis direction <100> and the crystal axis direction <110> in the plane orientation (110) of the n-type silicon substrate. It was decided to form. Here, the crystal axis direction <110> corresponds to a direction in which the absolute value of the piezoresistance coefficient is large, and the crystal axis direction <100> has a small absolute value of the piezoresistance coefficient in the plane orientation (110). Corresponds to the direction.

  The glass plate 80 is bonded to the surface of the protective film 70 so as to cover the resistive element 60 via the protective film 70 on the back surface thereof. The glass plate 80 protects the resistive element 60 together with the protective film 70. To play a role. The glass plate 40, the semiconductor substrate 50, the resistance element 60, the protective film 70, and the glass plate 80 constitute a detection element of the pressure sensor.

  The pressure sensor has a cylindrical rod 90 made of a metal material. The rod 90 is coaxial between the diaphragm 22 and the glass plate 80 in the thin peripheral wall portion 21 of the housing 20. Is sandwiched between. Thus, the rod 90 is axially moved upward in accordance with the upward displacement of the diaphragm 22 in FIG. 1 to press the resistance element 60 onto the surface of the semiconductor substrate 50 through the glass plate 80. This means that the rod 90 applies a load to the resistance element 60 through the glass plate 80.

  As shown in FIG. 4, the pressure detection device includes a control circuit 100, and the control circuit 100 is fitted in an axial intermediate portion of the housing 20 as shown in FIG. 1.

  As shown in FIGS. 4 and 5, the control circuit 100 includes a gate signal generation circuit 110. The gate signal generation circuit 110 includes a clock circuit 111 and both frequency dividing circuits 111- as shown in FIG. 1 and 111-2.

The clock circuit 111 sequentially generates a clock pulse signal C having a predetermined period T (see FIG. 6). In the first embodiment, if the time is t (see FIG. 6), the predetermined period T is T = t _{i + 1} −t _i (i = 1, 2, 3,...).

The frequency dividing circuit 111-1 divides the clock pulse signal C sequentially generated from the clock circuit 111, and sequentially generates the frequency divided pulse signal B1 having a period 2T that is twice the period T of the clock pulse signal C. . In the first embodiment, the period 2T is 2T = t _{2 + i} −t _i .

The frequency divider circuit 111-2 divides the frequency-divided pulse signal B1 sequentially generated from the frequency divider circuit 111-1, and the frequency-divided pulse signal having a period 4T that is twice the period 2T of the frequency-divided pulse signal B1. B2 is generated (see FIG. 6). In the first embodiment, the period 4T is 4T = t _{4 + i} −t _i .

  The gate signal generation circuit 110 has four AND gates 112 to 115. The AND gate 112 takes the logical product of the frequency-divided pulse signal B1 from the frequency-dividing circuit 111-1 and the frequency-divided pulse signal B2 from the frequency-dividing circuit 111-2, and calculates the time tk (k = 1, 5, 9,. ..) a gate signal (hereinafter referred to as a gate signal G1) is generated.

  The AND gate 113 takes the logical product of the inverted signal of the frequency-divided pulse signal B1 from the frequency divider 111-1 and the frequency-divided pulse signal B2 from the frequency-divided circuit 111-2, and calculates the time tm (m = 2, 6, 10), a gate signal (hereinafter referred to as a gate signal G2) is generated.

  The AND gate 114 calculates the logical product of the frequency-divided pulse signal B1 from the frequency-dividing circuit 111-1 and the inverted signal of the frequency-divided pulse signal B2 from the frequency-divided circuit 111-2, and calculates the time tn (n = 3, 7, 11), a gate signal (hereinafter referred to as a gate signal G3) is generated.

  The AND gate 115 calculates the logical product of the inverted signal of the divided pulse signal B1 from the frequency dividing circuit 111-1 and the inverted signal of the divided pulse signal B2 from the frequency dividing circuit 111-2, and calculates the time tp (p = 4). , 8, 12,...), A gate signal (hereinafter referred to as a gate signal G4) is generated.

  The gate signal generation circuit 110 has four OR gates 116 to 119. The OR gate 116 performs a logical sum of outputs from the AND gate 112, the AND gate 114, and the AND gate 115. Accordingly, the OR gate 116 outputs the gate signal G1, G3, or G4 from the AND gate 112, 114, or 115 (see FIG. 6).

Here, for example, the gate signal G1 is generated during the time t = t _{1 to} t = t ₂ , the gate signal G3 is generated during the time t = t _{3 to} t = t ₄ , and the gate signal G4 is Occurs between time t = t _{4 and} t = t ₅ (see FIG. 6).

The OR gate 117 calculates the logical sum of the outputs from the AND gate 112, the AND gate 113, and the AND gate 115. As a result, the OR gate 117 outputs the gate signal G1, G2, or G4 from the AND gate 112, 113, or 115 (see FIG. 6). Here, the gate signal G2 is generated, for example, during the time t = t _{2 to} t = t ₃ (see FIG. 6).

  The OR gate 118 calculates the logical sum of the outputs from the AND gate 112, the AND gate 113, and the AND gate 114. Thereby, the OR gate 118 outputs the gate signal G1, G2 or G3 from the AND gate 112, 113 or 114 (see FIG. 6).

  The OR gate 119 takes the logical sum of the outputs from the AND gate 113, the AND gate 114, and the AND gate 115. Thereby, the OR gate 119 outputs the gate signal G2, G3 or G4 from the AND gate 113, 114 or 115 (see FIG. 6).

  Further, as shown in FIG. 4, the control circuit 100 includes four analog switches 120 to 150, and the analog switch 120 is connected to the output terminal of the OR gate 116 of the gate signal generation circuit 110 at the gate terminal 121. It is connected.

  The analog switch 120 is connected to the electrode pad 66 of the resistance element 60 at the input terminal 122, and the analog switch 120 is connected to the positive electrode + Vcc of the DC power source at the output terminal 123. . The analog switch 120 is grounded at the output terminal 124, and the output terminal 125 of the analog switch 120 is connected to the input terminal of the arithmetic circuit 160.

  Thus, the analog switch 120 receives gate signals G1, G3, and G4 (see FIG. 6) sequentially from the OR gate 116 at the gate terminal 121, and sequentially inputs the input terminal 122 to the output terminals 123, 125, and Switch to connect to 124.

  In other words, the analog switch 120 sequentially connects the electrode pad 66 of the resistance element 60 to the positive electrode + Vcc of the DC power source based on the gate signals G1, G3, and G4 sequentially output from the OR gate 116, The operation circuit 160 is switched to be connected and grounded.

  The analog switch 130 is connected to the output terminal of the OR gate 117 of the gate signal generation circuit 110 at the gate terminal 131. The analog switch 130 is connected to the electrode pad 67 of the resistance element 60 at the input terminal 132, and the analog switch 130 is connected to the positive electrode + Vcc of the DC power supply at the output terminal 133. . The analog switch 130 is grounded at the output terminal 134, and the output terminal 135 of the analog switch 130 is connected to the input terminal of the arithmetic circuit 161.

  Thus, the analog switch 130 receives gate signals G1, G2, and G4 (see FIG. 6) sequentially from the OR gate 117 at the gate terminal 131, and sequentially inputs the input terminal 132 to the output terminals 134, 133, and Switch to connect to 135.

  In other words, the analog switch 130 sequentially grounds the electrode pads 67 of the resistance element 60 based on the gate signals G1, G2, and G4 sequentially output from the OR gate 117, and connects the positive electrode + Vcc of the DC power supply to the positive electrode + Vcc. Switching to connect and connect to the arithmetic circuit 161.

  The analog switch 140 is connected to the output terminal of the OR gate 118 of the gate signal generation circuit 110 at the gate terminal 141. The analog switch 140 is connected to the electrode pad 68 of the resistance element 60 at the input terminal 142. The analog switch 140 is connected to the positive electrode + Vcc of the DC power supply at the output terminal 143. . The analog switch 140 is grounded at the output terminal 144, and the output terminal 145 of the analog switch 140 is connected to the input terminal of the arithmetic circuit 162.

  Thus, the analog switch 140 receives gate signals G1, G2, and G3 (see FIG. 6) sequentially from the OR gate 118 of the gate signal generation circuit 110 at the gate terminal 141, and sequentially inputs the input terminal 142 to the respective terminals. It is switched to connect to the output terminals 145, 144 and 143.

  In other words, the analog switch 140 sequentially connects the electrode pads 68 of the resistance element 60 to the arithmetic circuit 162 based on the gate signals G1, G2, and G3 sequentially output from the OR gate 118, grounds, and the DC It is switched to connect to the positive electrode + Vcc of the power supply.

  The analog switch 150 is connected to the output terminal of the OR gate 119 of the gate signal generation circuit 110 at the gate terminal 151. The analog switch 150 is connected to the electrode pad 69 of the resistance element 60 at the input terminal 152. The analog switch 150 is connected to the positive electrode + Vcc of the DC power supply at the output terminal 153. . The analog switch 150 is grounded at the output terminal 154, and the output terminal 155 of the analog switch 150 is connected to the input terminal of the arithmetic circuit 163.

  Therefore, the analog switch 150 receives gate signals G2, G3, and G4 (see FIG. 6) sequentially from the OR gate 119 of the gate signal generation circuit 110 at the gate terminal 151, and sequentially inputs the input terminal 152 to the respective terminals. It is switched to connect to output terminals 155, 154 and 153.

  In other words, the analog switch 150 sequentially connects the electrode pads 69 of the resistance element 60 to the arithmetic circuit 163 based on the gate signals G2, G3, and G4 sequentially output from the OR gate 119, grounds, and the DC It is switched to connect to the positive electrode + Vcc of the power supply.

  According to the above, when each of the OR gates 116, 117, and 118 outputs the gate signal G1 (see FIG. 6), the analog switch 120 connects the electrode pad 66 of the resistance element 60 to the positive terminal + Vcc of the DC power source. The analog switch 130 grounds the electrode pad 67 of the resistance element 60, and the analog switch 140 connects the electrode pad 68 of the resistance element 60 to the arithmetic circuit 162.

  Thus, as the electrode pad 68 is connected to the input terminal of the arithmetic circuit 162, the DC power supply supplies the electrode pad 66 to the positive side and the electrode pad 67 to the negative side, and applies a positive DC voltage to both electrode pads. Applied between 66 and 67, a midpoint potential is generated at the crossing portion 65 of the resistance element 60. At this time, the analog switch 150 is in an off state and maintains the electrode pad 69 of the resistance element 60 in an open state.

  When each of the OR gates 117, 118, and 119 outputs the gate signal G2 (see FIG. 6), the analog switch 130 connects the electrode pad 67 of the resistance element 60 to the positive terminal + Vcc of the DC power supply. The analog switch 140 grounds the electrode pad 68 of the resistance element 60, and the analog switch 150 connects the electrode pad 69 of the resistance element 60 to the arithmetic circuit 163.

  Thus, as the electrode pad 69 is connected to the input terminal of the arithmetic circuit 163, the DC power supply supplies the positive DC voltage to both electrode pads with the electrode pad 67 on the positive side and the electrode pad 68 on the negative side. Applied between 67 and 68, a midpoint potential is generated at the crossing portion 65 of the resistance element 60. At this time, the analog switch 120 is in an off state and maintains the electrode pad 66 of the resistance element 60 in an open state.

  When each of the OR gates 118, 119, and 116 outputs a gate signal G3 (see FIG. 6), the analog switch 140 connects the electrode pad 68 of the resistance element 60 to the positive terminal + Vcc of the DC power supply. The analog switch 150 grounds the electrode pad 69 of the resistance element 60, and the analog switch 120 connects the electrode pad 66 of the resistance element 60 to the arithmetic circuit 160.

  Thus, as the electrode pad 66 is connected to the input terminal of the arithmetic circuit 160, the DC power supply supplies the positive DC voltage to both electrode pads with the electrode pad 68 on the positive side and the electrode pad 69 on the negative side. Applied between 68 and 69, a midpoint potential is generated at the crossing portion 65 of the resistance element 60. At this time, the analog switch 130 is in an off state and maintains the electrode pad 67 of the resistance element 60 in an open state.

  When each of the OR gates 119, 116, 117 outputs a gate signal G4 (see FIG. 6), the analog switch 150 connects the electrode pad 69 of the resistance element 60 to the positive terminal + Vcc of the DC power supply. The analog switch 120 grounds the electrode pad 66 of the resistance element 60, and the analog switch 130 connects the electrode pad 67 of the resistance element 60 to the arithmetic circuit 161.

  As a result, as the electrode pad 67 is connected to the input terminal of the arithmetic circuit 161, the DC power supply uses the electrode pad 69 as the positive side and the electrode pad 66 as the negative side, and applies a positive DC voltage to both electrode pads. Applied between 69 and 66, a midpoint potential is generated at the crossing portion 65 of the resistance element 60. At this time, the analog switch 140 is in an off state and maintains the electrode pad 68 of the resistance element 60 in an open state.

  Each of the arithmetic circuits 160 to 163 is configured with an operational amplifier having an infinite input impedance. The arithmetic circuit 160 receives and amplifies the midpoint potential of the resistance element 60 via the electrode pad 66 and the analog switch 120, and outputs the amplified voltage to the sample and hold circuit 170. The arithmetic circuit 161 receives and amplifies the midpoint potential of the resistance element 60 via the electrode pad 67 and the analog switch 130, and outputs the amplified voltage to the sample and hold circuit 171.

  The arithmetic circuit 162 receives and amplifies the midpoint potential of the resistance element 60 via the electrode pad 68 and the analog switch 140 and outputs the amplified voltage to the sample hold circuit 172. The arithmetic circuit 163 receives and amplifies the midpoint potential of the resistance element 60 via the electrode pad 69 and the analog switch 150, and outputs the amplified voltage to the sample hold circuit 173.

  The sample hold circuit 170 samples and holds the amplified voltage from the arithmetic circuit 160 and outputs it to the averaging circuit 180 as a sample hold voltage. The sample hold circuit 171 samples and holds the amplified voltage from the arithmetic circuit 161 and outputs it to the averaging circuit 181 as a sample hold voltage.

  The sample hold circuit 172 samples and holds the amplified voltage from the arithmetic circuit 162 and outputs it to the averaging circuit 180 as a sample hold voltage. The sample hold circuit 173 samples and holds the amplified voltage from the arithmetic circuit 163 and outputs it to the averaging circuit 181 as the sample hold voltage.

  The averaging circuit 180 averages the sample and hold voltages from both the sample and hold circuits 170 and 172 by arithmetic averaging to generate an average voltage. The averaging circuit 181 generates an averaged voltage by averaging the sample and hold voltages from both the sample and hold circuits 171 and 173 by arithmetic averaging.

  The difference calculation circuit 190 calculates the difference between both averaged voltages from both the averaging circuits 180 and 181 to generate a difference voltage.

  Next, a process for manufacturing the resistance element 60 and the protective film 70 on the semiconductor substrate 50 described above will be described. As the semiconductor substrate 50, an n-type silicon wafer 51 having a thickness of 400 (μm) and a resistance value within a range of 10 (Ωcm) to 20 (Ωcm) is prepared (see FIG. 7).

  After both thermal oxide films 52 are formed on both sides of the silicon wafer 51 with a film thickness of 100 (nm), the thermal oxide film 52 (hereinafter referred to as the surface) on the surface side of the silicon wafer 51 of the both thermal oxide films 52 is formed. A mask is applied to the side thermal oxide film 52), and a cross-shaped portion 53 corresponding to the outer shape of the resistance element 60 is formed on the thermal oxide film 52 by patterning (see FIG. 8). Here, the cross-shaped portion 53 is formed on the thermal oxide film 52 in a cross shape that extends along both the crystal axis direction <100> and the crystal axis direction <110> in the plane orientation (110) of the silicon wafer 51. .

Next, boron is implanted into the surface of the silicon wafer 51 through the surface-side thermal oxide film 52 by an ion implantation apparatus, and then at a temperature of 950 (° C.) in a nitrogen N ₂ gas atmosphere for 30 (minutes). A resistance element 60 made of a p-type semiconductor is formed by annealing treatment (see FIG. 9). The concentration of boron is 20 (atoms / cm ³ ).

  Thereafter, an HTO film having a thickness of 300 (nm) is formed as a protective film 70 on the surface of the silicon wafer 51 so as to cover the resistance element 60 (see FIG. 10).

  Next, the corresponding portions of the protective film 70 corresponding to the electrode pads 66 to 69 are etched to form the contact holes 53 (see FIG. 11).

  Thereafter, after forming a metal film on the protective film 70, the metal film is subjected to patterning to form the electrode pads 66 to 69 (see FIG. 12).

  Then, both glass plates 40 and 80 are bonded to the back surface of the silicon wafer 51 and the surface of the protective film 70 by anodic bonding, and then the glass plate 40 is fixed to the pedestal 30 with an adhesive.

  Then, as can be seen from FIG. 1, each terminal 31 is inserted into the pedestal 30, and one end of each terminal 31 is connected to each corresponding electrode pad 66 to 69 by each bonding wire 32.

In the first embodiment configured as described above, when the pressure in the combustion chamber of the engine is applied uniformly over the entire surface of the resistance element 60, and when the pressure is applied with an inclination to the surface of the resistance element 60, An example of detection by the pressure sensor will be described separately. It is assumed that the pressure sensor is in an operating state.
1. When the pressure in the combustion chamber of the engine is uniformly applied over the entire surface of the resistance element 60. When the axial direction of the rod 90 is perpendicular to the surface of the semiconductor substrate 50, the pressure in the combustion chamber is as shown in FIG. As indicated by the solid arrow 2, the rod 90 is applied perpendicularly to the surface of the resistance element 60 through the glass plate 80. Therefore, the pressure is applied uniformly over the entire surface of the resistance element 60 as shown by the region 3 surrounded by a two-dot chain line in FIG. This means that the uniform load acts on the surface of the semiconductor substrate 50, in other words, the surface of the resistance element 60.

  Here, as described above, the resistance element 60 is formed in a cross shape along the crystal axis direction <100> and the crystal axis direction <110> in the plane orientation (110) of the semiconductor substrate 50. For this reason, as shown in FIG. 3, the resistance change of the resistance element in the crystal axis direction <100> is negligibly small compared to the resistance change of the resistance element in the crystal axis direction <110>. Among them, the resistance value change occurs only in the resistance element portions 62 and 64 in the crystal axis direction <110>.

  Therefore, if the resistance values of the resistance element portions 61 to 64 are R1 to R4, R1≈R3≈R and R2 = R4 = R + ΔR. Here, ΔR is an increase in resistance value caused by each resistance value change of each of the resistance element portions 62 and 64 described above, and is proportional to the pressure.

  In such a state, when each of the OR gates 116, 117, and 118 of the gate signal generation circuit 110 outputs the gate signal G1 (see FIG. 6) at t = t1, as described above, the analog switch 120 is turned on. Switching is made based on the gate signal G1 from the gate 116 to connect the electrode pad 66 of the resistance element 60 to the positive terminal + Vcc of the DC power supply, and the analog switch 130 grounds the electrode pad 67 of the resistance element 60 to The switch 140 connects the electrode pad 68 of the resistance element 60 to the arithmetic circuit 162. At this time, the analog switch 150 is in an off state and maintains the electrode pad 69 of the resistance element 60 in an open state.

  Therefore, the resistance element 60 is applied with a positive DC voltage from the DC power source with the electrode pad 66 on the positive side and the electrode pad 67 on the negative side. Therefore, this DC voltage is applied to a series circuit including the resistance element portion 61, the crossover portion 65, and the resistance element portion 62 of the resistance element 60. In accordance with this, the crossing portion 65 of the resistance element 60 is connected to the input terminal of the arithmetic circuit 162 via the resistance element portion 63 and the electrode pad 68.

  In such a state, if the positive DC voltage is V, as described above, the resistance value of the resistance element unit 61 is R1≈R, and the resistance value of the resistance element unit 62 is R2 = R + ΔR. Therefore, the potential of the crossing portion 65, that is, the midpoint potential (hereinafter referred to as the midpoint potential VM) is expressed by the following formula (1).

VM = VM1 = R2 ・ V / (R1 + R2) ≒ (R + ΔR) ・ V / (2R + ΔR) ... (1)
Therefore, the arithmetic circuit 162 receives the midpoint potential VM1 from the crossover portion 65 of the resistance element 60 via the resistance element portion 63 and the electrode pad 68, amplifies it, and outputs it to the sample hold circuit 172 as an amplified voltage. Accordingly, the amplified voltage is sampled and held by the sample and hold circuit 172 as a sample and hold voltage.

  Next, when each of the OR gates 117, 118, and 119 of the gate signal generation circuit 110 outputs the gate signal G2 (see FIG. 6) at t = t2, as described above, the analog switch 130 causes the electrode of the resistance element 60 to be output. The pad 67 is connected to the positive terminal + Vcc of the DC power supply, the analog switch 140 grounds the electrode pad 68 of the resistance element 60, and the analog switch 150 connects the electrode pad 69 of the resistance element 60 to the arithmetic circuit 163. . At this time, the analog switch 120 is in an off state and maintains the electrode pad 66 of the resistance element 60 in an open state.

  For this reason, the resistance element 60 is applied with a positive DC voltage V from the DC power source with the electrode pad 67 on the positive side and the electrode pad 68 on the negative side. Accordingly, the DC voltage V is applied to a series circuit including the resistance element portion 62, the crossover portion 65, and the resistance element portion 63 of the resistance element 60. In accordance with this, the crossing portion 65 of the resistance element 60 is connected to the input terminal of the arithmetic circuit 163 via the resistance element portion 64 and the electrode pad 69.

  In such a state, as described above, the resistance value of the resistance element portion 62 is R2 = R + ΔR, and the resistance value of the resistance element portion 63 is R3≈R. = VM2 is expressed by the following equation (2).

VM = VM2 = R2 ・ V / (R2 + R3) ≒ R ・ V / (2R + ΔR) ・ ・ ・ ・ ・ ・ ・ ・ (2)
Accordingly, the arithmetic circuit 163 receives the midpoint potential VM2 from the crossing portion 65 of the resistance element 60 via the resistance element portion 64 and the electrode pad 69, amplifies it, and outputs it as an amplified voltage to the sample hold circuit 173. Along with this, the amplified voltage is sampled and held by the sample and hold circuit 173 as a sample and hold voltage.

  Next, when each of the OR gates 118, 119, and 116 of the gate signal generation circuit 110 outputs the gate signal G3 (see FIG. 6) at t = t3 as described above, the analog switch 140 causes the electrode of the resistance element 60 to be output. The pad 68 is connected to the positive terminal + Vcc of the DC power supply, the analog switch 150 grounds the electrode pad 69 of the resistance element 60, and the analog switch 120 connects the electrode pad 66 of the resistance element 60 to the arithmetic circuit 160. . At this time, the analog switch 130 is in an off state and maintains the electrode pad 67 of the resistance element 60 in an open state.

  For this reason, the resistance element 60 is applied with a positive DC voltage V from the DC power source with the electrode pad 68 on the positive side and the electrode pad 69 on the negative side. Accordingly, the DC voltage V is applied to a series circuit including the resistance element portion 63, the crossover portion 65, and the resistance element portion 64 of the resistance element 60. In accordance with this, the crossing portion 65 of the resistance element 60 is connected to the input terminal of the arithmetic circuit 160 via the resistance element portion 61 and the electrode pad 66.

  In such a state, as described above, the resistance value of the resistance element portion 63 is R3≈R, and the resistance value of the resistance element portion 64 is R4 = R + ΔR. = VM3 is expressed by the following equation (3).

VM = VM3 = R4 ・ V / (R3 + R4) ≒ (R + ΔR) ・ V / (2R + ΔR) ... (3)
Accordingly, the arithmetic circuit 160 receives the midpoint potential VM3 from the crossover portion 65 of the resistance element 60 via the resistance element portion 61 and the electrode pad 66, amplifies it, and outputs it to the sample hold circuit 170 as an amplified voltage. Along with this, the amplified voltage is sampled and held by the sample and hold circuit 170 as a sample and hold voltage.

  Then, when each of the OR gates 119, 116, 117 of the gate signal generation circuit 110 outputs the gate signal G4 (see FIG. 6) at t = t4 as described above, the analog switch 150 causes the electrode of the resistance element 60 to be output. The pad 69 is connected to the positive terminal + Vcc of the DC power source, the analog switch 120 grounds the electrode pad 66 of the resistance element 60, and the analog switch 130 connects the electrode pad 67 of the resistance element 60 to the arithmetic circuit 161. . At this time, the analog switch 140 is in an off state and maintains the electrode pad 68 of the resistance element 60 in an open state.

  For this reason, the resistance element 60 is applied with a positive DC voltage V from the DC power source with the electrode pad 69 on the positive side and the electrode pad 66 on the negative side. Accordingly, the DC voltage V is applied to a series circuit including the resistance element portion 64, the crossover portion 65, and the resistance element portion 61 of the resistance element 60. In accordance with this, the crossing portion 65 of the resistance element 60 is connected to the input terminal of the arithmetic circuit 161 via the resistance element portion 62 and the electrode pad 67.

  In such a state, as described above, the resistance value of the resistance element portion 64 is R4 = R + ΔR, and the resistance value of the resistance element portion 61 is R1≈R. = VM4 is expressed by the following equation (4).

VM = VM4 = R1 ・ V / (R4 + R1) ≒ R ・ V / (2R + ΔR) ・ ・ ・ ・ ・ ・ ・ ・ (4)
Accordingly, the arithmetic circuit 161 receives the midpoint potential VM4 from the crossing portion 65 of the resistance element 60 via the resistance element portion 62 and the electrode pad 67, amplifies it, and outputs it to the sample hold circuit 171 as an amplified voltage. Accordingly, the amplified voltage is sampled and held by the sample and hold circuit 171 as a sample and hold voltage.

  When the sample-and-hold is completed as described above, the averaging circuit 180 averages the sample-and-hold voltages from both the sample-and-hold circuits 170 and 172 to generate an averaged voltage (hereinafter referred to as an averaged voltage VA1). Here, the averaged voltage VA1 of the averaging circuit 180 is expressed by the following formula (5) based on both formulas (1) and (3).

VA1 = (VM1 + VM3) / 2 = (R + ΔR) ・ V / (2R + ΔR) (5)
The averaging circuit 181 averages the sample and hold voltages from both the sample and hold circuits 171 and 173 to generate an average voltage (hereinafter referred to as an average voltage VA2). Here, the averaged voltage VA2 of the averaging circuit 181 is expressed by the following equation (6) based on both equations (2) and (4).

VA2 = (VM2 + VM4) / 2 = R ・ V / (2R + ΔR) (6)
Next, the difference calculation circuit 190 calculates a difference between the averaged voltages VA1 and VA2 from the two averaging circuits 180 and 181 to generate a difference voltage (hereinafter referred to as difference voltage VA). Here, the differential voltage VA of the averaging circuit 181 is expressed by the following equation (7) based on both equations (5) and (6).

VA = VA1-VA2 = ΔR ・ V / (2R + ΔR) ≒ ΔR ・ V / (2R) ・ ・ ・ ・ ・ ・ (7)
However, in Equation (7), ΔR is negligibly small as compared with 2R. The differential voltage VA is proportional to ΔR, and ΔR is proportional to the pressure. Therefore, the differential voltage VA is proportional to the pressure. Therefore, it can be seen that the pressure is obtained based on the differential voltage VA.
2. When the pressure in the combustion chamber of the engine is applied with an inclination with respect to the surface of the resistance element 60 When the axial direction of the rod 90 is inclined with respect to the surface of the semiconductor substrate 50 as indicated by a two-dot chain line in FIG. The pressure in the combustion chamber is applied in an oblique direction with respect to the surface of the resistance element 60 through the glass plate 80 with the rod 90 as shown by the two-dot chain line arrow 4 in FIG. This means that the unbalanced load acts on the surface of the semiconductor substrate 50, in other words, the surface of the resistance element 60.

  For example, in the case of this uneven load, the pressure distribution on the surface of the semiconductor substrate 50 is represented by pressure distribution isobaric lines 5 to 9 as shown by a two-dot chain line in FIG. In the present embodiment, the pressure distribution isobaric line 7 on the crossing portion 65 of the resistance element 60 represents the pressure reference value 1. The pressure distribution isobaric line 5 represents the pressure 1.2, the pressure distribution isobaric line 6 represents the pressure 1.1, the pressure distribution isobaric line 8 represents the pressure 0.9, and the pressure distribution isobaric line 9 represents the pressure 0. 8 is assumed to be represented.

  Here, as described above, the resistance element 60 is formed in a cross shape along the crystal axis direction <100> and the crystal axis direction <110> in the plane orientation (110) of the semiconductor substrate 50. For this reason, as shown in FIG. 3, the resistance value changes only in the resistance element portions 62 and 64 in the crystal axis direction <110> of the resistance element 60.

  Therefore, among the resistance values R1 to R4 of the resistance element portions 61 to 64, R1≈R3≈R, as described above. However, it is assumed that the resistance value of the resistance element portion 62 is R2 = R + ΔR2 and the resistance value of the resistance element portion 64 is R4 = R + ΔR4 due to the above-described uneven load.

  In such a state, when each of the OR gates 116, 117, 118 of the gate signal generation circuit 110 outputs the gate signal G1 (see FIG. 6) at t = t1, the analog switch 120 is The electrode pad 66 of the resistance element 60 is connected to the positive terminal + Vcc of the DC power supply, the analog switch 130 grounds the electrode pad 67 of the resistance element 60, and the analog switch 140 calculates the electrode pad 68 of the resistance element 60. Connect to circuit 162.

  For this reason, a positive DC voltage from the DC power source is applied to a series circuit including the resistance element portion 61, the crossover portion 65, and the resistance element portion 62, as described above. In accordance with this, the crossing portion 65 of the resistance element 60 is connected to the input terminal of the arithmetic circuit 162 via the resistance element portion 63 and the electrode pad 68.

In such a state, as described above, the resistance value of the resistance element portion 61 is R1≈R, and the resistance value of the resistance element portion 62 is R2 = R + ΔR2. = VM11 is expressed by the following equation (8).
It is expressed as such.

VM = VM11 = R2 ・ V / (R1 + R2)
≒ (R + ΔR2) ・ V / (2R + ΔR2) ... (8)
Accordingly, the arithmetic circuit 162 receives the midpoint potential VM11 from the crossover portion 65 of the resistance element 60 via the resistance element portion 63 and the electrode pad 68, amplifies it, and outputs it to the sample hold circuit 172 as an amplified voltage. Accordingly, the amplified voltage is sampled and held by the sample and hold circuit 172 as a sample and hold voltage.

  Next, when each of the OR gates 117, 118, and 119 of the gate signal generation circuit 110 outputs the gate signal G2 (see FIG. 6) at t = t2, similarly to the above, the analog switch 130 is connected to the resistance element 60. The electrode pad 67 is connected to the positive terminal + Vcc of the DC power source, the analog switch 140 grounds the electrode pad 68 of the resistance element 60, and the analog switch 150 connects the electrode pad 69 of the resistance element 60 to the arithmetic circuit 163. To do.

  For this reason, the positive DC voltage V from the DC power source is applied to a series circuit including the resistance element portion 62, the crossover portion 65, and the resistance element portion 63 of the resistance element 60, as described above. In accordance with this, the crossing portion 65 of the resistance element 60 is connected to the input terminal of the arithmetic circuit 163 via the resistance element portion 64 and the electrode pad 69.

  In such a state, as described above, the resistance value of the resistance element portion 62 is R2 = R + ΔR2, and the resistance value of the resistance element portion 63 is R3≈R. = VM22 is expressed by the following equation (9).

VM = VM22 = R2 ・ V / (R2 + R3)
≒ R ・ V / (2R + ΔR2) ... (9)
Thus, the arithmetic circuit 163 receives the midpoint potential VM22 from the crossing portion 65 of the resistance element 60 via the resistance element portion 64 and the electrode pad 69, amplifies it, and outputs it to the sample hold circuit 173 as an amplified voltage. Along with this, the amplified voltage is sampled and held by the sample and hold circuit 173 as a sample and hold voltage.

  Then, as described above, when each of the OR gates 118, 119, and 116 of the gate signal generation circuit 110 outputs the gate signal G3 (see FIG. 6) at t = t3, the analog switch 140 The electrode pad 68 is connected to the positive terminal + Vcc of the DC power source, the analog switch 150 grounds the electrode pad 69 of the resistance element 60, and the analog switch 120 connects the electrode pad 66 of the resistance element 60 to the arithmetic circuit 160. To do.

  For this reason, the positive DC voltage V from the DC power source is applied to a series circuit including the resistance element portion 63, the crossover portion 65, and the resistance element portion 64, as described above. In accordance with this, the crossing portion 65 of the resistance element 60 is connected to the input terminal of the arithmetic circuit 160 via the resistance element portion 61 and the electrode pad 66.

  In such a state, as described above, the resistance value of the resistance element portion 63 is R3≈R, and the resistance value of the resistance element portion 64 is R4 = R + ΔR4. Is expressed by the following formula (10).

VM = VM33 = R4 ・ V / (R3 + R4)
≒ (R + ΔR4) ・ V / (2R + ΔR4) ... (10)
Accordingly, the arithmetic circuit 160 receives the midpoint potential VM33 from the crossover portion 65 of the resistance element 60 via the resistance element portion 61 and the electrode pad 66, amplifies it, and outputs it to the sample hold circuit 170 as an amplified voltage. Along with this, the amplified voltage is sampled and held by the sample and hold circuit 170 as a sample and hold voltage.

  Next, when each of the OR gates 119, 116, and 117 of the gate signal generation circuit 110 outputs the gate signal G 4 (see FIG. 6) at t = t 4, the analog switch 150 causes the resistance element 60 to The electrode pad 69 is connected to the positive terminal + Vcc of the DC power source, the analog switch 120 grounds the electrode pad 66 of the resistance element 60, and the analog switch 130 connects the electrode pad 67 of the resistance element 60 to the arithmetic circuit 161. To do.

  For this reason, the positive DC voltage V from the DC power source is applied to the series circuit including the resistance element portion 64, the crossover portion 65, and the resistance element portion 61 of the resistance element 60 as described above. In accordance with this, the crossing portion 65 of the resistance element 60 is connected to the input terminal of the arithmetic circuit 161 via the resistance element portion 62 and the electrode pad 67.

  In such a state, as described above, the resistance value of the resistance element portion 64 is R4 = R + ΔR4, and the resistance value of the resistance element portion 61 is R1≈R. = VM44 is expressed by the following equation (11).

VM = VM44 = R1 ・ V / (R4 + R1)
≒ (R) ・ V / (2R + ΔR4) ... (11)
Accordingly, the arithmetic circuit 161 receives and amplifies the midpoint potential VM44 from the crossing portion 65 of the resistance element 60 via the resistance element portion 62 and the electrode pad 67, and outputs the amplified voltage to the sample and hold circuit 171 as an amplified voltage. Accordingly, the amplified voltage is sampled and held by the sample and hold circuit 171 as a sample and hold voltage.

  When the sample-and-hold is completed as described above, the averaging circuit 180 averages the sample-and-hold voltages from both the sample-and-hold circuits 170 and 172 to generate an averaged voltage (hereinafter referred to as an averaged voltage VA11). Here, the averaged voltage VA11 of the averaging circuit 180 is expressed by the following formula (12) based on both formulas (8) and (10).

VA11 = (VM11 + VM33) / 2
= [4R + 3 (ΔR2 + ΔR4)] ・ V / [8R + 4 (ΔR2 + ΔR4)] ・ ・ ・ ・ ・ ・ (12)
The averaging circuit 181 averages the sample and hold voltages from both the sample and hold circuits 171 and 173 to generate an averaged voltage (hereinafter referred to as an averaged voltage VA22). Here, the averaged voltage VA22 of the averaging circuit 181 is expressed by the following equation (13) based on both equations (9) and (11). Note that ΔR2 · ΔR4≈0.

VA22 = (VM2 + VM4) / 2
＝ [4R + (ΔR2 + ΔR4)] ・ V / [8R + 4 (ΔR2 + ΔR4)] ・ ・ ・ ・ ・ ・ (13)
Next, the difference calculation circuit 190 calculates the difference between the averaged voltages VA11 and VA22 from the two averaging circuits 180 and 181 to generate a difference voltage (hereinafter referred to as difference voltage VAA). Here, the difference voltage VAA of the difference calculation circuit 190 is expressed by the following equation (14) based on both equations (12) and (13).

VAA = VA11-VA22 = (ΔR2 + ΔR4) ・ V / [4R + 2 (ΔR2 + ΔR4)]
≒ (ΔR2 + ΔR4) ・ V / (4R) ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ (14)
Here, for example, assuming a pressure distribution isobaric diagram as shown in FIG. 15 and ΔR2 = 0.9R and ΔR4 = 1.1ΔR, VAA≈ (0.9ΔR + 1.1ΔR) · V / (4R) = ΔRV / (2R).

Therefore, even if there is a difference or variation between ΔR2 and ΔR4 as described above, the difference output becomes ΔRV / (2R), the variation is absorbed and averaged, and the influence of the uneven load is reduced. Obtained as an appropriate value.
(Second Embodiment)
FIGS. 16-21 has shown the principal part of 2nd Embodiment of the pressure detection apparatus which concerns on this invention. In the second embodiment, considering the heat resistance of the resistance element 60, unlike the first embodiment, the semiconductor substrate 50 is an SOI in which a resistance element 60 made of a p-type semiconductor is formed in the plane orientation (110). It is composed of a (silicon on insulator) substrate.

  Therefore, in the second embodiment, the pressure sensor is the same as the pressure sensor described in the first embodiment except that the semiconductor substrate 50 described in the first embodiment is an SOI substrate (see FIG. 1)).

  Hereinafter, a process of adopting the SOI substrate as the semiconductor substrate 50 and manufacturing the resistance element 60 and the protective film 70 on the SOI substrate will be described.

  As the SOI substrate, a bonded SOI wafer 200 having a configuration as shown in FIG. 16 is prepared. In the SOI wafer 200, an intermediate oxide film 202 and an active layer 203 are sequentially stacked on a support substrate 201.

  In the second embodiment, the support substrate 201 is made of an n-type semiconductor material having a thickness of 525 (μm) and a resistance value within a range of 10 (Ω · cm) to 20 (Ω · cm). The intermediate oxide film 202 has a thickness of 1 (μm). The active layer 203 is made of a p-type semiconductor having a thickness of 1.5 (μm) and a resistance value within a range of 10 (Ω · cm) to 20 (Ω · cm).

In order to form the resistance element 60, boron (see reference numeral 204 in FIG. 17) is implanted into the active layer 203 of the SOI wafer 200 with an ion implantation apparatus. Here, the concentration of boron is set to 20 (atoms / cm ³ ) as described above.

Next, in order to obtain a uniform concentration of boron implanted as described above in the active layer 203, annealing is performed for 5 (hours) in an N ₂ atmosphere at 1100 (° C.).

  Thereafter, a patterning process is performed on the silicon in the active layer 203 to form a cross-shaped piezoresistor by etching to form a resistance element 60 (see reference numeral 204 in FIG. 18). The silicon etching is performed by reactive ion etching in a semiconductor process.

  Next, an HTO film 205 is formed as a protective film 70 with a film thickness of 300 (nm) (FIG. 19). At this time, the HTO film 205 is also formed on the back surface side of the support substrate 201, but the protective film 70 is configured by the HTO film 205 formed on the front surface side of the support substrate 201.

  Thereafter, the corresponding portions of the protective film 70 corresponding to the electrode pads 66 to 69 are etched to form the contact holes 206 (see FIG. 20).

  Next, after forming a metal film on the protective film 70, the metal film is subjected to a patterning process to form the electrode pads 66 to 69 (see FIG. 21). And after bonding both the glass plates 40 and 80 to the back surface of the SOI wafer 200 and the surface of the protective film 70 by anodic bonding, the glass plate 40 is fixed to the pedestal 30 with an adhesive. Other configurations are the same as those in the first embodiment.

  According to the pressure sensor having the configuration manufactured as described above, since the semiconductor substrate 50 is made of an SOI substrate, the above-described pressure sensor is further improved in heat resistance as compared with the pressure sensor described in the first embodiment. By using the control circuit 100 described in the first embodiment, the same effects as those of the first embodiment can be achieved.

In carrying out the present invention, the following various modifications are possible without being limited to the above embodiments.
(1) As described in the first or second embodiment, the resistance element 60 is not limited to the cross-shaped resistance element including the two pairs of resistance element portions 61, 63, 62, and 64. The resistance element portion may be a resistance element formed in a radial shape.

  However, also in this radiation-shaped resistance element, both resistance element parts corresponding to the both resistance element parts 62 and 64 described in the first or second embodiment are the same as those in the first or second embodiment. It is desirable that the semiconductor substrate 50 be formed along the crystal axis direction <110> in the plane orientation (110). Thereby, substantially the same operation effect as the first or second embodiment can be achieved.

For example, a radial-shaped resistance element composed of three pairs of resistance element portions is formed with a pair of resistance element portions of the three pairs of resistance element portions along the crystal axis direction <110> as shown in FIG. The other pair of resistor elements are formed along the crystal axis direction <100>, and the remaining pair of resistor elements are formed at a predetermined angle α (for example, 45 °) with respect to the crystal axis direction <100>. It is desirable to form.
(2) The semiconductor substrate 50 may be a p-type silicon substrate instead of the n-type silicon substrate. However, the resistance element 60 described in the above embodiment is formed in a cross shape along the crystal axis direction <100> and the crystal axis direction <110> in the plane orientation (110) of the p-type silicon substrate.

  The semiconductor substrate 50 is an SOI substrate in which a resistor element made of an n-type semiconductor is formed in the plane orientation (110) instead of the SOI substrate in which the resistor element 60 made of a p-type semiconductor is formed in the plane orientation (110). May be. However, the resistance elements are formed in a cross shape along the crystal axis direction <100> and the crystal axis direction <110>.

According to this, as shown in FIG. 23, the resistance element 60 made of an n-type semiconductor has a large change in piezoresistance coefficient in the crystal axis direction <100> in the plane orientation (110). Therefore, by using such a resistance value change, substantially the same effect as the first or second can be achieved.
(4) The impurity component is not limited to boron, and may be, for example, gallium or indium.
(5) The resistance element 60 is not limited to being formed in the plane orientation (110), but may be formed in a plane orientation equivalent to the plane orientation (110). Here, the plane orientation equivalent to the plane orientation (100) is, for example, (−110), (1-10), (−1-10), (101), (−101), (10-1), Examples include (-10-1), (011), (0-11), (01-1), or (0-1-1) plane orientation. Note that “−1” in the plane orientation means a bar with “−” on “1”.
(6) The resistance element 60 is not limited to the direction along the crystal axis direction <100> and the crystal axis direction <110> in the plane orientation (110) of the semiconductor substrate 50, and the crystal axis direction <100> and the crystal axis direction < Even if it is formed in a cross shape in the direction equivalent to 110>, the same effect as the first or second embodiment can be achieved.

  Here, the direction equivalent to the crystal axis direction <100> includes, for example, <-100>, <010>, <0-10>, <001>, or <00-1>. The directions equivalent to the crystal axis direction <110> are, for example, <−110>, <1-10>, <-1-10>, <101>, <−101>, <10-1>, <10-1> -10-1>, <011>, <0-11>, <01-1>, or <0-1-1>. Note that “−1” in the crystal axis direction means a bar with “−” on “1”.

It is a fragmentary sectional view which shows the pressure sensor in 1st Embodiment of the pressure detection apparatus which concerns on this invention. It is a partially broken enlarged plan view showing a semiconductor substrate, a resistance element, and a protective film in the first embodiment. In the said 1st Embodiment, when a pressure is applied to the resistance element which consists of a p-type semiconductor formed in the surface orientation (110), it is a graph which shows the dependence of the piezoresistance coefficient which arises in a resistance element in the crystal axis direction. It is a block diagram which shows the control circuit of FIG. FIG. 5 is a circuit configuration diagram showing a gate signal generation circuit of FIG. 4. It is a timing chart which shows the output waveform of the main component of FIG. It is sectional drawing of a silicon wafer. It is sectional drawing which shows the process of forming an oxide film in both surfaces of the silicon wafer of FIG. 7, and forming a cross-shaped part in the surface side oxide film of the said silicon wafer. FIG. 9 is a cross-sectional view showing a step of forming a resistance element by injecting boron into the cross-shaped portion of FIG. 8. FIG. 10 is a cross-sectional view showing a process of forming an HTO film as a protective film on the surface of a silicon wafer through the resistance element and the oxide film of FIG. 9. FIG. 11 is a cross-sectional view showing a process of forming each electrode pad contact hole in the protective film of FIG. 10. FIG. 12 is a cross-sectional view showing a process of forming an electrode pad in each contact hole of FIG. 11. FIG. 3 is a side view showing a state in which pressure is applied when the rod is positioned in a vertical state or an inclined state with respect to the surface of the resistance element in the first embodiment. FIG. 14 is a plan view of a semiconductor substrate and a resistance element showing a uniform load region when pressure is applied to the resistance element in a direction indicated by a solid line in FIG. 13. FIG. 14 is a plan view of a semiconductor substrate and a resistance element showing an uneven load region when pressure is applied to the resistance element in a direction indicated by a two-dot chain line in FIG. 13. It is sectional drawing which shows SOI of 2nd Embodiment of this invention. FIG. 17 is a cross-sectional view showing a step of implanting boron into the active layer of the SOI wafer of FIG. 16. It is sectional drawing which shows the process of forming the cross-shaped piezoresistive material which is a resistance element in the active layer of FIG. It is sectional drawing which shows the process of forming a protective film on the intermediate oxide film of a SOI wafer via the resistance element of FIG. FIG. 20 is a cross-sectional view showing a step of forming an electrode pad contact hole in the protective film of FIG. 19. FIG. 21 is a cross-sectional view showing a process of forming each electrode pad in each contact hole of FIG. 20. It is explanatory drawing at the time of forming a resistive element radially with three pairs of resistive element parts in the said 1st or 2nd embodiment. In the first or second embodiment, when pressure is applied to a resistance element made of an n-type semiconductor formed in the plane orientation (110), the dependence of the piezoresistance coefficient generated in the resistance element on the crystal axis direction is increased. It is a graph to show.

Explanation of symbols

50 ... Semiconductor substrate, 60 ... Resistance element, 61-64 ... Resistance element part,
65 ... intersection part (middle point part), 90 ... rod, 100 ... control circuit,
110: Gate signal generation circuit, 120-150: Analog switch,
160-163 ... arithmetic circuit, 170-173 ... sample hold circuit,
180, 181... Averaging circuit, 190... Differential operation circuit, + Vcc.

Claims (3)

A pressure sensor including a semiconductor substrate and a pressure detection element having a piezoresistive element formed in a pressure receiving portion that receives pressure in the semiconductor substrate;
A pressure detection device comprising a pressing member that applies a load to the pressure receiving portion,
In the piezoresistive element, the absolute value of the piezoresistive coefficient is larger than the half value between the minimum value and the maximum value on the midpoint portion and the plane orientation (110) or the plane orientation equivalent to this plane orientation. Having an even number of resistance element portions extending radially from the midpoint portion so as to include the crystal axis direction as one radial direction;
The pressure detecting device, wherein the resistance element portion is formed to intersect at the midpoint portion. Voltage application means for sequentially applying a voltage to each of the adjacent resistance element portions adjacent to each other among the even number of resistance element portions of the pressure detection element;
The pressure detection apparatus according to claim 1 , further comprising a control unit having an averaging unit that averages each midpoint portion generated at the midpoint portion for each voltage application by the voltage applying unit. A pressure sensor including a semiconductor substrate and a pressure detection element having a piezoresistive element formed in a pressure receiving portion that receives pressure in the semiconductor substrate;
A pressing member for applying a load to the pressure receiving portion;
A pressure detecting device comprising a control means ,
The piezoresistive element has a crystal orientation in which the absolute value of the piezoresistance coefficient is larger than the half value between the minimum value and the maximum value in the plane orientation (110) or a plane orientation equivalent to this plane orientation, and It is formed in a cross shape along both the crystal axis direction perpendicular to the crystal axis direction ,
The semiconductor substrate is an n-type silicon substrate or an SOI substrate,
The piezoresistive element is formed of a p-type semiconductor material,
The crystal axis direction having a piezoresistance coefficient larger than the half value of the absolute value of the absolute value of the piezoresistance coefficient and the crystal axis direction perpendicular to the crystal axis direction are the crystal axis direction <110> or A crystal axis direction equivalent to this crystal axis direction and a crystal axis direction <100> or a crystal axis direction equivalent to this crystal axis direction,
Furthermore, the piezoresistive element of the pressure detecting element has a midpoint portion and four resistance element portions extending in a cross shape from the midpoint portion,
The control means includes
Voltage applying means for applying a voltage to each of the two adjacent resistance element portions adjacent to each other among the four resistance element portions of the pressure detection element;
A pressure detecting device comprising: averaging means for averaging each midpoint voltage generated at the midpoint portion for each voltage application by the voltage applying means .