JP5065084B2 - Voltage detector - Google Patents

Description

  The present invention relates to a voltage detection device, and more particularly to a voltage detection device that performs voltage detection for each block obtained by dividing an assembled battery in which a plurality of unit cells each including a secondary battery are connected in series.

  In recent years, hybrid vehicles (hereinafter referred to as HEVs) that travel using both an engine and an electric motor have become widespread. The HEV includes two types of batteries, a low voltage battery of about 12V for starting the engine and a high voltage battery for driving the electric motor. The high voltage battery described above obtains a high voltage by connecting a plurality of unit cells in series with a secondary battery such as a nickel-hydrogen battery or a lithium battery as a unit cell.

  In the above-described high voltage battery, the voltage across the unit cell, that is, the state of charge (SOC) varies as charging and discharging are repeated. When charging or discharging the battery, from the viewpoint of ensuring the durability and safety of each unit cell, charging is prohibited when the unit cell with the highest SOC (or both-ends voltage) reaches the set upper limit SOC (or upper-end both-ends voltage value). However, it is necessary to inhibit discharge when the unit cell having the lowest SOC (or both-ends voltage) reaches the set lower limit SOC (or lower-end both-ends voltage value). Therefore, when SOC variation occurs in each unit cell, the usable capacity of the battery is substantially reduced. For this reason, in HEV, so-called assist / regeneration, which replenishes battery energy to gasoline when climbing, or regenerates energy to the battery when descending, becomes insufficient, reducing actual vehicle power performance and fuel consumption. become. Therefore, in order to equalize the SOC of each unit cell, it is necessary to detect the voltage across each unit cell.

Therefore, the high-voltage battery is divided into a plurality of blocks, and an A / D converter (analog / digital conversion means) that converts the voltage between both ends of the unit cell into analog / digital (A / D) is provided for each block. And the voltage detection apparatus which transmits the digital value of the both-ends voltage of the unit cell converted by this A / D converter to the main microcomputer (control means) which manages the whole high voltage battery is proposed. In the conventional voltage detection device described above, the voltage across the unit cell cannot be accurately detected unless the reference voltage of the A / D converter for each block is the same. For this reason, conventionally, the reference voltage of the A / D converter for each block is set to the same value using a highly accurate reference voltage source. However, in this case, it is necessary to use an expensive high-precision reference voltage source for each block, which causes a problem in cost. As another conventional example, for example, one described in Patent Document 1 has been proposed.
JP 2006-211885 A

  Accordingly, the present invention focuses on the above-described problems, and an object thereof is to provide a voltage detection device that can detect the voltage across the unit cell of each block with high accuracy and low cost.

  In order to solve the above-mentioned problem, the invention according to claim 1 is provided corresponding to each block obtained by dividing an assembled battery in which a plurality of unit cells each formed of a secondary battery are connected into a plurality of blocks, and the corresponding block is provided. An analog / digital conversion means for analog / digital conversion of a voltage between both ends of each constituting unit cell, and a control means for receiving a digital value of the voltage across each unit cell converted by the analog / digital conversion means are provided. In the voltage detection device, an input for inputting the divided voltage of the reference voltage of the analog / digital conversion means provided corresponding to the non-reference block to the analog / digital conversion means provided corresponding to the reference block. And a base of the non-reference block converted by the analog / digital conversion means provided in the reference block. Based on the voltage division, converted by the analog / digital conversion means provided corresponding to the non-reference block due to the difference between the reference voltage of the reference block and the reference voltage of the non-reference block The voltage detecting apparatus further comprises correction means for correcting the error generated in the digital value of the voltage across the unit cell so as to be erased.

  The invention according to claim 2 is provided corresponding to each block obtained by dividing a battery pack in which a plurality of unit cells each comprising a secondary battery are connected, and the voltage across each unit cell constituting the corresponding block is determined. In a voltage detection apparatus provided with: an analog / digital conversion means for analog / digital conversion; and a control means for receiving a digital value of a voltage across each unit cell converted by the analog / digital conversion means. A first divided voltage of the reference voltage of the analog / digital conversion means provided corresponding to the non-reference block is input to the analog / digital conversion means provided corresponding to the second non-reference block. A reference voltage obtained by dividing a reference voltage of the analog / digital conversion means provided corresponding to the input means and the second non-reference block; Second input means for inputting to the analog / digital conversion means provided correspondingly, and the second input means converted by the analog / digital conversion means provided corresponding to the second non-reference block. Based on the divided voltage of the reference voltage of one non-reference block and the divided voltage of the second non-reference block converted by the analog / digital conversion means provided corresponding to the reference block. On the basis of a digital value obtained by converting the divided voltage of the reference voltage of one non-reference block by the analog / digital conversion means provided corresponding to the reference block, and a digital value obtained by the calculation means, The analog / not provided corresponding to the first non-reference block due to the difference between the reference voltage of the reference block and the first non-reference block And correcting means for correcting to erase an error occurring in the digital value of the voltage across the converted unit cells by digital converting means lies in the voltage detection apparatus characterized by comprising a.

  According to a third aspect of the present invention, in the voltage according to the first or second aspect, the input means is provided so as to supply the divided voltage to the analog / digital conversion means via a capacitor. It exists in the detection device.

  As described above, according to the first aspect of the invention, the analog / digital conversion means provided corresponding to the non-reference block due to the difference between the reference voltage of the reference block and the reference voltage of the non-reference block. Since the error generated in the digital value of the voltage across the converted unit cell can be eliminated, it is not necessary to use an expensive high-precision reference voltage source for all blocks if only a reference block is used. The voltage across the unit cell of each block can be detected at low cost.

  According to the second aspect of the present invention, the analog / digital conversion means provided corresponding to the first non-reference block due to the difference between the reference voltage of the reference block and the reference voltage of the first non-reference block. This eliminates the error that occurs in the digital value of the voltage across the unit cell converted by, so if a high-precision reference voltage source is used only for the reference block, there is no need to use an expensive high-precision reference voltage source for all blocks, and high accuracy In addition, the voltage across the unit cell of each block can be detected at a low cost.

  According to the third aspect of the present invention, the partial pressure can be accurately level-shifted by the capacitor.

First Embodiment Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the voltage detection apparatus of the present invention. Reference sign _{BL in the} figure is a low voltage battery. As shown in FIG. 1, the low-voltage battery _BL is composed of, for example, one secondary battery. The low-voltage battery _BL is used as an operating power source for a starter that starts the engine, and an alternator or the like is connected to both ends as a charger as necessary.

In the figure, reference sign B _H is a high voltage battery as an assembled battery. The high-voltage battery B _H is used as a power source for the electric motor in an HEV that uses both the engine and the electric motor as a travel drive source. Both ends of the high-voltage battery B _H are connected as a load as necessary, and an alternator is required. Is connected as a charger.

The high voltage battery B _H is divided into _n blocks (n is an arbitrary integer) blocks B _{1 to} B _n . Each of the blocks B _{1 to} B _n is composed of, for example, two unit cells C _{11 to} C _n2 . The voltage detection device includes high voltage detection circuits 11 to 1n and a low voltage system control circuit 30 as control means. The low voltage system control circuit 30 operates by receiving power from the low voltage battery _BL and controls the high voltage detection circuits 11 to 1n.

The high voltage detection circuits 11 to 1n are provided corresponding to the blocks B _{1 to} B _n . High voltage measuring circuit 11~1n may operate by receiving the corresponding unit cells C ₁₁ constituting the block B ₁ .about.B _n to -C _n2 only the power supply from the plurality of blocks B ₁ .about.B _n, the corresponding block detecting the voltage across the unit cells C ₁₁ -C _n2 constituting the B ₁ ~B _n. That is, in the high voltage detection circuits 11 to 1n described above, the minus side of the corresponding blocks B _{1 to} B _n is at the ground level, and the ground levels are different from each other. As a result, the breakdown voltage of the devices constituting the high voltage detection circuits 11 to 1n can be lowered.

Next, the configuration of the above-described high voltage detection circuits 11 to 1n will be described with reference to FIG. As shown in the figure, the high voltage measuring circuit 11~1n each, a capacitor Cp that both ends of the unit cells C ₁₁ -C _n2 constituting the corresponding block B ₁ .about.B _n is connected, the corresponding blocks B ₁ ~ A selection switch group 24 that connects one end of each of the unit cells C _{11 to} C _n2 constituting B _n to the capacitor Cp, and digitally converts the voltage across the unit cells C _{11 to} C _n2 supplied via the capacitor Cp. A / D converter 22 as analog / digital conversion means, switches S11 and S12 provided between capacitor Cp and A / D converter 22, and a reference voltage source for supplying a reference voltage to A / D converter 22 25 and a high-voltage CPU 25 that controls the entire high-voltage detection circuits 11 to 1n.

It said selection switch group 24 is composed of a switch provided at both ends of the unit cells C ₁₁ -C _n2. Further, A / D converter 22 described above, the reference voltage source 25 and, the high pressure system CPU25, the power supply line is connected to the positive side of the corresponding block B ₁ .about.B _n, block B ₁ to the ground line corresponding It is connected to the negative side of ~ _Bn . As the reference voltage source 25 of the block B ₁ as the reference block, for example, a high-precision one of about ± 0.01% is used. On the other hand, the blocks B _{2 to} B _n as non-reference blocks are, for example, those with lower accuracy than the block B ₁ of about ± 0.5%.

As shown in FIGS. 1 and 2, the high voltage CPU 25 of the high voltage detection circuit 11 is connected to the low voltage control circuit 30 via a transmission line L _T1 and a reception line L _R1 . On the transmission line L _T1 , a transmission insulating device D _T such as a photocoupler using light as a medium or a magnetic coupler using magnetism as a medium is provided. A detection command or the like can be transmitted from the low voltage system control circuit 30 to the high voltage detection circuit 11 in a state where the high voltage detection circuit 11 and the low voltage system control circuit 30 are insulated by the transmission insulating device _DT . Further, the receiving isolation device D _R such as a photo coupler or a magnetic coupler is provided in the receiving line L _R1. And a high voltage measuring circuit 11 and the low voltage system control circuit 30 in a state of being insulated by the receiving isolation device D _R, can be low voltage system control circuit 30 receives and detection results of the voltage across the high-voltage detection circuit 11. The high-voltage CPUs 25 of the high-voltage detection circuits 11 to 1n are serially connected to each other via a transmission line L _T2 and a reception line L _R2 .

As shown in FIG. 2, the high voltage detection circuits 12 to 1n excluding the high voltage detection circuit 11 have reference voltages V _{ref2 to} V _refn of the A / D converter 22 provided corresponding to the blocks B _{2 to} B _n . An input circuit 27 is provided as first input means for inputting the partial pressure to the A / D converter 22 provided corresponding to the block B ₁ .

Each of the input circuits 27 is _{divided by the} voltage _dividing resistors R1 and R2 provided between the reference voltages V _{ref2 to} V _refn and the ground of each block B _{2 to} B _n , and the voltage _dividing resistors R1 and R2. The operational amplifier 28 that amplifies the reference voltages V _{ref2 to} V _refn , the output of the operational amplifier 28, the switch S 21 provided between one end of the capacitor Cp of the block B ₁ , and the corresponding blocks B _{2 to} B _n The switch S22 is provided between the ground and the other end of the capacitor Cp.

Next, the reference voltage detection operation of the voltage detection device having the above-described configuration will be described below with reference to FIGS. FIG. 3 is a flowchart showing the reference voltage detection processing procedure of the low-voltage system control circuit 30 shown in FIG. FIG. 4 is a flowchart showing the reference voltage detection processing procedure of the high-voltage CPU 25. At a predetermined timing, the low voltage system control circuit 30 starts the reference voltage detection process. In the reference voltage detection process, the low voltage system control circuit 30 first outputs a wake-up signal (step Sp1). The awakening signal is supplied to a power circuit (not shown) provided in each of the blocks B _{1 to} B _n via an insulating device (not shown). When the power supply circuit of each of the blocks B _{1 to} B _n receives the awakening signal, it supplies power to the high voltage detection circuits 11 to 1n. Then, the high-voltage CPU 25 of the high-voltage detection circuits 11 to 1n is released from the sleep mode in response to the power supply, and starts the high-voltage reference voltage detection process shown in FIGS.

Next, the low-voltage system control circuit 30 sets m (integer), which is an arbitrary integer, to 2 (step Sp2), and then transmits a reference voltage detection command to the block B _m to the transmission line L _T1 ( Step Sp3). In response to this, a digital value of a _divided value of the reference voltage V _refm of the block B _m is transmitted from the high voltage system CPU 25 of the block B ₁ to the low voltage system control circuit 30. When the low-voltage system control circuit 30 receives the digital value of the _divided value of the reference voltage V _refm and stores it in a storage medium (not shown) (step Sp4), it determines whether m has reached the highest address n. (Step Sp5).

If m has reached the highest address n (Y in Step Sp5), the low voltage system control circuit 30 determines that the digital values of all the _divided values of the reference voltages V _{ref2 to} V _{refn have} been received from the high voltage side. Then, after outputting the sleep signal (step Sp7), the low-voltage system reference voltage detection process is terminated. The sleep command is supplied to a power circuit (not shown) provided in each of the blocks B _{1 to} B _n via an insulating device (not shown). When the power supply circuit of each of the blocks B _{1 to} B _n receives the sleep command, it shuts off the power to the high voltage detection circuits 11 to 1n. On the other hand, if m has not reached the highest address n (N in step Sp5), the low-voltage system control circuit 30 increments m (step Sp6) and then returns to step Sp3. Thereby, the reference voltage detection commands addressed to the blocks B _{2 to} B _n are sequentially transmitted from the low voltage system control circuit 30 to the high voltage side.

On the other hand, as shown in FIG. 4, when the high voltage system CPU 25 of the high voltage detection circuit 1p of an arbitrary block B _p (p is an integer from 1 to n) receives the reference voltage detection command (Y in step Sp11), It is determined whether or not the destination of the reference voltage detection command is its own address p (step Sp12). If its own address p (= m) (Y in step S12), the high voltage system CPU25 of the high voltage detection circuit 1p block B _p turns on the switches S21 and S22 (step SP13).

According to the on of the switch S21 and S22, the partial pressure of the reference voltage V _refp across the block B _p of the capacitor Cp of the block B ₁ is supplied. High voltage measuring circuit 1p block B _p waits for the capacitor Cp is charged voltage across the capacitor Cp to the lapse of a predetermined time, such as to reach the same voltage as the reference voltage V _refp block B _p (Y at step Sp14 ), The switches S21 and S22 are turned off (step Sp15). After that, the high voltage detection circuit 1p of the block B _p sends a charge completion signal with the address 1 of the block B ₁ and the transmission source as its own address p to the high voltage system CPU 25 of the lower block B _p-1 . After the transmission (step Sp16), the process returns to step Sp11.

On the other hand, if the high-voltage CPU 25 of the high-voltage detection circuit 1p does not have its own address p (≠ m) (N in step Sp12), the reference voltage detection command received in step Sp11 is one block B _p higher. _The data is transferred to the ₊₁ high-voltage CPU 25 (step Sp17). When the high voltage CPU 25 of the high voltage detection circuit 1p of any block B _p receives the charge completion signal (Y in step Sp18), it determines whether the destination of the charge completion signal is its own address p ( Step Sp19). If it is not its own address p (≠ 1) (N in Step Sp19), the charge completion signal is transferred to the next lower block B _p-1 (Step Sp20), and the process returns to Sp11.

On the other hand, if the high-voltage CPU 25 of the high-voltage detection circuit 1p has its own address p (= 1) (Y in step Sp19), the switches S11 and S12 are turned on (step Sp21), and the reference stored in the capacitor Cp. The _divided voltage value of the voltage V _refm is input to the A / D converter 22 and converted into a digital value. Then, the high-voltage CPU 25 of the block B _p takes in the digital value (step Sp22), and turns off the switches S11 and S12 (step Sp23). Then, the high voltage system CPU25 block B _p sends to the low voltage system control circuit 30 and attach the source address of the charge completion signal to a digital value fetched in step SP22 (step SP24), the flow returns to step Sp11.

By the low voltage system reference voltage detection process and the high voltage system reference voltage detection process described above, the low voltage system control circuit 30 has the blocks B _{2 to} B converted by the A / D converter 22 provided corresponding to the block B _1. Digital values of the _divided voltages of the reference voltages V _{ref2 to} V _refn of the A / D converter 22 provided corresponding to _n are sequentially stored.

  Next, the cell voltage detection operation of the voltage detection device having the above-described configuration will be described below with reference to FIGS. FIG. 5 is a flowchart showing a cell voltage detection processing procedure of the low-voltage system control circuit shown in FIG. FIG. 6 is a flowchart showing the cell voltage detection processing procedure of the high-voltage CPU 25. In response to the ignition ON, the low voltage system control circuit 30 starts the low voltage system cell voltage detection process shown in FIG. In the cell voltage detection process, the low voltage system control circuit 30 first outputs an awakening signal (step Sp31). In response to the output of the awakening signal, power is supplied to the high voltage detection circuits 11 to 1n as described above. Thereby, the high voltage system CPU 25 of the high voltage detection circuits 11 to 1n is released from the sleep mode and starts the high voltage system cell voltage detection process shown in FIG.

Next, after setting m (integer), which is an arbitrary integer, to 1 (step Sp32), the low-voltage system control circuit 30 transmits a cell voltage detection command to the block B _m to the transmission line L _T1 ( Step Sp33). In response to this, the digital values AD _Cm1 and AD _{Cm2 of the} voltage across the unit cells C _m1 and C _m2 constituting the block B _m are transmitted from the high voltage side to the low voltage system control circuit 30. Low voltage system control circuit 30, after receiving the digital value AD _Cm1, AD _Cm2 (step SP34), sends digital values AD _Cm1, AD _Cm2 is the voltage across the unit cell C _11, C ₁₂ of the block B ₁ It is determined whether or not the digital values are AD _C11 and AD _C12 (step Sp35). If the digital values are AD _C11 and AD _C12 (Y in step Sp35), the low-voltage system control circuit 30 stores the AD _C11 and AD _C12 received in step Sp34 as they are (step Sp36), and then proceeds to step Sp38.

In contrast, the digital value AD _C11, AD _C12 else (N in step Sp35), low voltage system control circuit 30 serves as a correction means corrects the digital value AD _Cm1, AD _Cm2 received in step Sp34 After storing (step Sp37), the process proceeds to step Sp38. In step Sp37, the low-voltage system control circuit 30 is based on the _divided voltage of the reference voltage V _refm of the block B _m converted by the A / D converter 22 provided in the block B ₁ stored in the reference voltage detection process described above. Te, block B ₁ of the reference voltage V _ref1 and the block B _m of the reference voltage V _refm unit cells are converted by the a / D converter 22 provided corresponding to the block B _m due to the difference between the C _m1 , C _m2 is corrected so as to eliminate errors occurring in the digital values AD _Cm1 and AD _Cm2 of the voltages V _Cm1 and V _Cm2 .

More specifically, _when the A / D converter 22 converts the voltages V _Cm1 and V _Cm2 (analog values) using the A / D converter 22 of the reference voltage V _refm of the block B _m , the digital of the voltages V _Cm1 and V _Cm2 is obtained. The values AD _Cm1 and AD _Cm2 are represented by the following formula (1). 2 ^q indicates the resolution of the A / D converter 22.
AD _Cm1 = V _Cm1 × 2 ^q / V _{refm
^{AD Cm2 = V Cm2 × 2 q}} / V refm ... (1)
In contrast, when the voltage across V _Cm1, V _Cm2 by the A / D converter 22 of the reference voltage V _ref1 of the block B ₁ A / D converts the digital value AD _Cm1 across voltage V _Cm1, V _Cm2 ', AD _Cm2 ′ is expressed by the following equation (2).
AD _Cm1 '= V _Cm1 × 2 ^q / V _ref1
AD _Cm2 '= V _Cm2 × 2 ^q / V _ref1 (2)
Therefore, by correcting the digital value AD _Cm1, AD _Cm2 received in step Sp34, as shown in the following equation (3), the reference voltage V _refm the A / D converter 22 with the converted digital values AD _Cm1, AD _Cm2 can be converted into digital values AD _Cm1 ′ and AD _Cm2 ′ converted by the A / D converter 22 of the reference voltage V _ref1 .
AD _Cm1 '= AD _Cm1 × V _refm / V _ref1
AD _Cm1 '= AD _Cm1 × V _refm / V _ref1 (3)

The reference voltage V _refm described above can be obtained from the digital value AD _Vrefm of the _divided value of the reference voltage V _refm stored by the reference voltage detection process described above. That is, since the digital value AD _Vrefm of the _divided value of the reference voltage V _refm detected by the above-described reference voltage detection process is converted by the A / D converter 22 of the reference voltage V _ref1 , it is expressed by Expression (4). be able to. Note that the voltage dividing ratio by the resistors R1 and R2 is K.
AD _Vrefm = V _refm × (1 / K) × 2 ^q / V _ref1 (4)
When this is modified, the following equation (5) is obtained.
V _refm = (V _ref1 / 2 ^q ) × K × AD _Vrefm (5)
Therefore, by substituting equation (5) into equation (3), a correction equation shown in equation (6) below can be obtained.
AD _Cm1 '= AD _Cm1 × AD _Vrefm × K × (1/2 ^q )
_{AD Cm2 '= AD Cm2 × AD} Vrefm × K × (1/2 q) ... (6)

Therefore, high voltage system CPU25 at step Sp37 in FIG. 5, multiplies the digital value AD _Vrefm and K received in step Sp4 of 3 to the digital value AD _Cm1, AD _Cm2 received in step SP34 (1/2 ^q) New digital values AD _Cm1 and AD _Cm2 are obtained by correcting the obtained values. By using the correction equation shown in the above Expression (6), the reference voltage V _refm the A / D converter 22 unit cells C _m1 converted by, C voltage across V _Cm1 of _m2, the digital value of V _Cm2 AD _Cm1 , AD _Cm2 is converted into digital values AD _Cm1 and AD _Cm2 of the voltages V _Cm1 and V _Cm2 across the unit cells C _m1 and C _m2 converted by the A / D converter 22 of the reference voltage V _ref1. the _first reference voltage V _ref1 and the unit cells are converted by the a / D converter 22 provided corresponding to the block B _m due to the difference between the reference voltage V _refm blocks B _m C _m1, C _m2 Errors occurring in the digital values AD _Cm1 and AD _Cm2 of the both-end voltages V _Cm1 and V _Cm2 can be eliminated. That is, even if A / D conversion is performed using the reference voltage source 25 of the blocks B _{2 to} B _{n with} low accuracy, the digital value AD _Cm1 is A / D converted using the reference voltage source 25 of the block B ₁ with high accuracy. , Can be converted to _ADCm2 . This eliminates the need to use a block B ₁ .about.B _n precision of the reference voltage source 25 for each, to detect the voltage across the unit cells C ₁₁ -C _n2 of high accuracy and low cost blocks B ₁ .about.B _n be able to.

In step Sp38, the low-voltage system control circuit 30 determines whether m has reached the highest address n. If m has reached the address n of the uppermost (Y in step SP38), the low-voltage control circuit 30, the digital value of the voltage across the unit cells C ₁₁ -C _n2 constituting all the blocks B ₁ .about.B _n Is received from the high voltage system CPU 25 of the block B ₁ and a sleep signal is output (step Sp39), the low voltage system cell voltage detection process is terminated. In response to the output of the sleep command, the power supply to the high voltage detection circuits 11 to 1n is cut off as described above. On the other hand, if m has not reached the highest address n (N in step Sp38), the low-voltage system control circuit 30 increments m (step Sp40) and then returns to step Sp33. As a result, the cell voltage detection commands addressed to the blocks B _{2 to} B _n are sequentially transmitted from the low voltage system control circuit 30 to the high voltage side.

On the other hand, as shown in FIG. 6, when the high voltage system CPU 25 of the high voltage detection circuit 1p of any block B _p receives the cell voltage detection command (Y in step Sp51), the destination of the cell voltage detection command is its own. It is determined whether or not the address is p (step Sp52). If its own address p (= m) (Y in step S52), the high voltage system CPU25 of the high voltage detection circuit 1p block B _p is the voltage across the unit cell C _p1, C _p2 constituting the block B _p A / D converter 22 is converted (step Sp53). More specifically, in step SP53, connecting both ends of the unit cells C _p1 in the capacitor Cp by controlling the selection switch group 24. Thus, when the voltage across the capacitor Cp becomes equal to the voltage across the unit cell C _p1 , the high voltage CPU 25 turns off the selection switch group 24 and separates the unit cells C _p1 and C _p2 from the capacitor Cp. Thereafter, when the switches S11 and S12 are turned on, the voltage across the capacitor Cp equal to the voltage across the unit cell C _p1 is input to the A / D converter 22 and A / D converted. Similarly, for the unit cell C _p2 , the high voltage system CPU 25 inputs the voltage across the capacitor Cp equal to that of the unit cell C _p2 to the A / D converter 22 and performs A / D conversion.

Thereafter, the high-voltage CPU25 After transmitting the digital value AD _cp1, AD _cp2 voltage across V _cp1, V _cp2 of the unit cell C _p1, C _p2 converted in step Sp53 next lower block B _p1 ( Step Sp54), the process returns to Step Sp51. In the case of high-voltage CPU25 blocks B1, in step SP54, and transmits the digital value AD _cp1, AD _cp2 the low voltage system control circuit 30. On the other hand, if the destination of the cell voltage detection command received in step Sp51 is not its own address p (≠ m) (N in step Sp52), the cell voltage detection command is transferred to the block B _{p + 1} one higher order. (Step Sp55). After that, when the digital values AD _cm1 and AD _cm2 are received from the upper block B _m (Y in Step Sp56), the high voltage CPU 25 transmits the digital values AD _cm1 and AD _cm2 to the one lower block B _p-1 . After (step Sp57), the process returns to step Sp51 again. According to the high voltage system cell voltage detection process described above, the digital values AD _{C11 to} AD _Cn2 of the both-end voltages V _{c11 to} V _cn2 of the unit cells C _{11 to} C _n2 of the blocks B _{1 to} B _n are sequentially transmitted to the low voltage side. The

According to the above voltage detecting device, provided corresponding to the block B ₂ .about.B _n due to the difference between the reference voltage V _ref2 ~V _refn reference voltage V _ref1 and the block B ₂ .about.B _n blocks B ₁ The error generated in the digital value of the voltage across the unit cells C _{21 to} C _n2 converted by the A / D converter 22 can be eliminated, so an expensive high-precision reference voltage source is used for each of the blocks B _{2 to} B _n. it is not necessary, high accuracy and low cost voltage across the unit cells C ₁₁ -C _n2 of the blocks B ₂ .about.B _n can be detected.

Further, according to the voltage detection device described above, the input circuit 27 is provided so as to supply the divided voltage values of the unit cells C _{21 to} C _n2 to the A / D converter 22 via the capacitor Cp. The voltage division can be accurately level shifted by the capacitor Cp.

Second Embodiment Next, a second embodiment will be described. In the first embodiment described above, the input circuit 27 corresponds to all the _divided voltages of the reference voltages V _{ref2 to} V _refn of the A / D converter 22 provided corresponding to the blocks B _{2 to} B _n to the block B ₁ . However, the present invention is not limited to this. For example, an input circuit 27 of any of the block B _m is, corresponds to the partial pressure of the reference voltage V _refm the A / D converter 22 provided corresponding to the block B _m in the block B _m-1 of the next lower It is also conceivable to input to the A / D converter 22 provided. Accordingly, the address (m−1) of the one lower block B _m−1 is attached to the destination of the charge completion signal transmitted at step Sp16 in FIG.

That is, as shown in FIG. 7, the input circuit 27 of the block B _3, corresponding to the partial pressure of the reference voltage V _ref3 of the A / D converter 22 provided corresponding to the block B ₃ to the block B ₂ It is provided so as to input to the provided A / D converter 22. The input circuit block B ₂ 27 is block B ₂ correspondingly provided with A / D converter 22 corresponding to provided the A / D converting the partial pressure of the reference voltage V _ref2 to the block B ₁ of the It is provided to input to the device 22. As is clear from the above, the block B ₃ is the first non-reference block, the block B ₂ is the second non-reference block, the input circuit 27 of the block B ₃ is the first input means, and the input of the block B ₂ The circuit 27 corresponds to second input means.

In the first embodiment described above, the low voltage system control circuit 30 stores the digital signal of the _{divided values} of the reference voltages V _{ref2 to} V _refn transmitted from the high voltage side as it is (step Sp4 in FIG. 3). In the second embodiment, the low-voltage system control circuit 30 functions as arithmetic means, and digital values AD _{Vref3 to} V _{refn of} the reference voltages V _{ref3 to} V _refn converted by the A / D converters 22 of the blocks B _{3 to} B _{n. Are} converted into digital values AD _{Vref3 to} V _refn converted by the A / D converter 22 of the block B ₁ .

Details of the conversion will be described. When the A / D converter 22 of the reference voltage V _{ref (m-1)} of the lower block B _m-1 is A / D converted to the reference voltage V _refm (analog value) of an arbitrary block B _m , the reference voltage The digital value AD _Vrefm of V _refm is expressed by the following equation (7). 2 ^q indicates the resolution of the A / D converter 22, and the voltage dividing ratio by the resistors R1 and R2 is K.
AD _Vrefm = V _refm × (1 / K) × 2 ^q / V _{ref (m-1)} (7)
On the other hand, when the reference voltage V _refm is A / D converted by the A / D converter 22 of the reference voltage V _ref1 of the block B ₁ , the digital value ADV _refm of the reference voltage V _refm is expressed by the following equation (8). The
AD _Vrefm = V _refm × (1 / K) × 2 ^q / V _ref1 (8)
Therefore, if the digital value AD _Vrefm received in step Sp4 is corrected as shown in the following equation (9), the digital value AD _Vrefm ′ converted by the A / D converter 22 of the reference voltage V _ref1 is converted. Can do.
AD _Vrefm ′ = AD _Vrefm × V _{ref (m−1)} / V _ref1 (9)

The above-mentioned reference voltage V _{ref (m-1)} is a digital value AD _{Vref (m-1)} to a reference voltage V _{ref (m-1) to a} divided voltage value of V _ref2 stored by the above-described reference voltage detection process. It can be obtained from AD _ref2 . That is, the digital values AD _{Vref (m−1) to} AD _ref2 of the divided voltages of the reference voltages V _{ref (m−1) to} V _ref2 detected by the above-described reference voltage detection process are the reference voltages V _{ref (m− 2) Since} each of them is converted by the A / D converter 22 of ~ _Vref1 , it can be expressed by Expression (10).
AD _{Vref (m-1)} = _{Vref (m-1)} x (1 / K) x ^2q / _{Vref (m-2)}
AD _{Vref (m-2)} = _{Vref (m-2)} x (1 / K) x ^2q / _{Vref (m-3)}
...
AD _Vref3 = V _ref3 × (1 / K) × 2 ^q / V _ref2
AD _Vref2 = V _ref2 × (1 / K) × 2 ^q / V _ref1 (10)
When this is modified, the following equation (11) is obtained.
_{Vref (m-1)} = ( _{Vref (m-2)} / ^2q ) * K * AD _{Vref (m-1)
V ref (m-2) =} (V ref (m-3) / 2 q) × K × AD Vrefm (m-2)
...
V _ref3 = (V _ref2 / 2 ^q ) × K × AD _Vref3
V _ref2 = (V _ref1 / 2 ^q ) × K × AD _Vref2 (11)
Therefore, if the equation (11) is substituted into the equation (9), a correction equation shown in the following equation (12) can be obtained.
AD _Vrefm '= (V _ref1 / 2 ^{(m-1) q} ) x K ^(m-1) x AD _Vrefm x ... x AD _Vref2
(12)

Therefore, in step Sp4 of FIG. 3, the high voltage CPU 25 _adds (V _ref1 / 2 ^{(m-1) q} ), K ^(m-1), and AD _{Vref (m-1)} to the digital value AD _Vrefm received from the high voltage system. X ... x AD _Vref1 is a new digital value AD _{Vrefm obtained} by correcting the value multiplied by x AD _Vref1 . By using the correction equation shown in the above equation (12), the digital values AD _{Vref3 to} V _refn of the reference voltages V _{ref3 to} V _refn converted by the A / D converters 22 of the blocks B _{3 to} B _n are converted into the block B. _The digital values AD _{Vref3 to} V _refn converted by _one A / D converter 22 can be converted.

That is, the _divided voltage of the reference voltage V _ref3 of the block B ₃ converted by the A / D converter 22 provided corresponding to the block B ₂ and the A / D conversion provided corresponding to the block B _1. Based on the _divided voltage of the reference voltage V _ref2 of the block B ₂ converted by the converter 22, the _divided voltage of the reference voltage V _ref3 of the block B ₃ is converted by the A / D converter 25 provided corresponding to the block B _1. The obtained digital value ADV _ref3 can be obtained. Since the subsequent steps are the same as those in the first embodiment described above, detailed description thereof is omitted here.
In the first and second embodiments described above, the input circuit 27 is provided to supply the divided voltage to the A / D converter 22 via the capacitor Cp. However, the present invention is limited to this. It is not a thing. For example, a partial voltage may be provided to the A / D converter 22 using another level shift circuit.

  Further, the above-described embodiments are merely representative forms of the present invention, and the present invention is not limited to the embodiments. That is, various modifications can be made without departing from the scope of the present invention.

It is a block diagram which shows one Embodiment of the voltage detection apparatus of this invention. It is a circuit diagram which shows the detail of the high voltage | pressure detection circuit shown in FIG. 1 in 1st Embodiment. It is a flowchart which shows the reference voltage detection processing procedure of the low voltage | pressure system control circuit shown in FIG. It is a flowchart which shows the reference voltage detection processing procedure of the high voltage | pressure system CPU shown in FIG. It is a flowchart which shows the cell voltage detection processing procedure of the low voltage | pressure system control circuit shown in FIG. It is a flowchart which shows the cell voltage detection processing procedure of the high voltage | pressure system CPU shown in FIG. It is a circuit diagram which shows the detail of the high voltage | pressure detection circuit shown in FIG. 1 in 2nd Embodiment.

Explanation of symbols

22 A / D converter (analog / digital conversion means)
27 Input circuit (input means)
30 Low pressure system control circuit (control means, correction means, calculation means)
B _H high-voltage battery (assembled battery)
B ₁ block (reference block)
B ₂ .about.B _n blocks (non-reference block)
C _{11 to} C _n2 unit cell Cp capacitor V _{ref1 to} V _refn reference voltage

Claims (3)

Analog / digital that is provided corresponding to each block obtained by dividing an assembled battery in which a plurality of unit cells composed of secondary batteries are connected into a plurality of blocks, and that converts both-end voltages of each unit cell constituting the corresponding block from analog to digital In the voltage detection apparatus provided with the conversion means and the control means for receiving the digital value of the voltage across each unit cell converted by the analog / digital conversion means,
Input means for inputting the divided voltage of the reference voltage of the analog / digital conversion means provided corresponding to the non-reference block to the analog / digital conversion means provided corresponding to the reference block;
Due to the difference between the reference voltage of the non-reference block and the reference voltage of the non-reference block, based on the divided voltage of the reference voltage of the non-reference block converted by the analog / digital conversion means provided in the reference block Correction means for correcting so as to eliminate an error occurring in the digital value of the voltage across the unit cell converted by the analog / digital conversion means provided corresponding to the non-reference block;
A voltage detection apparatus comprising: Analog / digital that is provided corresponding to each block obtained by dividing an assembled battery in which a plurality of unit cells composed of secondary batteries are connected into a plurality of blocks, and that converts both-end voltages of each unit cell constituting the corresponding block from analog to digital In the voltage detection apparatus provided with the conversion means and the control means for receiving the digital value of the voltage across each unit cell converted by the analog / digital conversion means,
The divided voltage of the reference voltage of the analog / digital conversion means provided corresponding to the first non-reference block is input to the analog / digital conversion means provided corresponding to the second non-reference block. First input means;
A second voltage is inputted to the analog / digital conversion means provided corresponding to the reference block by dividing the reference voltage of the analog / digital conversion means provided corresponding to the second non-reference block. Input means,
Divided by the reference voltage of the first non-reference block converted by the analog / digital conversion means provided corresponding to the second non-reference block, and provided corresponding to the reference block The analog / digital that is provided with the reference voltage of the first non-reference block corresponding to the reference block based on the divided voltage of the second non-reference block converted by the analog / digital conversion means. Arithmetic means for obtaining a digital value converted by the digital conversion means;
Based on the digital value obtained by the computing means, the analog / reference signal provided corresponding to the first non-reference block due to the difference between the reference voltage of the reference block and the first non-reference block. Correction means for correcting so as to eliminate an error occurring in the digital value of the voltage across the unit cell converted by the digital conversion means;
A voltage detection apparatus comprising:   The voltage detection apparatus according to claim 1, wherein the input unit is provided so as to supply the divided voltage to the analog / digital conversion unit via a capacitor.

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