JP5067934B2 - Switching circuit - Google Patents

Description

  The present invention relates to an improvement in a control electrode (hereinafter abbreviated as a gate) drive circuit of a metal oxide field effect transistor (hereinafter abbreviated as a MOSFET) of a switching circuit.

If the horizontal transfer electrode drive circuit of the charge transfer type (Cherge Cuopled Device, hereinafter abbreviated as “CCD”) image sensor also has an amplitude of 5V or less, a logic integrated circuit for driving the CCD image sensor can be used. A CMOS logic integrated circuit can be used. (See Non-Patent Document 1)
However, an electron multiplying CCD image pickup device (hereinafter referred to as EM-CCD) can increase sensitivity in combination with electronic cooling, but a horizontal transfer electrode (Charge Multiplication Gate) that performs electron multiplication of EM-CCD. (Hereinafter abbreviated as CMG) is TI's 330,000 pixels, with a capacitive load of about 25 pF, 12.5 MHz, voltage amplitude is large and variable from 18 Vp-p to 24 Vp-p, and high electron gain with high CMG voltage amplitude At the time of doubling, the sensitivity changes by 1.4 times at 0.1 V, and the sensitivity changes by 1.8 times at 11 ° C. Therefore, it is required to ensure the amplitude of the drive waveform, to have high stability, and to reduce heat generation. In the e2V product, the CMG voltage amplitude is larger from 35 Vp-p to 45 Vp-p. Therefore, it is difficult to use a general-purpose IC having a withstand voltage of about 18 V like other electrode driving of a CCD image pickup device. Therefore, a pulse waveform is supplied to the horizontal transfer electrode for electron multiplication of the EM-CCD by the drain of a complementary enhancement type MOSFET with variable power supply voltage, and the gate of the MOSFET can be driven by a CMOS logic integrated circuit. It is common. (See Non-Patent Document 2 and Non-Patent Document 3)
Further, as shown in FIG. 15 of the block diagram showing the configuration of a conventional complementary MOSFET drive circuit in which the conduction time and the non-conduction time are substantially equal for the battery-powered switching power source and the non-multiplier horizontal transfer electrode Hφ drive. This circuit has also been put into practical use (see Patent Document 1). FIG. 15 is a schematic diagram showing the input / output voltage of the conventional complementary MOSFET drive circuit, FIG. 16 is a schematic diagram showing the input / output voltage operation of the conventional complementary MOSFET drive circuit, and FIG. 17 is a conventional complementary MOSFET drive. The schematic diagram which shows the input / output waveform of the operation | movement of a circuit is shown.

  15 and 17, when the output voltage Vout10 of the IC 10 that drives the gate of the MOSFET becomes 0V, the diode D5 is turned on and driven by the resistor 3, and the gate voltage of the Qch of the Pch-MOSFET is relatively long. When the threshold voltage is exceeded, Q1 of the Pch-MOSFET is turned on. When the output voltage Vout10 of the IC 10 that drives the gate of the MOSFET becomes 5V, the diode D6 becomes conductive and is driven by the resistor 4, and the gate voltage of the Q1 of the Pch-MOSFET rises in a short time until the threshold voltage, and the charge charge is increased. Until it is pulled out, it remains at the threshold voltage, and Q1 of the Pch-MOSFET is turned off in a relatively long time.

  Similarly, when the output voltage Vout10 of the IC 10 that drives the gate of the MOSFET becomes 0V, the diode D7 becomes conductive and is driven by the resistor 5, and the gate voltage of the Nch-MOSFET Q2 falls to the threshold voltage in a short time. Until the charge charge is extracted, the threshold voltage is maintained and Q2 of the Nch-MOSFET is turned off in a relatively long time. When the output voltage Vout10 of the IC 10 for driving the gate of the MOSFET becomes 5V, the diode D8 is turned on and driven by the resistor 6, so that the gate voltage of the Nch-MOSFET Q2 exceeds the threshold voltage in a relatively long time, and the Nch- MOSFET Q2 is turned on.

  As a result, Q1 of the Pch-MOSFET and Q2 of the Nch-MOSFET have substantially the same conduction time and non-conduction time.

  The required driving capability is NchMOSFET turn-on <PchMOSFET turn-on <NchMOSFET turn-off <PchMOSFET turn-off. In FIG. 15 of the prior art, the driving capability is asymmetric between the diodes D2 and D5 to D10.

  The capacitance between the gate and source (hereinafter abbreviated as Cgs) of the MOSFET is proportional to the product of the drain-source breakdown voltage (hereinafter abbreviated as breakdown voltage) and the drain current capacity (hereinafter abbreviated as current capacity). It is almost proportional. With a withstand voltage of 30 V in mass production in 2006, the Pch peak current capacity is 1.6 A, about 40 pF, and the Nch peak current capacity is 2.8 A, about 30 pF. Further, the gate charge charge (hereinafter abbreviated as Qg) for cutting off the current of the MOSFET is proportional to the product of the withstand voltage and the current capacity and the drain current, and is also approximately proportional to the fineness of processing. With a withstand voltage of 30 V in mass production in 2006, Qg is about 2100 pC per 1 A of Pch current and about 1400 pC per 1 A of Nch current, and Pch requires a large driving capability.

The gate-source cut-off (threshold) voltage Vgth is substantially proportional to the fineness of processing, and is usually 0.4 to 1.4 V at a withstand voltage of 30 V in 2006 mass production. The gate-source (control) voltage at which the conduction resistance is almost saturated is also almost proportional to the fineness of processing. In the mass production of 30V in 2006, Pch is usually 4.5V and Nch is usually 2.5V. Requires a large driving capacity.
Sony CCD image sensor ICX422 data sheet ICX422 diagonal 11 mm (2/3 type) solid-state image sensor for EIA black and white TI TC247SPD EM-CCD image sensor data sheet TC247SPD-B0 680 x 500 PIXEL IMPACTRONTM MONOCHROME CCD IMAGE SENSOR e2V CCD65 EM-CCD Image Sensor Data Sheet A1A-CCD65_Series_Ceramic Issue 7, June 2004 JP 2001-298934 A

  In the conventional technique in which the conduction time and the non-conduction time are substantially equal to each other, the resistor series diodes D5 to D8 of the output of FIG. 15 and the DC regeneration diodes D2, D9,. FIG. 17 is a schematic diagram showing the input / output waveform of the operation of the conventional complementary MOSFET drive circuit, with D10, the gate drive amplitude is reduced by 1.8V, which is three times the diode forward drop voltage 0.6V, to 3.2V. It becomes like this.

  The horizontal transfer CMG electrode capacitance switching circuit that performs electron multiplication of EM-CCD has a large amplitude of, for example, 24 Vp-p, and has a low withstand voltage and conductive resistance for driving a battery input switching power supply and non-multiplier horizontal transfer electrode Hφ. A MOSFET having a low gate-source (control) voltage that is almost saturated cannot be used. The gate voltage at which the on-resistance of the PchMOSFET driven by CMG decreases is as high as 4.5V, for example. Therefore, if the conventional technique in which the conduction time and the non-conduction time are forcibly equal is applied to the CMG drive, the gate voltage is insufficient as 3.2 V, the on-resistance of the PchMOSFET does not decrease, and the symmetry and saturation of the CMG voltage Vo The waveform characteristics such as the characteristics deteriorate, the effective CMG voltage amplitude decreases, and the effective sensitivity of the EM-CCD decreases. When VH is increased in order to ensure sensitivity, the turn-off of the MOSFET is delayed, and reactive power for simultaneously conducting NchMOSFET and PchMOSFET is consumed. It is expected that the amount of heat generated increases due to a large loss due to reactive power, the temperature rises, and the sensitivity of the EM-CCD decreases.

  In other words, the present invention secures the gate drive amplitude of the Pch MOSFET that drives the charge multiplying electrode of the EM-CCD, pulls out the charge charge amount Qg of the MOSFET in a short time, and turns it on for the time to pull out Qg. The object is to solve the above problems by delaying the phase, keeping the conduction period of the MOSFET short and keeping the non-conduction period short.

  In order to solve the above problems, the present invention provides an inverting switching circuit using a P-type voltage control semiconductor element and an N-type voltage control semiconductor element, and unbuffered inversion for driving a control electrode of the P-type voltage control semiconductor element. Means for shifting the input voltage in the ground direction with respect to the power supply voltage of the logic CMOS integrated circuit, and the input voltage relative to the power supply voltage of the unbuffered inversion logic CMOS integrated circuit that drives the control electrode of the N-type voltage control semiconductor element It is a switching circuit characterized by having at least one of means for shifting in the power supply voltage direction.

  In an inverting switching circuit using a P-type voltage control semiconductor element and an N-type voltage control semiconductor element, the input voltage of an unbuffered inversion logic CMOS integrated circuit that drives the control electrode of the P-type voltage control semiconductor element is grounded or negative. Means for resistance-dividing the voltage into voltage; means for resistance-dividing the input voltage of the unbuffered inversion logic CMOS integrated circuit that drives the control electrode of the N-type voltage control semiconductor element to positive voltage; and control of the P-type voltage control semiconductor element At least one of means for setting the power supply voltage of the unbuffered inversion logic CMOS integrated circuit for driving the electrode higher than the maximum value of the input voltage of the unbuffered inversion logic CMOS integrated circuit for driving the control electrode of the P-type voltage control semiconductor element; A switching circuit comprising:

  Further, in the above, with respect to the power supply voltage of the inverting switching circuit, the absolute value of the voltage to be resistance-divided, the reciprocal of the resistance-dividing ratio, and the unbuffered inversion for driving the control electrode of the P-type voltage control semiconductor element A switching circuit comprising means for varying at least one of a power supply voltage of a logic CMOS integrated circuit in conjunction with the logic CMOS integrated circuit.

  That is, according to the present invention, in an inverting switching circuit using a P-type voltage control semiconductor element and an N-type voltage control semiconductor element, the drawing current value and discharge of an unbuffered inverting logic CMOS integrated circuit that drives the gate of the voltage control semiconductor element. It is a switching circuit characterized by setting current values individually.

  As described above, according to the present invention, a relatively high gate drive voltage approximated to the on-resistance saturation gate voltage of the Pch MOSFET, a large amount of drive current for saturation operation at turn-off, and moderate drive at non-saturation operation at turn-on. Current, a relatively low gate drive voltage approximating the on-resistance saturation gate voltage of the Nch MOSFET, a lot of drive current for saturation operation at turn-off, and a moderate drive current at non-saturation operation at turn-on. Along with the speeding up of Qg extraction, the gate waveforms of both channel MOSFETs turn off quickly, turn on slowly, turn off period wide, and turn on period narrow. Further, the input voltage is shifted with respect to the power supply voltage of the CMOS inversion logic integrated circuit, so that the off period of the gate waveforms of both channel MOSFETs is wide and the on period is narrowed. Therefore, the conduction time of both chMOSFETs that have become wider by the time required for Qg extraction is also shortened, the through current generated because the conduction time of the PchMOSFET and the conduction time of the NchMOSFET overlap, and the amplitude of the capacitive load switching waveform is reduced. It is ensured and improves waveform characteristics such as symmetry and saturation, and further reduces power loss.

  In addition, the present invention increases the turn-off drive capability of the CMOSIC in proportion to the amount of charge extracted from the MOSFET, thereby pulling out the Qg in a short time, or speeding up the MOSFET turn-off, or approximating the on-state gate voltage to the on-resistance saturated gate voltage. Waveform characteristics such as symmetry and saturation are improved, or the OFF period of the MOSFET is lengthened and the ON period is shortened to reduce the reactive power at which the Nch MOSFET and the Pch MOSFET are simultaneously conducted.

  Further, when driving the CMG electrode capacitance of the EM-CCD, the through current is reduced by increasing the turn-off speed of the MOSFET, the heat generation and the temperature rise for the loss are reduced, and the sensitivity is improved. Further, since the CMG waveform characteristics are improved and the amplitude voltage is secured, the effective sensitivity is improved.

  The present invention will be described with reference to FIGS.

  FIGS. 1 and 11 are block diagrams showing one embodiment of the present invention in which a MOSFET driving circuit drives a gate with a relatively small current when turned on and a relatively large current when turned off, and another embodiment. FIGS. 2 and 12 are schematic diagrams showing input / output voltages of the operation of the MOSFET driving circuit according to one embodiment of the present invention and another embodiment, and FIGS. 3 to 10, FIG. 13 and FIG. It is a schematic diagram showing input / output waveforms of the operation of one embodiment of the present invention and another embodiment of the MOSFET drive circuit.

  1 to 14, VA is a power source, Vgain is a variable voltage source, Vref is a reference voltage source, VccH, VccL and 5V are logic power sources, VH and VL are switching circuit power sources, and IC1 and IC2 are CMOS. An unbuffered inverter logic integrated circuit (InvIC), IC5 is an operational amplifier (Operational Amplifier: Op Amp), IC6 to IC8 are variable power supply circuits (Adjist Regurator: Adj Reg), Q1 is a PchMOSFET, Q2 is an NchMOSFET, D1, D2 Is a DC regeneration diode, and D3 is a DC regeneration Schottky barrier diode (hereinafter referred to as SBD). CMG is an electron multiplying horizontal transfer electrode of EM-CCD, CL is a load capacitor, C1 and C2 are AC coupling capacitors, R1 and R2 are gate drive resistors, and R3 to R22 are division resistors.

  3 to 10, 13, and 14, Vin1 is an input waveform of the logic circuit 1, Vin2 is an input waveform of the logic circuit 2, Vout1 is an output waveform of the logic circuit 1, and Vout2 is a logic circuit. 2, Vg1 is the gate voltage of Q1 of the PchMOSFET, and Vg2 is the gate voltage of Q2 of the NchMOSFET.

  In FIG. 1 and FIG. 11 of the block diagram showing one embodiment of the present invention and another embodiment, Vgain is inverted by the operational amplifiers IC5, R7, and R8 as in FIG. 15 of the prior art block diagram. Variable power supply circuits IC8, R9, R10, and R11 re-invert the power supply voltage of the MOSFET that determines the voltage amplitude of CMG that varies the sensitivity.

  The difference between FIG. 1 and FIG. 11 in the block diagram showing one embodiment of the present invention and another embodiment and FIG. 15 in the block diagram of the prior art is that a diode is connected to the output of the logic integrated circuit as shown in FIG. In FIG. 1 and FIG. 11, the input voltage range of the CMOS unbuffer inversion logic integrated circuit that drives the control electrode of the voltage control semiconductor element is changed to CMOS unbuffer inversion. Different from the power supply voltage range of the logic integrated circuit, the gate of the N-type voltage control semiconductor element and the gate of the P-type voltage control semiconductor element are driven with a relatively small current when turned on and with a relatively large current when turned off. And shortening the conduction period and lengthening the non-conduction period. As will be described in detail later, in FIG. 1, the MOSFET power supply voltage and the input voltage range of the CMOS inversion logic integrated circuit are varied in conjunction with R4 and R6, and if R4 and R6 are opened, a P-type voltage control semiconductor element The input voltage range of the CMOS unbuffered inversion logic integrated circuit for driving the control electrodes of the N type is controlled to be low, and the input voltage of the CMOS unbuffered inversion logic integrated circuit for driving the control electrodes of the N-type voltage control semiconductor element is fixed to be high. . Although details will be described later, in FIG. 11, the MOSFET power supply voltage and the power supply voltage of the CMOS inversion logic integrated circuit are varied in conjunction with R12 and R15. If R12 and R15 are opened, the P-type voltage control semiconductor device The power supply voltage of the CMOS unbuffered inversion logic integrated circuit that drives the control electrode is fixed high, and the power supply voltage of the CMOS unbuffered inversion logic integrated circuit that drives the control electrode of the N-type voltage control semiconductor element is fixed low.

An embodiment of the present invention will be described below with reference to FIGS.
In FIG. 1, the gate voltage at which the on-resistance of the Pch MOSFET of Q1 decreases is as high as 4.5V, for example, so VccH is set to be equal to or less than the recommended maximum voltage of IC1. That is, if the IC1 type is 74AC, VccH = 6V or less, and if the IC1 type is 74LVC or TC7SZ, VccH = 5.5V or less. The gate voltage that lowers the on resistance of the N2 MOSFET of Q2 is as low as 2.5 V, for example, so that if the IC2 type is 74LVC or TC7SZ that has a sufficiently high speed, high drive capability and allows an input voltage higher than the power supply voltage, VccL = 4.5V To do.

  Instead of varying the divided voltages VD1 and VE1 with the operational amplifiers IC5 and IC9, the divided resistors R4 and R6 are opened and fixed divided voltages VD2 and VE2 are used. A variable resistor IC may be used for R22 to be linked with the MOSFET power supply voltage. If the voltage dividing resistors R4 and R6 are present, the voltage dividing resistors R21 and R22 may be opened, and the IC1 and IC2 types and the VccH and VccL are different. 4 (a2) or the operation waveform of FIG. 2 (c) results in the operation waveforms of FIG. 7 (c1) and FIG. 8 (c2).

  For simplicity, the voltage dividing resistors R4 and R6 are opened, and the voltage dividing resistors R21 and R22 are operated, and the operation waveforms of FIGS. 5 (b1) and 6 (b2) in the operation of FIG. The operation of d) may be fixed in the middle of the operation waveforms of FIG. 9 (d1) and FIG. 10 (d2). More simply, VD2 may be grounded and VE2 may be VccH.

  Here, in FIG. 1, since the gate voltage at which the on resistance of the Pch MOSFET of Q1 decreases is as high as 4.5V, for example, the DC regenerative diode D3 is set to 1SS388 having a forward drop voltage of 0.3V of SBD, for example, 2mA. The Q1 gate voltage Vgs of the Pch MOSFET is secured from -5.4V to -4.7V. Further, while the gate voltage is secured, the difference between the power supply voltage of the logic CMOS integrated circuit and the output voltage of the logic CMOS integrated circuit when driving the threshold voltage of the gate of the MOSFET is reduced, but the drive current of 32 mA is guaranteed. If a high-speed logic CMOS integrated circuit such as TC7SZ series is used, or if a plurality of high-speed logic CMOS integrated circuits such as LVC series that guarantee a drive current of 24 mA are connected in parallel, VccH = 5V may be set. The operations shown in FIGS. 2C and 2D result in the operation waveforms shown in FIGS. 7C1 and 8C2 and FIGS. 9D1 and 10D2. If the IC1 is made to have a higher driving capability or the number of parallel circuits is increased, the DC regenerative diode D3 may be 1SS421 having a forward drop voltage of 0.2 mA of 2 mA by SBD.

  As a result, as shown in FIG. 2, the highest level of the input Vin1 of the unbuffered inverter logic integrated circuit IC1 is lower than the power supply voltage VccH of the IC1, and the driving capability of the inverted output low level of the IC1 is relatively low in the non-saturated operation. The driving capability when Q1 is turned on is relatively low, and the turn-on of Q1 is delayed. The minimum level of the input Vin1 of the IC1 is near the ground potential, the driving capability of the inverted output high level of the IC1 is relatively high in the saturation operation, the driving capability at the time of turning off the Q1 of the PchMOSFET is relatively high, and the turning off of the Q1 is quick. . The maximum level of the input Vin2 of the unbuffered inverter logic integrated circuit IC2 is higher than or close to VccL of the power supply voltage VccL of the IC1, and the driving capability of the inverted output low level of the IC2 is relatively high in the saturation operation, and when the Q2 of the NchMOSFET is turned off. The driving capability is relatively high in non-saturated operation, and Q2 is turned off faster. The minimum level of the input Vin2 of the IC2 is higher than the ground potential, the driving capability of the inverted output high level of the IC2 is relatively low in the non-saturation operation, the driving capability at the turn-on time of the Q1 of the PchMOSFET is relatively low, and the turn-on time of the Q1 is slow. Become. Further, since the central value VccH / 2 of the power supply voltage of IC1, the central value VccL / 2 of the power supply voltage of IC2 and the central value of the input voltage Vin are shifted, the output Vout1 of IC1 and the output Vout2 of IC2 are low. The period of Hi becomes asymmetric, and the on period of Q1 and Q2 is short and the off period is long.

  Further, the input Vin1 of the IC1 is divided by the voltage dividing resistors R3 and R4, and the input Vin2 of the IC2 is divided by the voltage dividing resistors R5 and R6. As a result, as shown in FIG. 2, the highest level of the input Vin1 of the unbuffered inverter logic integrated circuit IC1 is lower than the power supply voltage 5V of the IC1, and the driving capability of the inverted output low level of the IC1 is relatively low in the saturation operation. The driving capability at the turn-on of Q1 is relatively low, and the turn-on of Q1 is delayed. The lowest level of the input Vin1 of the IC1 is the ground potential, and the driving capability of the inverted output high level of the IC1 is relatively high in the non-saturation operation, the driving capability at the time of turning off the Q1 of the PchMOSFET is relatively high, and the turning off of the Q1 is quick. . The maximum level of the input Vin2 of the unbuffered inverter logic integrated circuit IC2 is 5V, which is the same as the power supply voltage of the IC2, and the driving capability of the inverted output of the IC2 is relatively high in the saturation operation, and the driving capability when the Q2 of the NchMOSFET is turned off. Is relatively high and Q2 turn-off is faster. The minimum level of the input Vin2 of the IC2 is higher than the ground potential, the driving capability of the inverted output high level of the IC2 is relatively low in the non-saturation operation, the driving capability at the turn-on time of the Q1 of the PchMOSFET is relatively low, and the turn-on time of the Q1 is slow. Become.

  That is, by varying the voltages VD1 and VE1 or by varying the resistors R21 and R22, the MOSFET power supply voltage and the input voltage range of the CMOS inversion logic integrated circuit are varied in conjunction with each other. As a result, even if the amount of charge charge Qg drawn proportional to the drain current of the MOSFET changes as shown in FIGS. 3 to 10, the conduction period and the non-conduction period between Q1 and Q2 are almost the same between Q1 and Q2. No through current flows.

  As a result, the voltage amplitude of CMG increases due to high sensitivity operation, the drain current of the MOSFET increases, and even if Qg increases, the input voltage of the CMOS inversion logic integrated circuit changes and the turn-on becomes slower, The turn-off is faster, the through current is less, the CMG amplitude voltage and the rectangular waveform are secured, the sensitivity is not lowered, and the effective sensitivity is improved.

  Hereinafter, another embodiment of the present invention will be described with reference to FIGS.

  In FIG. 11, the output of the operational amplifier IC7 whose Vgain is inverted by R12 and R15 is re-inverted by the variable power supply circuits IC9, R12, R13 and R14, and the power supply voltage VH of the PchMOSFET and the power supply of the CMOS inverted logic integrated circuit for driving the PchMOSFET. The voltage VccH is varied in direct proportion, and the input voltage Vin2 of the CMOS inversion logic integrated circuit that drives the Nch MOSFET is divided by the resistors R6 and R22 into the power supply voltage VccH.

  In FIG. 11, since the gate voltage at which the on-resistance of the Pch MOSFET Q1 decreases is as high as 4.5 V, for example, VccH is positively linked to VH and varies below the recommended maximum voltage of IC1. In other words, if IC1 type is 74AC, VccH = 6V or less, and if IC1 type is 74LVC or TC7SZ, VccH = 5.5V or less. The charge voltage Qg and turn-off delay of the Nch MOSFET Q2 are smaller than those of the Pch MOSFET Q1, and the gate voltage at which the on resistance of Q2 decreases is as low as 2.5 V, for example. If it is 74LVC or TC7SZ that permits the above, VccL = 4.5V. As a result, as shown in FIG. 12, the highest level of the input Vin1 of the unbuffered inverter logic integrated circuit IC1 is lower than the power supply voltage VccH of the IC1, and the inverting output low level driving capability of the IC1 is relatively low in the non-saturated operation. The driving capability when Q1 is turned on is relatively low, and the turn-on of Q1 is delayed. The minimum level of the input Vin1 of the IC1 is the ground potential, the driving capability of the inverted output high level of the IC1 is relatively high in the saturation operation, the driving capability at the time of turning off the Q1 of the PchMOSFET is relatively high, and the turning off of the Q1 becomes fast. The highest level of the input Vin2 of the unbuffered inverter logic integrated circuit IC2 is higher than the power supply voltage VccL of the IC1, the low level driving capability of the inverted output of the IC2 is relatively high in the saturation operation, and the driving capability when the N2 MOSFET Q2 is turned off is Relatively high, Q2 turn-off is faster. The minimum level of the input Vin2 of the IC2 is higher than the ground potential, the driving capability of the inverted output high level of the IC2 is relatively low in the non-saturation operation, the driving capability at the turn-on time of the Q1 of the PchMOSFET is relatively low, and the turn-on time of the Q1 is slow. Become.

  That is, the power supply voltage of the MOSFET and the power supply voltage of the CMOS inversion logic integrated circuit are varied in conjunction with each other. As a result, even if the amount of charge charge Qg drawn proportional to the drain current of the MOSFET changes as shown in FIGS. 13 and 14, the conduction period and the non-conduction period between Q1 and Q2 are almost equal. No through current flows.

  As a result, the voltage amplitude of CMG increases due to high sensitivity operation, the drain current of the MOSFET increases, and even if Qg increases, the input voltage of the CMOS inversion logic integrated circuit changes and the turn-on becomes slower, The turn-off is faster, the through current is less, the CMG amplitude voltage and the rectangular waveform are secured, the sensitivity is not lowered, and the effective sensitivity is improved. This is the same as FIGS.

  As described above, according to one embodiment and another embodiment of the present invention, even if the voltage amplitude of the CMG increases and the drain current of the MOSFET increases due to high sensitivity operation, the Qg increases. Turn on the MOSFET by setting the input voltage range lower than the power supply voltage of the CMOS unbuffered inverting logic integrated circuit that drives the gate of the PchMOSFET and higher than the power supply voltage of the CMOS unbuffered inverting logic integrated circuit that drives the gate of the NchMOSFET. Is slow, the turn-off is fast, the waveform characteristics such as symmetry and saturation of CMG are improved, and the amplitude voltage and the rectangular waveform are secured, so that the sensitivity is not lowered and the effective sensitivity is improved. In addition, the power loss is reduced by the amount of through current, heat generation and temperature rise are reduced, and sensitivity is improved.

  Furthermore, the present invention can be widely used not only in the EM-CCD CMG drive circuit but also in the drive circuit of the complementary FET high-speed switching circuit in which the power supply voltage changes.

The block diagram which shows the structure of the complementary MOSFET drive circuit of one Example of this invention Schematic diagram showing several input / output voltage operations of the complementary MOSFET drive circuit of one embodiment of the present invention ((a) VccH = 5.5V, VccL = 4.5V, R4 = R6 = 390, R21 = R22 = open a1 : VD1 = VE1 = 2.5V, a2: VD1 = 0V, VE1 = 5V (b) VccH = 5.5V, VccL = 4.5V, VD2 = 0V, VE2 = 5V, R4 = R6 = open b1: R21 = R22 = 680 , B2: R21 = R22 = 390 (c) VccH = 5V, VccL = 5V, R4 = R6 = 390, R21 = R22 = open C1: VD1 = VE1 = 2.5V, C2: VD1 = -0.5V, VE1 = 5.5 V (d) VccH = 5V, VccL = 5V, VD2 = -0.5V, VE2 = 5.5V, R4 = R6 = open d1: R21 = R22 = 680, d2: R21 = R22 = 390) Schematic diagram showing input / output waveform operation of complementary MOSFET drive circuit of one embodiment of the present invention ((a1) VccH = 5.5V, VccL = 4.5V, R4 = R6 = 390, R21 = R22 = open VD1 for light load = VE1 = 2.5V) Schematic diagram showing input / output waveform operation of complementary MOSFET drive circuit of one embodiment of the present invention ((a2) VccH = 5.5V, VccL = 4.5V, R4 = R6 = 390, R21 = R22 = open heavy load VD1 = 0V, VE1 = 5V) Schematic diagram showing input / output waveform operation of complementary MOSFET drive circuit of one embodiment of the present invention ((b1) VccH = 5.5V, VccL = 4.5V, VD2 = 0V, VE2 = 5V, R4 = R6 = open light load (R21 = R22 = 680) Schematic diagram showing input / output waveform operation of complementary MOSFET drive circuit of one embodiment of the present invention ((b2) VccH = 5.5V, VccL = 4.5V, VD2 = 0V, VE2 = 5V, R4 = R6 = open heavy load (R21 = R22 = 390) The schematic diagram which shows the input-output waveform operation | movement of the complementary MOSFET drive circuit of other one Example of this invention. (c1) VccH = 5V, VccL = 5V, R4 = R6 = 390, R21 = R22 = open Light load VD = VE = 2.5V) The schematic diagram which shows the input-output waveform operation | movement of the complementary MOSFET drive circuit of one Example of this invention. (c2) VccH = 5V, VccL = 5V, R4 = R6 = 390, R21 = R22 = open heavy load VD = -0.5V VE = 5.5V) The schematic diagram which shows the input-output waveform operation | movement of the complementary MOSFET drive circuit of one Example of this invention. (d1) VccH = 5V, VccL = 5V, VD2 = -0.5V, VE2 = 5.5V, R4 = R6 = open for light load R21 = R22 = 560 The schematic diagram which shows the input-output waveform operation | movement of the complementary MOSFET drive circuit of one Example of this invention. (d2) VccH = 5V, VccL = 5V, VD2 = -0.5V, VE2 = 5.5V, R4 = R6 = open heavy load R21 = R22 = 330) Block diagram showing the configuration of a complementary MOSFET drive circuit according to another embodiment of the present invention (e) VccH = 5V to 6V VccL = 5V to 4V Schematic diagram showing input / output voltage operation of complementary MOSFET drive circuit of another embodiment of the present invention (e) VccH = 5V to 6V VccL = 5V to 4V The schematic diagram which shows the input-output waveform operation | movement of the complementary MOSFET drive circuit of other one Example of this invention. (e1) VccH = 5.5V VccL = 4.5V For light load The schematic diagram which shows the input-output waveform operation | movement of the complementary MOSFET drive circuit of other one Example of this invention. ((e2) VccH = 6V VccL = 4V for heavy load) The block diagram which shows the structure of the conventional complementary MOSFET drive circuit. Schematic diagram showing input / output voltage operation of a conventional complementary MOSFET drive circuit Schematic diagram showing the input / output waveform operation of a conventional complementary MOSFET drive circuit

Explanation of symbols

IC1, IC2: Unbuffered inversion logic CMOS integrated circuit (UB Inv IC),
IC10: Inverted logic CMOS integrated circuit (Inv IC),
IC5, IC9: Operational Amplifier (Op Amp),
IC6, IC7: Variable power supply circuit (Adjist Regurator: Adj Reg),
Q1: PchMOSFET, Q2: NchMOSFET,
D1: Schottky barrier diode, D2 to D8: diode,
C1, C2: capacity, CMG: EM-CCD electron multiplying horizontal transfer electrode,
Hφ: non-multiplied horizontal transfer electrode, R1 to R14, R18 to R25: resistance,
VA, VB: power supply, VCCH, VCCM, VCCL, 5V: logic power supply,
8V: non-multiplied horizontal transfer electrode power supply, VH, VL: switching circuit power supply,
Vgain, Vref: voltage source, Vin1 to Vin4, Vin10: IC input voltage,
Vout1 to Vout4, Vout10: IC output voltage, Vo: CMG voltage,
Vφ: non-multiplied horizontal transfer electrode voltage, Vg1, Vg2: MOSFET gate voltage,
VD1, VE1, VD2, VE2: Divided voltage

Claims (1)

In an inverting switching circuit using a P-type voltage control semiconductor element and an N-type voltage control semiconductor element,
Means for resistively dividing the input voltage of a 74LVC or TC7SZ unbuffered inversion logic CMOS integrated circuit that drives the control electrode of the P-type voltage control semiconductor element to ground or a negative voltage;
Means for resistively dividing the input voltage of the 74LVC or TC7SZ unbuffered inversion logic CMOS integrated circuit that drives the control electrode of the N-type voltage control semiconductor element to a positive voltage;
For the power supply voltage of the inverting switching circuit,
A switching circuit comprising means for varying the power supply voltage of a 74LVC or TC7SZ unbuffered inversion logic CMOS integrated circuit for driving a control electrode of the P-type voltage control semiconductor element in conjunction with the P-type voltage control semiconductor element.

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