JP5073541B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a static semiconductor memory device.

  FIG. 4 is a circuit diagram of a conventional general static random access memory (SRAM) cell.

  The SRAM cell includes a pair of driver transistors ND1 and ND2 that are NMOS transistors, a pair of load transistors PL1 and PL2 that are PMOS transistors, and a pair of access transistors NA1 and NA2 that are NMOS transistors.

  The source electrodes of the driver transistors ND1 and ND2 are each connected to ground (GND). The source electrodes of the load transistors PL1 and PL2 are each connected to the power supply VDD. The drain electrode of the driver transistor ND1 is connected to the drain electrode of the load transistor PL1. Hereinafter, this connection point is referred to as “node 1”. The drain electrode of the driver transistor ND2 is connected to the drain electrode of the load transistor PL2. This connection point is hereinafter referred to as “node 2”. The gate electrode of driver transistor ND1 and the gate electrode of load transistor PL1 are both connected to node 2. The gate electrode of driver transistor ND2 and the gate electrode of load transistor PL2 are both connected to node 1. A latch circuit is formed by a CMOS inverter composed of the driver transistor ND1 and the load transistor PL1, and a CMOS inverter composed of the driver transistor ND2 and the load transistor PL2. One of the source / drain electrodes of the access transistor NA1 is connected to the node 1, and the other is connected to the bit line True. One of the source and drain electrodes of the access transistor NA2 is connected to the node 2, and the other is connected to the bit line Bar. The gate electrodes of access transistors NA1 and NA2 are each connected to a word line.

  In the SRAM cell, the ratio of the current drive capability between the access transistors NA1 and NA2 activated by the word line and the driver transistors ND1 and ND2 in the latch part is usually about 1: 3, and the load transistors PL1 and PL2 in the latch part are High-speed and stable operation is realized by setting the current driving capability to be equal to or less than that of the access transistors NA1 and NA2.

  The static noise margin, which is an index indicating the stability of data stored in the memory cell, can be improved by increasing the current drive capability of the load transistors PL1 and PL2 relative to the driver transistors ND1 and ND2.

  However, when the current driving capability of the load transistors PL1 and PL2 is made larger than that of the driver transistors ND1 and ND2, the capability of holding the node High becomes high at the time of writing, and it becomes difficult to extract the node charge (inverted to Low). The writing margin deteriorates.

  That is, since the static noise margin and the write margin are in a trade-off relationship, it is difficult to improve both at the same time.

  FIG. 5 is a configuration diagram of an SRAM cell disclosed in Patent Document 1 with an improved static noise margin.

  The SRAM cell includes a pair of driver transistors 11 and 12 that are NMOS transistors, a pair of load transistors 13 and 14 that are PMOS transistors, and a pair of access transistors 15 and 16 that are NMOS transistors.

  The source electrodes of the driver transistors 11 and 12 are each connected to ground (GND). The source electrodes of the load transistors 13 and 14 are each connected to the power supply VDD. The drain electrode of the driver transistor 11 is connected to the drain electrode of the load transistor 13 and the drain electrode of the access transistor 15. Hereinafter, this connection point is referred to as “node N1”. The access transistor 15 has a source electrode connected to the bit line 18 and a gate electrode connected to the word line 17. The drain electrode of the driver transistor 12 is connected to the drain electrode of the load transistor 14 and the drain electrode of the access transistor 16. Hereinafter, this connection point is referred to as “node N2”. The access transistor 16 has a source electrode connected to the inverted bit line 19 and a gate electrode connected to the word line 17. The gate electrode of the driver transistor 11 and the gate electrode of the load transistor 13 are both connected to the node N2. The gate electrode of the driver transistor 12 and the gate electrode of the load transistor 14 are both connected to the node N1.

  The SRAM memory cell shown in FIG. 5 is a bulk type, but in this configuration, the bit line 18 is connected to the well of the load transistor 14 and the inverted bit line 19 is connected to the well of the load transistor 13. Node N1 is at L level and node N2 is at H level. At the time of reading, the bit line 18 and the inverted bit line 19 are precharged to H level. When the word line 17 rises to the H level, a column current flows through the driver transistor 11. When the potential of the bit line 18 changes to L level, the well potential of the load transistor 14 simultaneously changes to L level. Therefore, even if the current driving capability of the load transistor 14 is improved, the potential of the node N1 rises due to noise or the like, and the driver transistor 12 is slightly turned on, the potential at the node N2 drops from the H level. Is suppressed, the potential difference between the bit lines 18 and 19 can be read, and malfunction during reading is suppressed.

Japanese Patent Laid-Open No. 2006-065588

  In the present invention, the following analysis was performed. That is, in order to realize the memory cell (Patent Document 1) having the circuit configuration of FIG. 5 with silicon, the wells of the load transistors 13 and 14 which are PMOS transistors have different potentials, and therefore the wells must be separated. In general, since a transistor is formed on a P-type silicon substrate, N wells must be separated from each other in order to separate the wells. At this time, even when the potentials of the separated N wells are different from each other, it is necessary to separate the N wells while keeping a minimum distance so as not to cause a short circuit. As a result, there is a problem that the area of the SRAM cell is greatly increased.

  In addition, there is an SRAM that performs a read operation without turning off a precharge transistor connected to a bit line pair of a non-selected address for the purpose of eliminating the precharge time of the next data read and speeding up the read operation. is there. The configuration of the SRAM cell disclosed in Patent Document 1 cannot improve the static noise margin in such an SRAM. This is because the potential of the bit line of the SRAM cell of the non-selected address does not change to the L level, the well potential of the load transistor does not become the L level, and the current driving capability is not improved.

  Therefore, it is a problem to simultaneously increase the static noise margin and the write margin while suppressing an increase in the cell area of the static semiconductor memory device.

A static semiconductor memory device according to an aspect of the present invention includes an SRAM cell and an additional transistor control circuit. The SRAM cell has drains connected at a first node and gates at a second node. A first CMOS inverter including a PMOS transistor and an NMOS transistor connected to each other; a PMOS transistor and an NMOS transistor having drains connected to each other at the second node and gates connected to each other at the first node; A second CMOS inverter; a first access transistor having one end of a source / drain end connected to the first node and the other end connected to a first bit line;
One end of the source / drain end is connected to the second node, the other end is connected to the second bit line, one end of the source / drain end is connected to the first node, and the gate is the gate An SRAM including a first additional transistor connected to a second node, and a second additional transistor having one end of a source / drain end connected to the second node and a gate connected to the first node It is a cell, and the additional transistor control circuit is an additional transistor control circuit in which the other ends of the source and drain terminals of the first and second additional transistors are respectively connected.

  A static semiconductor memory device according to another aspect of the present invention is a static semiconductor memory device including a latch circuit composed of first and second CMOS inverters, and a PMOS transistor constituting the first CMOS inverter A first additional transistor, which is a PMOS transistor in which the gate electrodes are connected in common and the drain electrodes are connected in common at the first node, and the second CMOS inverter. A load transistor that is a PMOS transistor, and a second additional transistor that is a PMOS transistor in which gate electrodes are commonly connected and drain electrodes are commonly connected in a second node; First additional transistor saw The electrode is configured to be controlled to the L level only during the activation period of the word line when the first node transitions from the H level to the L level, and the source electrode of the second additional transistor is The second node is controlled to the L level only during the activation period of the word line when the second node transitions from the H level to the L level (Configuration 1).

  Since both the additional transistors can be formed in the same well as the load transistors of both CMOS inverters, an increase in cell area can be suppressed.

  In addition, among the additional transistors, the source electrode of the additional transistor whose drain electrode is connected to the node transitioning from the H level to the L level is controlled to be at the L level over the activation period of the word line in the transition. Then, the write margin is increased by lowering the potential of the node.

  Furthermore, since the on-current is increased by the current through the additional transistor in which the source electrode of both the additional transistors is set to the H level and the drain electrode is connected to the node of the H level, the static noise margin at the time of reading and in the holding state is reduced. To increase.

  Further, the additional transistor can be controlled by the additional transistor control circuit to secure a write margin and a static noise margin.

  The static semiconductor memory device according to a certain aspect of the present invention is as described above.

  The semiconductor memory device according to still another aspect of the present invention includes first and second driver transistors that are NMOS transistors, first and second load transistors that are PMOS transistors, and first and second accesses. Transistors, the source electrodes of the two driver transistors are respectively connected to the ground, the source electrodes of the two load transistors are respectively connected to a power source, the first driver transistor, the first load transistor, and the first The drain electrodes of the access transistors and the gate electrodes of the second driver transistor and the second load transistor are connected in common at a first node, and the second driver transistor, the second load transistor, and the second load transistor are connected to each other. And a drain electrode of each of the second access transistors, and a gate electrode of the first driver transistor and the first load transistor are connected in common at a second node, and a source electrode of the first access transistor is a first electrode The gate electrode is connected to the first word line, the source electrode of the second access transistor is connected to the second bit line, and the gate electrode is connected to the first word line. A first additional transistor that is a PMOS transistor having a drain electrode connected to the first node and a gate electrode connected to the second node, and a drain electrode A gate electrode connected to the second node and the first node A second additional transistor, which is a PMOS transistor connected to a node, and the source electrode of the first additional transistor is the word line when the first node transitions from the H level to the L level. The source electrode of the second additional transistor is controlled by the word line in the case where the second node transits from the H level to the L level. It is configured to be controlled to L level only during the activation period (Configuration 2).

  A static semiconductor memory device according to a first development mode is a configuration in which the first and second additional transistors are added to a one-port SRAM including six transistors in the configuration described in the configuration 1. (Configuration 1-1).

  A static semiconductor memory device according to a second development form has a configuration in which the first and second additional transistors are added to a dual port SRAM including eight transistors in the configuration described in the configuration 1. (Configuration 1-2).

  A static semiconductor memory device according to a third development form is the same as that of the configuration 2 described above, wherein the drain electrode is connected to the first node, the gate electrode is connected to the second word line, and the source electrode is the first electrode. A third access transistor connected to the third bit line, a drain electrode connected to the second node, a gate electrode connected to the second word line, and a source electrode connected to the fourth bit line The fourth access transistor is provided (Configuration 2-1).

  FIG. 1 is a circuit diagram of an SRAM cell according to the first embodiment of the present invention.

  Referring to FIG. 1, the SRAM cell includes a pair of driver transistors ND1 and ND2 that are NMOS transistors, a pair of load transistors PL1 and PL2 that are PMOS transistors, and a pair of access transistors NA1 and NA2 that are NMOS transistors. Prepare.

  The source electrodes of the driver transistors ND1 and ND2 are each connected to the ground (GND). The source electrodes of the load transistors PL1 and PL2 are each connected to the power supply VDD. The drain electrode of driver transistor ND1 is connected to the drain electrode of load transistor PL1. Hereinafter, this connection point is referred to as “node 1”. The drain electrode of driver transistor ND2 is connected to the drain electrode of load transistor PL2. Hereinafter, this connection point is referred to as “node 2”. The gate electrode of driver transistor ND1 and the gate electrode of load transistor PL1 are both connected to node 2. The gate electrode of driver transistor ND2 and the gate electrode of load transistor PL2 are both connected to node 1. A latch circuit is formed by a CMOS inverter composed of the driver transistor ND1 and the load transistor PL1, and a CMOS inverter composed of the driver transistor ND2 and the load transistor PL2. One of the source and drain electrodes of the access transistor NA1 is connected to the node 1, and the other is connected to the bit line True. One of the source and drain electrodes of the access transistor NA2 is connected to the node 2, and the other is connected to the bit line Bar. The gate electrodes of access transistors NA1 and NA2 are each connected to a word line.

  In the PMOS transistor P1, one of the source and drain electrodes is connected to the node 1, the other is connected to the control signal S1, and the gate electrode is connected to the node 2. In the PMOS transistor P2, one of the source and drain electrodes is connected to the node 2, the other is connected to the control signal S2, and the gate electrode is connected to the node 1.

  The PMOS transistors P1 and P2 and the load transistors PL1 and PL2 can be formed in the same N well.

  The control signals S1 and S2 are generated from the logic of the write enable signal, the column selection signal, the data input signal, and the row selection signal, so that the control required in each of the write, read, and hold operations can be performed.

  When the potential of the node 1 is “H”, the potential of the node 2 is “L”, and when the potential of the node 1 is “L”, the potential of the node 2 is “H”.

  FIG. 2 is a timing chart of the SRAM cell according to the first embodiment of the present invention.

  A case where the potential of the node 1 at which the potential is at the H level is set to the L level will be described with reference to the portion of “0” writing in FIG. When the potential of the node 1 is at the H level, P1 is on and P2 is off. Before the word line becomes H level, the control signal S1 is set to L level, and S2 remains at H level. When the control signal S1 is set to the L level, the potential of the node 1 decreases due to the on-resistance division of P1 and PL1. When the bit line True is left at the L level by the WriteBuffer and the bit line Bar is kept at the H level, the charge of the node 1 flows to the GND through the path from the access transistor NA1 to the WriteBuffer, and the node 1 becomes the L level. .

  The operation of reading the data of the node 1 whose potential is at the L level will be described with reference to the portion “Reading“ 0 ”” in FIG. At this time, P1 is off and P2 is on. First, the bit line True is precharged to H level, then the word line is set to H level, and the control signals S1 and S2 are set to H level, so that the charge on the bit line True is GND via the access transistor NA1 and the driver transistor ND1. And send a signal to the sense amplifier. At this time, the bit line Bar holds the H level.

  The operation in "" 1 "write" in FIG. 2 replaces node 1 and node 2, bit line True and bit line Bar, and control signal S1 and control signal S2 in the above description of "" 0 "write". It is explained as a thing.

  The operation in ““ 1 ”reading” in FIG. 2 is also described as the same replacement in the above description of ““ 0 ”reading”.

  With reference to the “Hold” portion of FIG. 2, the case where the data in the latch unit is held, that is, when neither writing nor reading is performed will be described. At this time, the word line is set to L level and the control signals S1 and S2 are set to H level to hold the data in the latch portion.

  A parallel PMOS in which the drain electrode is connected to the node 1 or 2 whose potential is at the H level by the PMOS transistors P1 and P2 having the source electrode connected to the control signals S1 and S2 at the H level in the reading state and the holding state. As the on-current in the transistors (P1 and PL1 or P2 and PL2) increases, the static noise margin increases.

  At the time of writing, the control signals S1 and S2 are controlled, and the potential of the node 1 or 2 that is at the H level is lowered by the on-resistance division of the series PMOS transistor (P1 and PL1 or P2 and PL2), thereby reducing the write margin. Increase.

  In other words, the static noise margin and the write margin, which are conventionally trade-off relationships, are simultaneously increased by changing the balance of the characteristics of the latch unit between the read time and the hold time and the write time by the control signals S1 and S2. be able to.

  Further, since it is not necessary to perform well isolation that leads to an increase in area, even if two wiring lines for the control signals S1 and S2 are added, an increase in the cell area can be suppressed slightly.

  Further, even when a method of reading without turning off the precharge transistor of the non-selected cell is employed for speeding up the reading operation, the independent control signals S1 and S2 that do not affect the potential of the bit line can be used in the normal operation mode. Similarly, the static noise margin can be improved.

  FIG. 6 is a configuration diagram of a conventional dual-port SRAM capable of reading and writing data from each port having an 8-transistor configuration.

  FIG. 3 is a block diagram of a cell when the present invention is applied to this dual port SRAM.

  In the dual port SRAM, as in the case of the 1 port SRAM (see FIG. 1), the drains and gates of the two PMOS transistors P1 and P2 are connected to different nodes 1 and 2, respectively, and the sources are the control signal S1, Connected to S2. As in the case of the 1-port SRAM, stable operation can be performed by increasing the static noise margin and the write margin during reading and holding.

  When applied to an 8-transistor dual-port SRAM (WR + WR), the area increase rate generated by adding two PMOS transistors P1 and P2 can be reduced as compared to the case of applying to a 1-port SRAM.

  Next, variations of the additional transistor control circuit that controls the above-described additional transistor will be described. In the embodiment described above, the control signals S1 and S2 are generated in addition to the logic in addition to the write enable signal, the column selection signal, and the data input signal. Thus, by adding the row selection signal to the logic, the control signals S1 and S2 can be controlled to the L level only when the first or second node transits from the H level to the L level. .

  However, even if the row selection signal is not added to the logic for controlling the control signals S1 and S2, the same effect as that obtained when the row selection signal is added to the logic can be obtained. In that case, the configuration of the additional transistor control circuit for controlling the control signals S1 and S2 can be simplified, and the additional transistor control circuit can be shared between SRAM cells sharing the bit line.

  FIG. 7 is a block diagram of an entire static semiconductor memory device in which an additional transistor control circuit is shared between SRAM cells sharing a bit line. In FIG. 7, a plurality of word lines are output from the row decoder 1 to the RAM cell array 2. Further, a plurality of bit line pairs including a bit line True and a bit line Bar extend from the “column selector and read / write control circuit 3” to the RAM cell array 2. A plurality of SRAM cells described in the first embodiment are provided in a matrix corresponding to the intersections of the plurality of word lines and the plurality of bit line pairs. In this embodiment, the additional transistor control circuit 4 for controlling the additional transistor is provided in the “column selector and read / write control circuit 3”. Control signals S1 and S2 are output to the RAM cell array 2 in correspondence with a plurality of bit line pairs extending from the “column selector and read / write control circuit 3” (not shown). In the RAM cell array 2, the control signals S1 and S2 may be wired in parallel with the bit line pair.

  FIG. 8 is a circuit diagram of the additional transistor control circuit 4. This additional transistor control circuit is provided in the “column selector and read / write control circuit 3” as described above. The NAND gate 5 receives the write enable signal WE, the data input inversion signal DIB, and the kth column selection signal CSk, and outputs the kth S1 signal S1k.

  Similarly, the NAND gate 6 receives the write enable signal WE, the data input signal DI, and CSk as the kth column selection signal, and outputs S1k as the kth S1 signal. Here, the CSk signal is a signal for selecting the k-th column (k is a natural number of n or less) among n (n is an integer of 2 or more) column selection signals generated by decoding the column address. In the case where there are n pairs of bit lines extending from the “column selector and read / write control circuit 3” to the RAM cell array 2, there are n additional transistor control circuits 4.

  With such a configuration, since the additional transistor control circuit 4 is shared for a plurality of SRAM cells connected to the same bit line pair, the control signals S1, S2 are also applied to the cells that are not directly written. May be controlled to L level. However, since the word line is at the H level only in the cell to which data is written, even if the control signals S1 and S2 are at the L level for the cell to which data is not written, the cell data There will be no problem that will destroy the.

  Next, FIG. 9 shows an example of an additional transistor control circuit of the dual port SRAM. FIG. 9 is a circuit diagram of an additional transistor control circuit that generates the control signal S1k among the control signals S1k and S2k for the SRAM cell arranged in the k-th column among the dual-port SRAM cells arranged in the n-th column. is there. The additional transistor control circuit shown in FIG. 9 includes an AND unit 7 that generates a control signal related to access from port A, an AND unit 8 that generates a control signal related to access from port B, and AND units 7 and 8. It comprises a NOR unit 9 that synthesizes the generated control signal.

  The AND unit 7 receives a write enable signal WEA for the port A, a data input inversion signal DIAB for the port A, and a column selector signal CSkA for selecting the k-th column cell in connection with the access related to the port A. H level is output when data 0 is written to any of the cells in the k-th column.

  The AND unit 8 inputs the write enable signal WEB for the port B, the data input inversion signal DIBB for the port B, and the k-th column selector signal CSkB for the port B, and enters any of the cells in the k-th column from the port B. Output H level when writing data 0.

  The NOR unit 9 synthesizes the signals generated by the AND units 7 and 8 and outputs a low level as the S1k signal when data 0 is written from the port A or B to the k-th column cell. By setting the additional transistor control circuit as described above, an additional transistor control circuit that outputs a control signal to the additional transistor can be realized even in the dual port SRAM.

  In FIG. 9, the AND units 7 and 8 and the NOR unit 9 are configured as an integrated ANDNOR gate, but may be configured as independent gates. For example, in a dual port SRAM, when the “column selector and read / write control circuit” of port A and the “column selector and read / write control circuit” of port B are laid out separately, the AND section 7 is connected to port A. The AND section 8 can be separately arranged in the “column selector and read / write control circuit” of the port B.

1 is a circuit diagram of an SRAM cell according to a first example of the present invention. FIG. 3 is a timing chart of the SRAM cell according to the first exemplary embodiment of the present invention. FIG. 6 is a circuit diagram of an SRAM cell according to a second example of the present invention. It is a circuit diagram of the SRAM cell comprised by the conventional 6 transistors. It is a circuit diagram of a conventional SRAM cell. It is a circuit diagram of the dual port SRAM cell comprised by the conventional 8 transistors. It is a block diagram of the whole static type semiconductor memory device concerning the 3rd example of the present invention. FIG. 6 is a circuit diagram of an additional transistor control circuit according to a third example of the present invention. FIG. 10 is a circuit diagram of an additional transistor control circuit of a dual port SRAM according to a fourth example of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Row decoder 2 RAM cell array 3 Column selector and read / write control circuit 4 Additional transistor control circuit 7, 8 AND part 9 NOR part 11, 12 Driver transistor 13, 14 Load transistor 15, 16 Access transistor 17, 21 Word line 18, 22 Bit line 19 Inverted bit line 23 SRAM cell GND Ground N1 Node 1
N2 node 2
NA1, NA2, NA1_A, NA1_B, NA2_A, NA2_B Access transistor ND1, ND2 Driver transistor P1, P2 PMOS transistor PL1, PL2 Load transistors S1, S2 Control signal

Claims (12)

A first CMOS inverter including a PMOS transistor and an NMOS transistor having drains connected at a first node and gates connected at a second node;
A second CMOS inverter including a PMOS transistor and an NMOS transistor having drains connected at the second node and gates connected at the first node;
A first access transistor having one of a source and a drain connected to the first node and the other connected to a first bit line;
A second access transistor having one of a source and a drain connected to the second node and the other connected to a second bit line;
A first additional transistor having one of a source and a drain connected to the first node and a gate connected to the second node;
A second additional transistor having one of a source and a drain connected to the second node and a gate connected to the first node;
An SRAM cell including:
And an additional transistor control circuit to which the other of the source and drain of the first and second additional transistors is connected.   The additional transistor control circuit receives a write signal to the static semiconductor memory device, a write address signal, and a write data signal, and sends a signal for controlling the first and second additional transistors to the source. 2. The static semiconductor memory device according to claim 1, wherein the static type semiconductor memory device outputs to the other drain. A plurality of bit line pairs each having the first and second bit lines as a pair of bit lines and a plurality of word lines are provided in a matrix,
The SRAM cell is arranged corresponding to each intersection of the plurality of bit line pairs and the plurality of word lines, and the gates of the first and second access transistors of each SRAM cell are connected to the corresponding word lines. And
The additional transistor control circuit is provided for each bit line pair,
When the write signal becomes active and one of the corresponding first bit line and second bit line becomes low level corresponding to the write address signal and the write data signal, the first or second 3. The static semiconductor memory device according to claim 2, wherein, of the two additional transistors, the other of the source and drain of the corresponding additional transistor is set to the low level. A third access transistor having one of a source and a drain connected to the first node and the other connected to a third bit line;
A fourth access transistor having one of a source and a drain connected to the second node and the other connected to a fourth bit line;
Including
The gates of the first and second access transistors are connected to a first word line, and the gates of the third and fourth access transistors are connected to a second word line;
A plurality of pairs of bit lines each including the first to fourth bit lines and a plurality of pairs of word lines each including the first and second word lines as a pair of word lines are provided in a matrix.
The SRAM cells are arranged corresponding to the intersections between each set of bit lines and each word line pair, and the first and second bit lines and the first word line are connected to the first port, and the third port is connected to the third port. , A dual-port static semiconductor memory device in which a fourth bit line and a second word line are connected to a second port,
The additional transistor control circuit is provided for each set of bit lines, the write signal becomes active, and the corresponding first to fourth bit lines correspond to the write address signal and the write data signal. 3. The static semiconductor memory device according to claim 2, wherein when one of the first and second additional transistors becomes low level, the other of the source and drain of one of the corresponding additional transistors is set to low level. 4. . Each access transistor is an NMOS transistor;
5. The static semiconductor memory device according to claim 1, wherein the first and second additional transistors are PMOS transistors. A static semiconductor memory device comprising a latch circuit comprising first and second CMOS inverters,
A PMOS transistor in which the gate electrodes are connected in common and the drain electrodes are connected in common at the first node to the load transistor that is a PMOS transistor constituting the first CMOS inverter. An additional transistor,
The second transistor is a PMOS transistor in which the gate electrodes are connected in common and the drain electrodes are connected in common at the second node with respect to the load transistor that is a PMOS transistor constituting the second CMOS inverter. With additional transistors,
The source electrode of the first additional transistor is configured to be controlled to L level only during an activation period of the word line when the first node transitions from H level to L level,
The source electrode of the second additional transistor is configured to be controlled to the L level only during the activation period of the word line when the second node transitions from the H level to the L level. A feature of a static semiconductor memory device.   7. The static semiconductor memory device according to claim 6, wherein the first and second additional transistors are added to a one-port SRAM including six transistors.   7. The static semiconductor memory device according to claim 6, wherein the first and second additional transistors are added to a dual port SRAM including eight transistors. First and second driver transistors that are NMOS transistors, first and second load transistors that are PMOS transistors, and first and second access transistors, and the source electrodes of both driver transistors are connected to ground, respectively. The source electrodes of the load transistors are connected to a power source, the drain electrodes of the first driver transistor, the first load transistor, and the first access transistor, the second driver transistor, and the second driver transistor, respectively. The gate electrodes of the two load transistors are connected in common at the first node, and are the drain electrodes of the second driver transistor, the second load transistor, and the second access transistor, respectively. In addition, the gate electrodes of the first driver transistor and the first load transistor are commonly connected at a second node, and the source electrode of the first access transistor is connected to the first bit line and the gate electrode. Is connected to the first word line, the source electrode of the second access transistor is connected to the second bit line, and the gate electrode is connected to the first word line.
A first additional transistor that is a PMOS transistor having a drain electrode connected to the first node and a gate electrode connected to the second node;
A second additional transistor that is a PMOS transistor having a drain electrode connected to the second node and a gate electrode connected to the first node;
The source electrode of the first additional transistor is configured to be controlled to an L level only during an activation period of the word line when the first node transitions from an H level to an L level.
The source electrode of the second additional transistor is configured to be controlled to L level only during the activation period of the word line when the second node transitions from H level to L level. A static semiconductor memory device. A third access transistor having a drain electrode connected to the first node, a gate electrode connected to a second word line, and a source electrode connected to a third bit line;
And a fourth access transistor having a drain electrode connected to the second node, a gate electrode connected to the second word line, and a source electrode connected to a fourth bit line. The static semiconductor memory device according to claim 9.   7. The static semiconductor memory device further includes an additional transistor control circuit, and source electrodes of the first and second additional transistors are connected to the additional transistor control circuit. 11. The static semiconductor memory device according to any one of 10 above.   The additional transistor control circuit receives a signal for controlling a write operation to the static semiconductor memory device, a write address signal, and a write data signal, and signals for controlling the first and second additional transistors, respectively. 12. The static semiconductor memory device according to claim 11, wherein the output is output to each of the source electrodes.

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