JP5076741B2 - Electro-optical device, drive circuit for electro-optical device, and electronic apparatus - Google Patents

Description

  The present invention relates to an electro-optical device such as an active matrix liquid crystal device, an electro-optical device driving circuit for driving the electro-optical device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device. For example, the present invention relates to a technical field of a NAND circuit included in a driving circuit of an electro-optical device such as a scanning line driving circuit.

  In this type of electro-optical device, for example, downsizing of a drive circuit in the electro-optical device is achieved for the purpose of reducing the size of the electro-optical device and reducing the pixel pitch. For example, Patent Document 1 describes a NAND circuit having an array in which a pair of NMOS (N-channel Metal Oxide Semiconductor) pull-down transistors and a pair of PMOS (P-Channel Metal Oxide Semiconductor) pull-up transistors are vertically stacked. Has been.

  On the other hand, for the purpose of preventing flicker or the like, a pixel area or a pixel array area (also referred to as an image display area) in which a plurality of pixels are arranged is divided into partial areas such as upper and lower two divisions and upper and lower four divisions. Separately, vertical scanning is performed for each region and the vertical scanning is performed alternately or alternately between the regions. Preferably, the above-described double speed driving is performed for each partial region and the double speed driving is performed alternately between the regions. A scanning method (hereinafter simply referred to as “region scanning” or “region scanning method”), in which scanning is performed by skipping a linear array of pixels across regions, is also proposed by the present applicant. Here, double speed driving is a driving method in which an image signal for one frame is stored in a memory, and the image signal of the same frame is inverted twice and used twice to increase the driving frequency. When the driving frequency is increased, The fact that flicker is invisible to the human eye is used (see Patent Documents 2 and 3).

JP 2006-49914 A JP 2004-177930 A JP-A-2005-227764

  However, according to the background art described above, since the transistors are stacked, there is a technical problem that the distance (ie, height) in the stacking direction becomes large. In particular, for area scanning, it is necessary to provide a plurality of logic circuits each including a plurality of transistors for each scanning line, and within a limited area on the substrate and according to a prescribed scanning line pitch. Therefore, there is a technical problem that it is difficult to create these logic circuits.

  The present invention has been made in view of, for example, the above-described problems. For example, while the scanning line driving circuit is complicated and sophisticated so as to enable area scanning or the like, for example, the scanning line is not accompanied by an increase in height. It is an object of the present invention to provide an electro-optical device, a driving circuit for an electro-optical device, and an electronic apparatus that can reduce the pixel pitch by reducing the pitch.

  In order to solve the above problems, an electro-optical device of the present invention supplies a data signal to a substrate, a plurality of data lines and a plurality of scanning lines that intersect with each other in a pixel region on the substrate, and the plurality of data lines. A data line driving circuit for performing scanning, a scanning line driving circuit for supplying scanning signals to the plurality of scanning lines in a predetermined order, and a plurality of supplying an enable signal for controlling an output period of the scanning signals to the scanning line driving circuit. Enable signal wiring, and the scanning line driving circuit includes a NAND circuit for controlling the output period based on the supplied enable signal for each scanning line, and a plurality of transistors constituting the NAND circuit Among these, at least one of the enable signal wirings is disposed between one transistor and another transistor adjacent to each other.

  According to the electro-optical device of the present invention, a plurality of data lines and a plurality of scanning lines intersect each other in a pixel region on a substrate such as a quartz substrate, and a plurality of pixel electrodes correspond to each of the intersections. Is provided. Here, the “pixel area” according to the present invention does not mean an area of individual pixels, but means an entire area in which a plurality of pixels are arranged in a matrix. It means the area that should be the “display area”.

  The data line driving circuit supplies a data signal to each of the plurality of data lines. The scanning line driving circuit supplies scanning signals to each of the plurality of scanning lines in a predetermined order. The enable signal wiring supplies an enable signal for controlling an output period of the scanning signal to the scanning line driving circuit. The “predetermined order” means that scanning signals are sequentially supplied to or output from a plurality of scanning lines, and the time series of scanning signals necessarily correspond to the physical arrangement of each scanning line. Not limited to. For example, it is not limited to the meaning of line-sequential, and typically, in response to region scanning in which the pixel region is divided into two or more, the scanning signal is skipped for each region and supplied to the scanning lines alternately or alternately. It means to do.

  At the time of driving, an image is displayed by a so-called active matrix system in which a data signal is supplied from the data line driving circuit to each pixel electrode via the data line to the pixel electrode column selected by horizontal scanning by the scanning line driving circuit. .

  The scanning line driving circuit includes a NAND circuit that controls an output period for each scanning line based on the supplied enable signal. Among the plurality of transistors constituting the NAND circuit, at least one enable signal wiring among the plurality of enable signal wirings is disposed between one transistor and another transistor adjacent to each other. That is, at least one enable signal wiring is arranged between one transistor and another transistor.

  According to the research by the inventors of the present application, it is generally necessary to reduce the layout area of the NAND circuit in the scanning line driving circuit as the pixel pitch becomes finer. On the other hand, a technique for reducing the area by vertically stacking transistors constituting the NAND circuit has been proposed, but it has been found that the height of the electro-optical device increases.

  However, in the present invention, the NAND signal is arranged by disposing at least one enable signal wiring between one transistor and another transistor adjacent to each other in the NAND circuit, that is, by inserting the enable signal wiring in the NAND circuit. The layout area of the entire scanning line driving circuit including the circuit is reduced. At this time, if the transistors constituting the NAND circuit are arranged on the same plane and arranged along the direction in which the scanning line extends, an increase in the height of the electro-optical device can be suppressed and scanning can be performed. The distance in the direction intersecting the direction in which the lines extend (that is, the direction in which the data lines extend) can be suppressed, and the pixel pitch can be miniaturized. In particular, in the case of area scanning, a NAND circuit including a plurality of transistors can be formed for each scanning line, that is, in accordance with a prescribed scanning line pitch within a limited area on the substrate. Become.

  In addition, compared with the case where the enable signal wiring is arranged outside the NAND circuit, the distance from the enable signal wiring to the transistor constituting the NAND circuit can be shortened, so that output delay can be prevented. This is very advantageous in practice.

  As described above, according to the present invention, for example, the scanning line pitch can be reduced without increasing the height while the scanning line driving circuit is complicated and sophisticated so as to enable, for example, area scanning. Thus, the pixel pitch can be reduced.

  In one aspect of the electro-optical device of the present invention, the one transistor and the other transistor are arranged along a direction in which the scanning line extends, and the one enable signal wiring is planar on the substrate. As shown in FIG. 5, the data line includes a wiring portion extending along the direction in which the data line extends, and the wiring portion is disposed between the one transistor and the other transistor.

  According to this aspect, the distance in the direction in which the data lines extend can be suppressed, and the pixel pitch can be miniaturized.

  In another aspect of the electro-optical device of the present invention, the scanning line driving circuit supplies scanning signals to the plurality of scanning lines in the order corresponding to the area scanning as the predetermined order.

  According to this aspect, it is possible to realize an electro-optical device that can perform area scanning and display, for example, a high-definition image.

  In another aspect of the electro-optical device of the present invention, the plurality of enable signal lines are arranged between the one transistor and the other transistor.

  According to this aspect, for example, when two enable signal lines are arranged, the odd-numbered scanning lines are controlled by an enable signal supplied via one enable signal line of the two enable signal lines. The even-numbered scanning lines are controlled by an enable signal supplied via the other enable signal wiring.

  In another aspect of the electro-optical device of the invention, the one transistor is a first conductivity type transistor, and the other transistor is a second conductivity type transistor.

  According to this aspect, one transistor is a first conductivity type transistor that is a P-channel transistor, for example, and the other transistor is a second conductivity type transistor that is an N-channel transistor, for example.

  In another aspect of the electro-optical device of the invention, the plurality of transistors are arranged on the same plane.

  According to this aspect, an increase in the height of the electro-optical device can be suppressed, which is very advantageous in practice.

  In order to solve the above problems, the drive circuit for an electro-optical device according to the present invention drives an electro-optical device including a substrate and a plurality of data lines and a plurality of scanning lines that intersect with each other in a pixel region on the substrate. A driving circuit for an electro-optical device, the data line driving circuit supplying a data signal to the plurality of data lines, the scanning line driving circuit supplying a scanning signal to the plurality of scanning lines in a predetermined order, and the scanning line A plurality of enable signal wirings for supplying an enable signal for controlling an output period of the scan signal to the drive circuit, the scan line drive circuit for each scan line based on the supplied enable signal Including a NAND circuit for controlling the output period, and among a plurality of transistors constituting the NAND circuit, between one transistor and another transistor adjacent to each other, One of the enable signal lines are arranged even without.

  According to the drive circuit for an electro-optical device of the present invention, it is possible to drive an electro-optical device that displays an image by, for example, an active matrix method. The electro-optical device driving circuit includes a data line driving circuit that supplies a data signal to each of the plurality of data lines of the electro-optical device, a scanning line driving circuit that supplies a scanning signal to each of the plurality of scanning lines, and the scanning line An enable signal line for supplying an enable signal to the drive circuit.

  The scanning line driving circuit includes a NAND circuit that controls an output period for each scanning line based on the supplied enable signal. Among the plurality of transistors constituting the NAND circuit, at least one enable signal wiring among the plurality of enable signal wirings is disposed between one transistor and another transistor adjacent to each other. As a result, the layout area of the entire scanning line driving circuit including the NAND circuit can be reduced.

  At this time, if the transistors constituting the NAND circuit are arranged on the same plane and arranged along the direction in which the scanning line extends, the height of the electro-optical device including the electro-optical device driving circuit can be increased. In addition to being able to suppress, the distance in the direction intersecting the direction in which the scanning lines extend (that is, the direction in which the data lines extend) can be suppressed, and the pixel pitch can be miniaturized.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  According to the electronic apparatus of the present invention, since the electro-optical device of the present invention described above is provided, a projection display device, a mobile phone, an electronic notebook, in which the pixel pitch is miniaturized while suppressing an increase in height, Various electronic devices such as a word processor, a viewfinder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

  Hereinafter, embodiments of an electro-optical device, a drive circuit for an electro-optical device, and an electronic apparatus according to the present invention will be described with reference to FIGS. 1 to 11. In the present embodiment, as an example of an electro-optical device, a TFT (Thin Film Transistor) active matrix driving type liquid crystal device with a built-in driving circuit is taken as an example.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view of the TFT array substrate as viewed from the side of the counter substrate together with the components formed thereon, and FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. The TFT array substrate 10 is made of a transparent substrate such as a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is made of a transparent substrate such as a quartz substrate or a glass substrate, for example. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are surrounded by an image display region 10a as an example of the “pixel region” according to the present invention. They are bonded to each other by a sealing material 52 provided in a sealing region located in the area.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or an ultraviolet / heat combination type curable resin for bonding the two substrates, and is applied to the TFT array substrate 10 in the manufacturing process, and then irradiated with ultraviolet rays. And cured by heating or the like. In the sealing material 52, a gap material such as glass fiber or glass beads for dispersing the distance (ie, gap) between the TFT array substrate 10 and the counter substrate 20 to a predetermined value is dispersed. Note that the gap material may be arranged in the image display region 10a or a peripheral region located around the image display region 10a in addition to or instead of the material mixed in the seal material 52.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. However, part or all of the frame light shielding film 53 may be provided as a built-in light shielding film on the TFT array substrate 10 side.

  A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. The sampling circuit 7 is provided so as to be covered with the frame light shielding film 53 on the inner side of the seal region along the one side. The scanning line driving circuit 104 is provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side.

  On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20. Further, a lead wiring 90 for electrically connecting the external circuit connection terminal 102 to the data line driving circuit 101, the scanning line driving circuit 104, the vertical conduction terminal 106, and the like is formed.

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which pixel switching TFTs as drive elements, wiring lines such as scanning lines and data lines are formed is formed. Although the detailed structure of this laminated structure is not shown in FIG. 2, pixel electrodes 9a made of a transparent material such as ITO (Indium Tin Oxide) are provided on the laminated structure in a predetermined pattern for each pixel. It is formed in an island shape.

  The pixel electrode 9a is formed in the image display region 10a on the TFT array substrate 10 so as to face a counter electrode 21 described later. On the surface of the TFT array substrate 10 facing the liquid crystal layer 50, that is, on the pixel electrode 9a, an alignment film 16 is formed so as to cover the pixel electrode 9a.

  A light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. For example, the light shielding film 23 is formed in a lattice shape when viewed in plan on the facing surface of the facing substrate 20. In the counter substrate 20, a non-opening area is defined by the light shielding film 23, and an area partitioned by the light shielding film 23 is an opening area that transmits light emitted from, for example, a projector lamp or a direct viewing backlight. The light shielding film 23 may be formed in a stripe shape, and the non-opening region may be defined by the light shielding film 23 and various components such as data lines provided on the TFT array substrate 10 side.

  On the light shielding film 23, a counter electrode 21 made of a transparent material such as ITO is formed so as to face the plurality of pixel electrodes 9a. In order to perform color display in the image display region 10a on the light shielding film 23, a color filter (not shown in FIG. 2) may be formed in a region including a part of the opening region and the non-opening region. An alignment film 22 is formed on the counter electrode 21 on the counter surface of the counter substrate 20.

  In addition to the data line driving circuit 101, the scanning line driving circuit 104, the sampling circuit 7, etc., a plurality of data lines are pre-set at a predetermined voltage level on the TFT array substrate 10 shown in FIGS. A precharge circuit that supplies a charge signal prior to an image signal, an inspection circuit for inspecting the quality, defects, and the like of the liquid crystal device during manufacture or at the time of shipment may be formed.

  Next, the configuration of the data line driving circuit 101 and the scanning line driving circuit 104 for driving the liquid crystal panel 100 will be specifically described with reference to FIG. FIG. 3 is a schematic configuration diagram illustrating a schematic configuration of a main part of the liquid crystal device according to the present embodiment.

  As shown in FIG. 3, the image display area 10a of the TFT array substrate 10 includes a plurality of pixel portions 100c arranged in a matrix, a plurality of scanning lines 100a and a plurality of data lines 100b arranged so as to cross each other. And are formed. Although not shown here, each of the plurality of pixel portions 100c includes a pixel electrode 9a, a TFT for switching control of the pixel electrode 9a, and a storage capacitor for maintaining a voltage applied to the pixel electrode 9a. And is configured.

  The data line driving circuit 101 supplies the input start pulse DX and data transfer clock CLX to the sampling circuit 7 as a sampling circuit driving signal. The sampling circuit 7 samples the input data signal Ds according to the sampling circuit drive signal. As a result, the data signal di (i = 1, 2, 3,..., M) is supplied to the data line 100b of the liquid crystal panel 100.

  Here, the scanning line driving circuit 104 will be described more specifically with reference to FIG. FIG. 4 is a diagram showing a circuit configuration of the scanning line driving circuit 104 according to the present embodiment.

  As shown in FIG. 4, the scan line driver circuit 104 includes a shift register 1041, a plurality of logic circuits (that is, NAND circuits 1042 and 1044, and NOT circuits 1043 and 1045), and enable signal wirings 1046 and 1047. Has been. The shift register 1041 is configured to sequentially output a transfer signal from each stage in accordance with the scan-side transfer clock CLY input to the scan line drive circuit 104, with respect to the start pulse DY input to the scan line drive circuit 104. ing.

  The plurality of logic circuits 1042 to 1045 finally perform the waveform shaping or the like on the transfer signals sequentially output from the shift register 1041, so that the scanning signal Gj (j = 1, 2, 3) is finally output to the scanning line 100 a. ,..., N) are sequentially output.

  Here, in particular, one of the enable signals ENBY1 and ENBY2 is input to the NAND circuit 1044. When the input enable signal ENBY1 or ENBY2 is at a high level, the scanning signal Gj is output to the scanning line 100a. That is, the scanning line 100a is scanned. On the other hand, when the input enable signal ENBY1 or ENBY2 is at a low level, the scanning signal Gj is not output to the scanning line 100a. That is, the scanning line 100a is not scanned. As a result, the scanning line driving circuit 104 can control scanning of the scanning line 100a in accordance with one of the enable signals ENBY1 and ENBY2.

  The NAND circuit 1044 has a function of shaping the transfer signal qk (k = 1, 2, 3,..., N) that has passed through the NAND circuit 1042 and the NOT circuit 1043 based on the enable signal ENBY1 or ENBY2. Yes.

  Next, the circuit configuration of the NAND circuit 1044 will be described with reference to FIG. FIG. 5 is a circuit diagram showing a circuit configuration of the NAND circuit 1044.

  In FIG. 5, the transfer signal qk output from the corresponding stage of the shift register 1041 and passed through the NAND circuit 1042 and the NOT circuit 1043 is supplied to the gate α of the NAND circuit 1044. One of the enable signals ENBY1 and ENBY2 is supplied to the gate β of the NAND circuit 1044.

  Next, a process of generating the scanning signal Gj in the scanning line driving circuit 104 will be described with reference to FIG. FIG. 6 is a timing chart for explaining the process of generating the scanning signal Gj.

  In FIG. 6, a transfer signal (not shown) is sequentially output from the shift register 1041 in the scanning line driving circuit 104 based on the start pulse DY and the scanning-side transfer clock CLY, and the transfer that has passed through the NAND circuit 1042 and the NOT circuit 1043. The signal qk is input to the NAND circuit 1044.

  In the NAND circuit 1044, waveform shaping is performed using one of the enable signals ENBY1 and ENBY2. Thereby, for example, the pulse width of the transfer signal qk is limited to the pulse width of the enable signal ENBY1 or ENBY2, and signals having different output timings are generated. Subsequently, the scan signal Gj is output via the NOT circuit 1045.

  In the liquid crystal device according to the present embodiment, as shown in FIG. 6, the pulses in the enable signals ENBY1 and ENBY2 are two peaks, and one of the two peaks is divided equally into the image display region 10a up and down. The other of the two peaks is used for driving the scanning line in the other divided partial region. That is, the liquid crystal device according to the present embodiment displays an image by the area scanning method. Specifically, for example, when the number of scanning lines is 800, the first to 400th scanning lines are driven using one of the two peaks, and the 401st to 800th scanning lines are used using the other. To drive. Thereby, a high-definition liquid crystal device can be realized.

  Next, a specific configuration of the NAND circuit 1044 will be described with reference to FIGS. 7 is a plan view of the NAND circuit 1044, FIG. 8 is a cross-sectional view taken along the line AA ′ of FIG. 7, FIG. 9 is a cross-sectional view taken along the line BB ′ of FIG. FIG. 8 is a cross-sectional view taken along the line CC ′ of FIG. 7 to 10, the scales of the layers and the members are different from each other in order to make the layers and the members large enough to be recognized on the drawings. Further, in FIG. 8 to FIG. 10, the components on the upper layer side from the later-described interlayer insulating film 43 are not shown.

  In FIG. 7, the NAND circuit 1044 includes transistors 411, 413, 415, and 417 provided on the TFT array substrate 10. In addition, enable signal wirings 1046 and 1047 are arranged between the transistors 415 and 417. Here, the transistors 411, 416 and 417 are P-channel transistors as examples of the “first conductivity type transistor” of the present invention, and the transistors 412, 413, 414 and 415 are “second conductivity type transistors” of the present invention. As an example, an N-channel transistor.

  In FIG. 7, transistors 411, 413, 415, and 417 constitute one NAND circuit, and transistors 411, 412, 414, and 416 constitute another NAND circuit. That is, FIG. 7 shows a NAND circuit corresponding to the nth scanning line and a NAND circuit corresponding to the (n + 1) th scanning line. In the liquid crystal device according to this embodiment, the transistor 411 is shared by two NAND circuits.

  On the TFT array substrate 10, in addition to the transistors 411, 413, 415 and 417, the enable signal wirings 1046 and 1047, various configurations including these are provided in a stacked structure. As shown in FIG. 8, this stacked structure includes, in order from the bottom, a first layer including semiconductor layers 451, 453, 455, and 417 constituting transistors 411, 413, 415, and 417, a wiring 441 including a gate electrode, The second layer including 443 and 445, the enable signal wirings 1046 and 1047, the power supply wirings VDD1, VDD2 and VSS, the third layer including the wirings 433 and 437, and the fourth layer including the wiring 421 are configured. The power supply wirings VDD1 and VDD2 correspond to VDD in FIG.

  A base insulating film 41 is provided between the first layer and the second layer, an interlayer insulating film 42 is provided between the second layer and the third layer, and an interlayer insulating film 43 is provided between the third layer and the fourth layer. This prevents short-circuiting between the elements. Further, in these various insulating films 12, 41, 42 and 43, contact holes and the like for electrically connecting wirings and the like included in each layer are formed.

  Although not shown in FIG. 8, the first layer further includes semiconductor layers 452, 454, and 456, and the second layer further includes wirings 442, 444, and 446. The third layer further includes wirings 431, 432, 434, 435, 436, and 438, and the fourth layer further includes wiring 422. The various wirings included in the third layer have a three-layer structure of, for example, an aluminum layer, a titanium nitride layer, and a plasma nitride film in order from the bottom layer. For example, it has a two-layer structure in which a lower layer is made of aluminum and an upper layer is made of titanium nitride.

  Returning to FIG. 7 again, the wiring 431 is electrically connected to the wiring 441 through the contact hole 431a. The wiring 441 corresponds to the gate α in FIG. The power supply wiring VDD1 is electrically connected to the semiconductor layer 451 through the contact hole 439a. In FIG. 7, for the sake of convenience, a lead line is given to only one contact hole. However, the power supply wiring VDD1 and the semiconductor layer 451 are connected through all three contact holes provided in the vertical direction in FIG. Is connected. The same applies to contact holes 433a, 433b, 434a, 434b, 435a, 435b, 436a, 436b, 437a, 438a, 439b, 439c, 439d and 439e which will be described later.

  The wiring 433 is electrically connected to the semiconductor layer 451 through the contact hole 433a and electrically connected to the semiconductor layer 453 through the contact hole 433b. The wiring 433 is electrically connected to the wiring 421 through the contact hole 421a (see FIG. 8). The wiring 421 is electrically connected to the wiring 437 through the contact hole 421b.

  The wiring 435 is electrically connected to the semiconductor layer 453 through the contact hole 435a and electrically connected to the semiconductor layer 455 through the contact hole 453b. The power supply wiring VSS is electrically connected to the semiconductor layer 455 through the contact hole 439b and electrically connected to the semiconductor layer 454 through the contact hole 439c (see FIG. 9).

  The enable signal wiring 1046 is electrically connected to the wiring 443 through the contact hole 1046a (see FIG. 8). Note that the wiring 443 corresponds to the gate β in FIG. The wiring 437 is electrically connected to the semiconductor layer 457 through the contact hole 437a and electrically connected to the wiring 445 through the contact hole 437b. Note that the wiring 445 corresponds to OUT in FIG. The power supply wiring VDD2 is electrically connected to the semiconductor layer 457 through the contact hole 439d and is also electrically connected to the semiconductor layer 456 through the contact hole 439e (see FIG. 10).

  The wiring 432 is electrically connected to the wiring 442 through the contact hole 432a. The wiring 434 is electrically connected to the semiconductor layer 451 through the contact hole 434a and electrically connected to the semiconductor layer 452 through the contact hole 434b. The wiring 434 is electrically connected to the wiring 422 through the contact hole 422a. The wiring 422 is electrically connected to the wiring 438 through the contact hole 422b.

  The wiring 436 is electrically connected to the semiconductor layer 452 through the contact hole 436a and electrically connected to the semiconductor layer 454 through the contact hole 436b. The enable signal wiring 1047 is electrically connected to the wiring 444 through the contact hole 1047a.

  The wiring 438 is electrically connected to the semiconductor layer 456 through the contact hole 438a and electrically connected to the wiring 446 through the contact hole 438b.

  The distance W1 of the NAND circuit 1044 configured as described above is about 10 μm (micrometer). As a result, it is possible to reduce the pixel pitch. Further, as shown in FIG. 7, since the distance from the contact hole 1046a to the transistor 415 and the distance from the contact hole 1046a to the transistor 417 are almost the same and short, the enable signal input to each of the transistors 415 and 417. The amplitude of ENBY1 can be made substantially the same. Similarly, the amplitude of the enable signal ENBY2 input to each of the transistors 414 and 416 can be made substantially the same.

  On the other hand, in this embodiment, since the transistors 411, 413, 415, and 417 (or the transistors 411, 412, 414, and 416) are arranged along the Y direction, the distance in the Y direction of the scanning line driving circuit 104 becomes long. However, for example, as long as the shift register 1041 in the scanning line driving circuit 104 is arranged in the seal region, the influence on the image display region 10a due to the increase of the distance in the Y direction of the NAND circuit 1044 can be eliminated. It has been found by the inventor's research that even if the shift register 1041 is arranged in the seal region, it does not affect the operation of the liquid crystal device.

<Electronic equipment>
Next, a case where the above-described liquid crystal device is applied to a projector which is an example of an electronic device will be described with reference to FIG. The liquid crystal panel 100 in the above-described liquid crystal device is used as a light valve of a projector. FIG. 11 is a plan view showing a configuration example of the projector.

  As shown in FIG. 11, a projector 1100 includes a lamp unit 1102 made up of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G have the same configuration as that of the above-described liquid crystal device, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit, respectively. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display images by the liquid crystal panels 1110R and 1110B need to be horizontally reversed with respect to the display images by the liquid crystal panel 1110G.

  Since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic device described with reference to FIG. 11, a mobile personal computer, a mobile phone, a liquid crystal television, a viewfinder type or a monitor direct view type video tape recorder, a car navigation device, a pager, and an electronic notebook , Calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), The present invention can also be applied to an organic EL display, a digital micromirror device (DMD), an electrophoresis apparatus, and the like.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification. An optical device, an electro-optical device drive circuit, and an electronic apparatus including the electro-optical device are also included in the technical scope of the present invention.

It is a top view which shows the whole structure of the liquid crystal device which concerns on embodiment of this invention. It is the HH 'sectional view taken on the line of FIG. It is a schematic block diagram which shows schematic structure of the principal part of the liquid crystal device which concerns on embodiment of this invention. It is a figure which shows the circuit structure of the scanning line drive circuit which concerns on embodiment of this invention. 1 is a circuit diagram showing a circuit configuration of a NAND circuit according to an embodiment of the present invention. 4 is a timing chart for explaining a process of generating a scanning signal in the scanning line driving circuit according to the embodiment of the present invention. 1 is a plan view of a NAND circuit according to an embodiment of the present invention. FIG. 8 is a cross-sectional view taken along line AA ′ in FIG. 7. FIG. 8 is a sectional view taken along line BB ′ of FIG. It is CC 'sectional view taken on the line of FIG. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Liquid crystal panel, 100a ... Scan line, 100b ... Data line, 101 ... Data line drive circuit, 104 ... Scan line drive circuit, 411-417 ... Transistor, 1041 ... Shift register, 1042, 1044 ... NAND circuit, 1043, 1045 ... NOT circuit, 1046, 1047 ... Enable signal wiring

Claims (7)

A substrate,
A plurality of data lines and a plurality of scanning lines intersecting with each other in a pixel region on the substrate;
A data line driving circuit for supplying a data signal to the plurality of data lines;
A scanning line driving circuit for supplying scanning signals to the plurality of scanning lines in a predetermined order;
A plurality of enable signal lines for supplying an enable signal for controlling an output period of the scan signal to the scan line driving circuit;
The scanning line driving circuit includes a NAND circuit that controls an output period of the scanning signal based on the enable signal,
Among the plurality of transistors constituting the NAND circuit, at least one of the plurality of enable signal wirings is disposed between one adjacent transistor and another transistor arranged along the extending direction of the scanning line. Enable signal wiring is placed,
The one enable signal wiring includes a wiring portion arranged along the extending direction of the data line when viewed in plan on the substrate, and the wiring portion includes the one transistor and the other transistor. An electro-optical device characterized by being disposed between.   The electro-optical device according to claim 1, wherein the scanning line driving circuit supplies scanning signals to the plurality of scanning lines in an order corresponding to region scanning as the predetermined order.   3. The electro-optical device according to claim 1, wherein the plurality of enable signal wirings are arranged between the one transistor and the other transistor. The one transistor is a first conductivity type transistor;
The electro-optical device according to any one of claims 1 to 3, wherein the other transistor is a second conductivity type transistor.   The electro-optical device according to claim 1, wherein the plurality of transistors are arranged on the same plane. An electro-optical device drive circuit for driving an electro-optical device comprising a substrate and a plurality of data lines and a plurality of scanning lines intersecting each other in a pixel region on the substrate,
A data line driving circuit for supplying a data signal to the plurality of data lines;
A scanning line driving circuit for supplying scanning signals to the plurality of scanning lines in a predetermined order;
A plurality of enable signal lines for supplying an enable signal for controlling an output period of the scan signal to the scan line driving circuit;
The scanning line driving circuit includes a NAND circuit that controls an output period of the scanning signal based on the enable signal,
Among the plurality of transistors constituting the NAND circuit, at least one of the plurality of enable signal wirings is disposed between one adjacent transistor and another transistor arranged along the extending direction of the scanning line. Enable signal wiring is placed,
The one enable signal wiring includes a wiring portion arranged along the extending direction of the data line when viewed in plan on the substrate, and the wiring portion includes the one transistor and the other transistor. A drive circuit for an electro-optical device, which is disposed between the two.   An electronic apparatus comprising the electro-optical device according to claim 1.

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