JP5087103B2 - Fully differential switched capacitor filter circuit and A / D converter - Google Patents

Description

  The present invention relates to a fully differential switched capacitor filter circuit and an A / D converter, and more particularly to a fully differential switched capacitor filter circuit and an A / D converter that perform filtering of an analog input signal.

  Conventionally, a filter circuit for removing a noise component contained in an analog signal or performing a filtering process for converting the frequency characteristic of the analog signal in an integrated circuit such as an IC (Integrated Circuit) or LSI (Large Scale Integrated) is realized. In this case, for example, a switched capacitor filter (SCF) circuit as shown in FIG. 4 has been widely used.

  In the SCF circuit, the resistance required for configuring the filter and the resistance of the capacitor are realized by a combination of the switch and the capacitor, so that the main characteristics such as the cut-off frequency and gain of the filter circuit are represented by the relative values of the capacitors. Can be determined. Therefore, by using such an SCF circuit, it is possible to realize a highly accurate filter circuit in an integrated circuit as compared with a normal R / C filter whose filter characteristics are determined by the absolute values of a resistor and a capacitor. it can.

In particular, even for an analog signal, an SCF circuit used for handling high-quality analog signals such as music is required to have a very low distortion of an output signal and a high S / N.
Therefore, as in the SCF circuit shown in FIG. 4, the circuit configuration is a fully differential circuit, the capacitance C of the sampling capacitors C1a and C1b is increased, and the operating frequency f of the SCF circuit 100 is increased. It has been done.

  When the SCF circuit 100 shown in FIG. 4 is operated at the operating frequency f, if the capacitances of the sampling capacitors C1a and C1b are C, the input impedance of the circuit can be considered equivalent to a resistance of 1 / (C · f). it can. Therefore, for the purpose of obtaining a high S / N ratio, increasing the capacitance C of the sampling capacitors C1a and C1b or increasing the operating frequency f of the SCF circuit 100 reduces the input impedance of the SCF circuit 100. It will be. For this reason, when, for example, a single-end differential conversion circuit is connected as an input circuit to the input side of the SCF circuit 100, it is necessary to connect a single-end differential conversion circuit having a small output impedance. For this reason, it has been difficult to bring out the performance of the SCF circuit sufficiently even with a high-performance SCF circuit.

  Therefore, in the fully differential switched capacitor circuit described in Patent Document 1 below, in order to further improve the S / N ratio of the SCF circuit, a sampling capacitor having a large capacity is used, or the clock frequency is increased. In addition to lowering the noise level of the SCF circuit, the input signal sampling method is improved so that the input signal level to the SCF circuit is equivalently increased.

The configuration of a conventional SCF circuit will be described with reference to FIG. FIG. 5 is a circuit configuration diagram showing the configuration of a fully differential integrator using a conventional SCF circuit.
The SCF circuit 200 illustrated in FIG. 5 is connected to the subsequent stage of the single-ended differential conversion circuit 300 as an example of an input circuit. The single-ended differential conversion circuit 300 includes operational amplifiers AMP2 and AMP3 and resistors R1a, R1b, R2a, and R2b. In order to input the analog input signal Vin to the SCF circuit 200, the single-end differential conversion circuit 300 performs single-end differential conversion on the analog input signal Vin, and a non-inverted signal Vinp having the same phase as the analog input signal Vin. This circuit outputs an inverted signal Vinn that is 180 degrees out of phase with the input signal Vin.

The SCF circuit 200 includes a non-inverted signal input terminal VINp, an inverted signal input terminal VINn, MOS transistors SW1a to SW4a, SW1b to SW4b, sampling capacitors C1a and C1b, an operational amplifier AMP, integration capacitors C2a and C2b, a non-inverted signal output terminal VOUTp, And an inverted signal output terminal VOUTn.
The non-inverted signal input terminal VINp receives the non-inverted input signal Vinp output from the single-ended differential conversion circuit 300.

The inverted signal input terminal VINn receives the inverted input signal Vinn output from the single end differential conversion circuit 300.
The MOS transistors SW1a to SW4a and SW1b to SW4b open and close the circuits according to the signal level of H (HIGH) or L (LOW) of the clock signals φ1 to φ2 output from the clock generation circuit, for example. For example, when the clock signal φ1 changes from the L level to the H level, the corresponding MOS transistors SW1a, SW1b, SW3a, and SW3b change from the open (disconnected) state to the closed (connected) state.

The sampling capacitors C1a and C1b sample charges corresponding to the voltages of the inverting input signal Vinn and the non-inverting analog input signal Vinp.
The operational amplifier AMP is a fully differential operational amplifier that outputs a voltage corresponding to a potential difference between the non-inverting input terminal VINp and the inverting input terminal VINn.
The integration capacitors C2a and C2b are respectively connected between the input terminal and the output terminal of the operational amplifier AMP, receive the charges sampled by the sampling capacitors C1a and C1b, and output a voltage (integral value) corresponding to the received charges. .

The non-inverted signal output terminal VOUTp outputs the non-inverted analog output signal Voutp output from the operational amplifier AMP.
The inverted signal output terminal VOUTn outputs the inverted analog output signal Voutn output from the operational amplifier AMP.
Note that the non-inverting input terminals of the operational amplifiers AMP2 and AMP3 and one ends of the MOS transistors SW3a and SW3b are connected to a reference (common) voltage VCOM. In the SCF circuit 200, regarding the reference voltage VCOM, the voltage VINP of the non-inverted analog input signal Vinp, and the voltage VINN of the inverted analog input signal Vinn,
VIN = VINP = −VINN (1)
(VINP + VINN) / 2 = VCOM (2)
It shall be related.

Next, the circuit operation in the conventional SCF circuit will be described with reference to FIG. FIG. 6 is a time chart showing output signal waveforms of clock signals φ, φ1, and φ2 in a conventional SCF circuit.
For example, the vertical axis of the time chart shown in FIG. 6 indicates clock signals φ, φ1, and φ2 output from the clock generation circuit, and the horizontal axis indicates time.
First, only the circuit operation for the sampling capacitor C1a will be described. The circuit operation for the sampling capacitor C1b will be described later.
In the phase T0, the clock signal φ1 becomes L level, and the MOS transistors SW1a and SW3a are opened. At the same time, the clock signal φ2 becomes H level, and the MOS transistors SW2a and SW4a are closed.

  At this time, the input side terminal of the sampling capacitor C1a is connected to the non-inverted signal input terminal VINp, and the output side terminal of the sampling capacitor C1a is connected to the inverting input terminal of the operational amplifier AMP. The potential difference between the non-inverting input terminal and the inverting input terminal of the operational amplifier AMP is ideally 0 and coincides with the reference voltage VCOM. Therefore, the voltage at the output terminal of the sampling capacitor C1a is always the reference voltage VCOM regardless of the open / closed state of the MOS transistors SW3a and SW4a.

When the phase T0 changes to the phase T1, the clock signal φ1 changes from L level to H level, and the MOS transistors SW1a and SW3a are closed. At the same time, the clock signal φ2 changes from the H level to the L level, and the MOS transistors SW2a and SW4a are opened.
At this time, the voltage at the input side terminal of the sampling capacitor C1a changes from the input voltage VINP to the input voltage VINN, but the potential at the output side terminal of the sampling capacitor C1a remains at the reference voltage VCOM. That is, when the capacitance of the sampling capacitor C1a is C, the operational amplifier AMP2 is compared with the sampling capacitor C1a.
C ・ (VINN−VINP) …… (3)
Is charged.

Then, when it becomes the phase T1 to the phase T2 (= phase T0), the clock signal φ1 again becomes H level to a L level, MOS transistors SW1a, is SW3a in the open state. At the same time, the clock signal φ2 changes from L level to H level, and the MOS transistors SW2a and SW4a are closed. The charge of C · (VINN−VINP) shown in the equation (3) is transferred from the sampling capacitor C1a to the integration capacitor C2a.

Similarly, the circuit operation for the sampling capacitor C1b will be described.
When the phase T1 is changed to the phase T2 (= phase T0), the MOS transistors SW1b and SW3b are opened, and the MOS transistors SW2b and SW4b are closed. At this time, the potential of the input side terminal of the sampling capacitor C1b changes from the input voltage VINP to the input voltage VINN. That is, when the capacitance of the integrating capacitor C1b is C, the operational amplifier AMP2 is compared with the sampling capacitor C1b.
C ・ (VINN−VINP) …… (4)
Is charged.

At this time, the charge of the charge amount = C · (VINP−VINN) is transferred from the sampling capacitor C1b to the integration capacitor C2b.
As described above, the number of times charges are transferred from the capacitors C1a and C1b to the capacitors C2a and C2b is one for each period (clock). Therefore, if the frequency of the clock signal φ is f, integration is performed for one second. The amount of charge transferred to the capacitor C2a is
C · (VINN−VINP) · f = − (2 · VIN) · C · f (5)
It is. Similarly, the amount of charge transferred to the integrating capacitor C2b is
C · (VINP−VINN) · f = (2 · VIN) · C · f (6)
It is.

In the SCF circuit 100 controlled by the normal sampling operation method shown in FIG. 4, the amount of charge transferred to the integration capacitor C2a per second is
-(Vin) · C · f (7)
It is. Similarly, the amount of charge transferred to the integrating capacitor C2b is
(Vin) ・ C ・ f ...... (8)
It is.
That is, the SCF circuit 200 equivalently doubles the input analog input signal level by the above-described sampling operation method as compared to the SCF circuit 100 of the normal sampling method shown in FIG. The S / N ratio was improved. Since the SCF circuit 200 equivalently doubles the input analog input signal level as compared with the SCF circuit 100 of the normal sampling method shown in FIG. 4, the amount of charge that can be transferred to the integration capacitor is also increased. It has doubled.

JP 2008-79129 A

On the other hand, since the operational amplifier AMP2 charges the capacitors C1a and C1b once for each cycle (clock), the charge charged by the operational amplifier AMP2 in one cycle is C · (VINN−VINP).・ 2 ・ f = − (2 ・ VIN) ・ C ・ (2 ・ f)
...... (9)
The input impedance of the SCF circuit 200 seen from the operational amplifier AMP2 side is
1 / (4 · C · f) (10)
It becomes. On the other hand, the input impedance of the SCF circuit 100 of the normal sampling method shown in FIG.
1 / (C · f) (11)
It becomes. Therefore, the input impedance of the SCF circuit 200 shown in Expression (10) is ¼ of the input impedance of the SCF circuit 100 shown in Expression (11).

In other words, in the SCF circuit 200 described above, the input signal voltage is equivalently doubled compared to the SCF circuit 100 shown in FIG. 4 to transfer from the sampling capacitors C1a and C1b to the integrating capacitors C2a and C2b. Although the S / N ratio is improved by doubling the amount of charge generated, the input impedance is reduced to ¼. For this reason, since it is required to use an input circuit having a small output impedance, it has been difficult to sufficiently bring out the original performance of the SCF circuit.
In view of the above problems, an object of the present invention is to provide a fully differential switched capacitor filter circuit and an A / D converter that can obtain an output signal with high input impedance and low noise and distortion. .

In order to achieve the above object, a fully differential switched capacitor filter circuit and an A / D converter according to the present invention are configured as follows.
A first fully differential switched capacitor filter circuit according to the present invention is a fully differential switched capacitor filter circuit that performs filtering processing of an analog signal, and is a first signal input terminal that inputs the first analog signal. When samples a second signal input terminal, the first or second signal input from the input terminal a first or charges corresponding to the voltage of the second analog signal to be input to the second analog signal a first sampling capacitor, a second sampling capacitor for sampling the charge corresponding to the voltage of the first or second said input from the signal input terminal of the first or second analog signal, an inverting input terminal and and fully differential operational amplifier having a non-inverting input terminal, between the non-inverting input terminal and the inverting output terminal of the fully differential operational amplifier A first feedback circuit connected, said second feedback circuit connected between the inverting input terminal and the non-inverting output terminal of the fully differential operational amplifier, the input terminal of the first sampling capacitor the A first connection state in which the input terminal of the second sampling capacitor is connected to the second signal input terminal and the input terminal of the first sampling capacitor is connected to the first signal input terminal; First switching means for switching between a second connection state connected to the second signal input terminal and an input terminal of the second sampling capacitor connected to the first signal input terminal; and A third connection state in which an output terminal of the second sampling capacitor is connected to a reference voltage; and an output terminal of the first sampling capacitor is connected to the counter of the fully differential operational amplifier. A fourth connection state in which the output terminal of the second sampling capacitor is connected to the non-inverting input terminal of the fully differential operational amplifier; and the output terminal of the first sampling capacitor is connected to the input terminal. A second switch for switching between a fifth connection state connected to the non-inverting input terminal of the differential operational amplifier and an output terminal of the second sampling capacitor connected to the inverting input terminal of the fully differential operational amplifier; and means, and a switching control means for controlling each switching of said first and second switching means, said switching control means, in a first phase, and the first and third connection state, the In the second phase immediately after the first phase, the second and fourth connection states are established, and in the third phase immediately after the second phase. The first and second switching means are set to the second and third connection states, and in the fourth phase immediately after the third phase, the first and fifth connection states are set. and controls switching respectively.

  According to the above-described fully differential switched capacitor filter circuit, the first and second switching means can be connected to perform the following operations in the first to fourth phases. First, in the first phase, the charge corresponding to the voltage of the first input signal is sampled in the first sampling capacitor, and the charge corresponding to the voltage of the second input signal is sampled in the second sampling capacitor. In the second phase, the charge corresponding to the differential voltage between the first input signal and the second input signal among the charges sampled in each sampling capacitor is transferred to one feedback circuit. Further, the charge corresponding to the differential voltage between the second input signal and the first input signal is transferred to the other feedback circuit. In the third phase, the voltages at the non-inverting input terminal and the inverting input terminal of the operational amplifier are in agreement with the reference voltage. Therefore, by switching the connection, the charge does not move to each capacitor, and the charge is not charged and transferred to the capacitor in this phase. In the fourth phase, the charge corresponding to the differential voltage between the second input signal and the first input signal among the charges sampled in each sampling capacitor is transferred to the other feedback circuit. In addition, the charge corresponding to the differential voltage between the first input signal and the second input signal is transferred to one feedback circuit.

  That is, the amount of charge that the fully differential operational amplifier charges the sampling capacitor in the second phase and the fourth phase around two cycles of the clock frequency for performing a series of operations from the first phase to the fourth phase, That is, the amount of charge transferred from the sampling capacitor to the feedback circuit is the same, but the input impedance of the fully differential switched capacitor filter circuit is doubled by setting the number of times of charging once per cycle. Is possible.

A second fully differential switched capacitor filter circuit according to the present invention is a fully differential switched capacitor filter circuit that performs filtering processing of an analog signal, and is a first signal input terminal that inputs a first analog signal. A second signal input terminal for inputting a second analog signal, and a charge corresponding to the voltage of the first or second analog signal input from the first or second signal input terminal. A first sampling capacitor; a second sampling capacitor that samples a charge corresponding to a voltage of the first or second analog signal input from the first or second signal input terminal; an inverting input terminal; A fully differential operational amplifier having a non-inverting input terminal and between the non-inverting input terminal and the inverting output terminal of the fully differential operational amplifier A first feedback circuit connected; a second feedback circuit connected between the inverting input terminal and a non-inverting output terminal of the fully differential operational amplifier; and an input terminal of the first sampling capacitor comprising: A first connection state in which the input terminal of the second sampling capacitor is connected to the second signal input terminal and the input terminal of the first sampling capacitor is connected to the first signal input terminal; And a second connection state in which the input terminal of the second sampling capacitor is connected to the first signal input terminal, and the input terminals of the first and second sampling capacitors are First switching means for switching between a non-connected state not connected to any of the first and second signal input terminals, and the first and second sampling capacitors. A third connection state in which the output terminal of the first sampling capacitor is connected to the inverting input terminal of the fully-differential operational amplifier and the output terminal of the second sampling capacitor. Is connected to the non-inverting input terminal of the fully-differential operational amplifier, and the output terminal of the first sampling capacitor is connected to the non-inverting input terminal of the fully-differential operational amplifier and the first Second switching means for switching between a fifth connection state in which an output terminal of the second sampling capacitor is connected to the inverting input terminal of the fully differential operational amplifier, an input terminal of the first sampling capacitor, A connection state in which the input terminal of the second sampling capacitor has the same potential; and an input terminal of the first sampling capacitor; , A third switching means for switching a state in which the input terminal of the second sampling capacitor is not connected, and a switching control means for controlling switching of the first, second and third switching means, respectively. The switching control means sets the first and third connection states in the first phase, and the second phase immediately after the first phase includes a first half phase and a second half phase . in first half phase of the two phases, the non-connected state and the fourth connection state not connected to any of said first and second said input terminal of the sampling capacitor of the first and second signal input terminals with the, by said third switching means, an input terminal of the input terminal of the first sampling capacitor and the second sampling capacitor is the same Position and so as to connect with each other, in the second half of the phase of the second phase, the second and with the fourth connection state, by the third switching means, the input terminal of the first sampling capacitor And the input terminal of the second sampling capacitor are not connected to each other, and in the third phase immediately after the second phase, the second and third connection states are set, and immediately after the third phase. the fourth phase comprises a first half of the phase and the late phase, the first in the fourth first half phase of phase, the first and second input terminals the first and second signal inputs of the sampling capacitor both When the disconnected state and the fifth connection state not connected to any terminal, by said third switching means, the first sample Connect manner to each other and an input terminal of the input terminal of the ring capacitor second sampling capacitor have the same potential, in the second half of the phase of the fourth phase, with the connection state of the first and fifth , Switching of the first, second and third switching means so that the input terminal of the first sampling capacitor and the input terminal of the second sampling capacitor are not connected to each other by the third switching means. Each of these is controlled.
According to the above fully differential switched capacitor filter circuit, the sampling capacitors can be connected to each other using the third switching means.

The third fully differential switched capacitor filter circuit according to the present invention is characterized in that the first and second feedback circuits are composed of only a capacitor or a switch and a capacitor.
That is, according to the fully differential switched capacitor filter circuit described above, the input impedance of the fully differential switched capacitor filter circuit is doubled even when, for example, a low-pass filter, a high-pass filter, an all-pass filter or an integrating circuit is configured. It is possible to configure as it is.

An A / D converter according to the present invention converts any one of the first to third fully differential switched capacitor filter circuits and a single-ended analog signal into a differential analog signal, and the differential analog signal And a single-ended differential conversion circuit that outputs the signal to the fully differential switched capacitor filter circuit, and an A / D conversion circuit that converts the analog signal filtered by the fully differential switched capacitor filter circuit into a digital signal. It is characterized by that.
According to the A / D converter of the present invention, since it is configured to include the above-described fully differential switched capacitor filter circuit, there is little noise and distortion without reducing the output impedance of the input circuit. An output signal can be obtained.

According to the fully-differential switched capacitor filter (SCF) circuit of the present invention, an output signal with less noise and distortion can be obtained by fully exhibiting the original performance of the SCF circuit without reducing the output impedance of the input circuit. Can be obtained.
Further, the input impedance of the SCF circuit can be increased without changing the amount of charge transferred from the sampling capacitor to the integration capacitor without greatly changing the configuration of the SCF circuit.
In addition, according to the A / D converter of the present invention, the analog signal filtered using the above SCF circuit is input to the A / D conversion circuit, so that the A / D conversion circuit performs signal processing with high accuracy. It can be carried out.

It is a block diagram which shows the structure of the A / D converter comprised by applying the fully differential switched capacitor circuit based on this invention. 1 is a circuit diagram showing a circuit configuration of an SCF circuit according to a first embodiment of the present invention. 4 is a time chart showing output signal waveforms of clock signals φ, φ1 to φ5 generated by the clock generation circuit of the SCF circuit according to the first embodiment of the present invention. It is a circuit block diagram which shows the structure of the SCF circuit of a normal sampling method. It is a circuit block diagram which shows the structure of the fully differential integrator by the conventional SCF circuit. 10 is a time chart showing output signal waveforms of clock signals φ, φ1 to φ4 in a conventional SCF circuit. It is a circuit diagram which shows the circuit structure of the SCF circuit which concerns on 2nd Embodiment of this invention. It is a time chart which shows the output signal waveform of clock signal (phi) and (phi) 1-phi6 produced | generated with the clock generation circuit of the SCF circuit which concerns on 2nd Embodiment of this invention.

DESCRIPTION OF EMBODIMENTS Preferred embodiments (examples) of the present invention will be described below with reference to the accompanying drawings.
First, with reference to FIG. 1, the configuration of an A / D converter will be described as an example of a device configured by applying a fully differential switched capacitor filter (SCF) circuit according to the present invention. FIG. 1 is a block diagram showing a configuration of an A / D converter configured by applying a fully differential switched capacitor circuit according to the present invention.
The A / D converter 10 shown in FIG. 1 is connected to the subsequent stage of the single-ended differential conversion circuit 300, similarly to the SCF circuit 200 described in the related art. As described above, the single-ended differential conversion circuit 300 performs the single-end differential conversion on the analog input signal Vin before inputting the analog input signal Vin to the A / D converter 10, and has the same phase as the analog input signal Vin. This circuit outputs a non-inverted input signal Vinp and an inverted input signal Vinn that is 180 degrees out of phase with the analog input signal Vin.

The A / D converter 10 includes a fully differential switched capacitor filter circuit 11a, a clock generation circuit 11b, and an A / D conversion circuit 11c.
The SCF circuit 11a is a circuit that performs a filtering process that removes a noise component included in the input analog input signal Vin or converts the frequency characteristics of the analog input signal Vin. This is a circuit corresponding to the SCF circuit 200 described in the prior art.
The clock generation circuit 11b generates a clock signal φ and, based on the clock signal φ, generates clock signals φ1 to φ5 that are control signals for causing a later-described MOS transistor of the SCF circuit 11a to function as a switch.

The A / D conversion circuit 11c receives the non-inverted output signal Vinp and the inverted output signal Vinn filtered in the SCF circuit 11a, and converts the non-inverted output signal Vinp and the inverted output signal Vinn, which are analog signals, into a digital signal Vout. Then, the converted digital signal Vout is output.
In the present embodiment, the single-end differential conversion circuit 300 is described as a processing unit for differentially converting a single-end analog signal. However, the A / D converter 10 for impedance conversion, level shift, amplification, and the like is used. A circuit for processing a signal optimal for the characteristics may be configured together with the single-ended differential conversion circuit 300.

(First embodiment)
Next, the circuit configuration of the SCF circuit according to the first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a circuit diagram showing a circuit configuration of the SCF circuit according to the first embodiment of the present invention.
The SCF circuit 11a shown in FIG. 2 includes substantially the same parts as the SCF circuit 200 shown in FIG. 5, but the SCF circuit 11a further includes MOS transistors SW5a and SW5b. It is different in point. The same elements as those of the SCF circuit 200 shown in FIG. 5 are denoted by the same reference numerals, and description of each part thereof is omitted.
The MOS transistors SW5a and SW5b function as switches that open and close the circuit by the clock signal φ5 output from the clock generation circuit 11b, similarly to the MOS transistors SW1a to SW4a and SW1b to SW4b.

Next, the circuit operation in the SCF circuit of the first embodiment will be described with reference to FIG. FIG. 3 is a time chart showing output signal waveforms of the clock signals φ, φ1 to φ5 generated by the clock generation circuit of the SCF circuit according to the first embodiment of the present invention.
The vertical axis of the time chart shown in FIG. 3 indicates clock signals φ and φ1 to φ5 output from the clock generation circuit 11b, and the horizontal axis indicates time.
Although the conventional SCF circuit 200 performs a series of operations during one cycle of the clock signal φ, the SCF circuit 11a according to the present invention performs a series of operations during two cycles of the clock signal φ.

First, the operation corresponding to the sampling capacitor C1a will be described.
In the phase T1 (sampling phase), the clock signals φ1 and φ3 become H (HIGH) level, and the MOS transistors SW1a and SW3a are closed. Further, since the other clock signals are at the L (LOW) level, the other MOS transistors are opened. Then, the sampling capacitor C1a samples the charge corresponding to the voltage VINN of the input signal Vinn.
Next, when the phase T1 changes to the phase T2 (transfer phase), the clock signals φ1 and φ3 change from the H level to the L level, and the MOS transistors SW1a and SW3a change from the closed state to the open state. Further, the clock signals φ2 and φ4 change from the L level to the H level, and the MOS transistors SW2a and SW4a change from the open state to the closed state. At this time,
C ・ (VINN−VINP) …… (101)
Are transferred to the integrating capacitor C2a.

Next, when the phase T2 is changed to the phase T3, the clock signal φ4 is changed from the H level to the L level, and the MOS transistor SW4a is changed from the closed state to the open state. Further, the clock signal φ3 changes from the L level to the H level, and the MOS transistor SW3a changes from the open state to the closed state. The other switch states remain the same.
At this time, the sampling capacitor C1a is connected between the non-inverted signal input terminal VINp and the reference voltage VCOM. However, it is assumed that the voltage at the inverting input terminal of the operational amplifier AMP matches the reference voltage VCOM. For this reason, charge does not move to the sampling capacitor. That is, the operational amplifier AMP2 does not charge the sampling capacitor C1a, and the charge of the sampling capacitor C1a is not transferred to the integration capacitors C2a and C2b.

Next, when the phase T3 changes to the phase T4 (phase T0 (transfer phase)), the clock signals φ2 and φ3 change from the H level to the L level, and the MOS transistors SW2a and SW3a change from the closed state to the open state. Further, the clock signals φ1 and φ5 change from the L level to the H level, and the MOS transistors SW1a and SW5a change from the open state to the closed state. At this time,
C ・ (VINP-VINN) ...... (102)
Are transferred to the integrating capacitor C2b.

Similarly, the operation corresponding to the sampling capacitor C1b will be described.
In the phase T1 (sampling phase), the clock signals φ1 and φ3 become H level, and the MOS transistors SW1b and SW3b are closed. Since the other clock signals are at the L level, the other MOS transistors are in an open state. Then, the sampling capacitor C1b samples the charge corresponding to the voltage VINP of the input signal Vinp.

Next, when the phase T1 changes to the phase T2 (transfer phase), the clock signals φ1 and φ3 change from the H level to the L level, and the MOS transistors SW1b and SW3b change from the closed state to the open state. Further, the clock signals φ2 and φ4 change from the L level to the H level, and the MOS transistors SW2b and SW4b change from the open state to the closed state. At this time,
C ・ (VINP-VINN) …… (103)
Are transferred to the integrating capacitor C2b.

Next, when the phase T2 changes to the phase T3, the clock signal φ4 changes from the H level to the L level, and the MOS transistor SW4b changes from the closed state to the open state. Further, the clock signal φ3 changes from the L level to the H level, and the MOS transistor SW3b changes from the open state to the closed state. The other switch states remain the same.
At this time, the sampling capacitor C1b is connected between the inverted signal input terminal VINn and the reference voltage VCOM. However, it is assumed that the voltage at the non-inverting input terminal of the operational amplifier AMP matches the reference voltage VCOM. For this reason, charge does not move to the sampling capacitor. That is, the operational amplifier AMP2 does not charge the sampling capacitor C1b, and the charge of the sampling capacitor C1b is not transferred to the integration capacitors C2a and C2b.

Next, when the phase T3 changes to the phase T4 (phase T0 (transfer phase)), the clock signals φ2 and φ3 change from the H level to the L level, and the MOS transistors SW2b and SW3b change from the closed state to the open state. Further, the clock signals φ1 and φ5 change from the L level to the H level, and the MOS transistors SW1b and SW5b change from the open state to the closed state. At this time,
C ・ (VINN−VINP) …… (104)
Are transferred to the integrating capacitor C2a.

The operation for the sampling capacitor C1a described above and the operation for the sampling capacitor C1b will be summarized. First, the amount of charge received by the integrating capacitor C2a is the sum of the equations (101) and (104).
C. (VIIN-VIIP) + C. (VIIN-VIIP) = 2.C. (VIIN-VIIP) (105)
It becomes. In addition, the amount of charge received by the integrating capacitor C2b is the sum of the equations (102) and (103).
C. (VIIP-VIIN) + C. (VIIP-VIIN) = 2.C. (VIIP-VIIN) (106)
It becomes. Therefore, if the frequency of the clock signal φ is f, the amount of charge transferred to the integrating capacitors C2a and C2b per second is
-2 ・ VIN ・ C ・ f (107)
2 ・ VIN ・ C ・ f ...... (108)
It becomes. The amount of charge is the same as the amount of charge transferred to the integrating capacitors C1b and C2b in the conventional SCF circuit 200 shown in equations (5) and (6).

  On the other hand, the operational amplifier AMP2 charges the sampling capacitors C1a and C1b only twice when the phase T1 shifts to the phase T2 (transfer phase) and when the phase T3 shifts to the phase T4 (transfer phase). It is. On the other hand, in the conventional SCF circuit 200, the operational amplifier AMP2 is charged twice in one cycle of the clock frequency. Therefore, in the SCF circuit 11a of the present embodiment, the number of times the operational amplifier AMP2 charges the capacitors C1a and C2a is half (one time) per cycle as compared with the conventional SCF circuit 200.

Therefore, in the SCF circuit 11a, when compared with the conventional SCF circuit 200, the operational amplifier AMP2 of the single-ended differential conversion circuit 300 connected to the preceding stage is half of a series of operation periods (two cycles of the clock frequency). This means that the same amount of charge is transferred to the integrating capacitor at the number of times of charging, that is, half the amount of charged charge. That is, the input impedance of the SCF circuit 11a can be doubled while keeping the same amount of charge transferred from the sampling capacitors C1a and C1b to the integrating capacitors C2a and C2b.
For this reason, it is not necessary to reduce the output impedance of the input circuit connected to the input side of the SCF circuit, so that an output signal with less noise and distortion can be obtained with the original performance of the SCF circuit. Furthermore, since the analog signal filtered with high accuracy by the SCF circuit according to the present embodiment is input to the A / D conversion circuit connected to the output side of the SCF circuit, the A / D conversion circuit also has high accuracy. Signal processing can be performed.

(Second Embodiment)
Next, a circuit configuration of the SCF circuit according to the second embodiment of the present invention will be described with reference to FIG. FIG. 7 is a circuit diagram showing a circuit configuration of an SCF circuit according to the second embodiment of the present invention.
The SCF circuit 21a shown in FIG. 7 has the same elements as the SCF circuit 11a shown in FIG. 2, but the SCF circuit 21a is further connected between the MOS transistor SW1a and the sampling capacitor C1a. The MOS transistor SW6 is connected between this node and a node between the MOS transistor SW1b and the sampling capacitor C1b.

  The MOS transistor SW6 functions as a switch for opening and closing the circuit by the clock signal φ6 output from the clock generation circuit 11b, similarly to the MOS transistors SW1a to SW5a and SW1b to SW5b described above. That is, in the SCF circuit 21a according to the second embodiment, the MOS transistor SW6 is used to connect the sampling capacitors C1a and C1b to each other.

Next, the circuit operation in the SCF circuit of the second embodiment will be described with reference to FIG. FIG. 8 is a time chart showing output signal waveforms of the clock signals φ, φ1 to φ6 generated by the clock generation circuit of the SCF circuit according to the second embodiment of the present invention.
The vertical axis of the time chart shown in FIG. 8 indicates clock signals φ and φ1 to φ6 output from the clock generation circuit 11b, and the horizontal axis indicates time.
Since the clock signal φ6 necessary for the operation of the SCF circuit 21a is added, as shown in FIG. 8, the phase T0 that is the transfer phase is divided into two phases T0a and T0b, and the phase T2 that is also the transfer phase is The phase T2a and the phase T2b are divided into two. The phases T1 and T3 are not divided. Note that the phases T0a and T2a are the transfer phase a, and the phases T0b and T2b are the transfer phase b.

The SCF circuit 21a does not cause the clock signals φ1 and φ2 to rise from the L level to the H level at the beginning of the phases T0a and T2a, but from the L level at the beginning of the phases T0b and T2b later than the SCF circuit 11a. Get up to level. In the SCF circuit 21a, the clock signal φ6 is at the H level only during the phases T0a and T2a, and is at the L level in all other phases.
When the phase T1 (sampling phase) is reached, the MOS transistors SW2a, SW2b, SW4a, SW4b, SW5a, SW5b, SW6 are opened, and the MOS transistors SW1a, SW1b. SW3a and SW3b are closed. The other switch states remain the same. Then, the charge corresponding to the voltage VINN of the input signal Vinn is sampled in the sampling capacitor C1a, and the charge corresponding to the voltage VINP of the input signal Vinp is sampled in the sampling capacitor C1b.

When the phase T1 is changed to the phase T2a (transfer phase a), the MOS transistors SW1a, SW1b, SW3a, SW3b are opened, and the MOS transistors SW4a, SW4b, SW6 are closed. The other switch states remain the same. Then, the sampling capacitors C1a and C1b are connected to each other via the MOS transistor SW6 and charge and discharge each other. Thereby, the voltage on the input terminal side of the sampling capacitors C1a and C1b is
(VINN + VINP) / 2 (201)
It becomes.

Next, when the phase T2a changes to the phase T2b (transfer phase b), the MOS transistor SW6 is opened and the MOS transistors SW2a and SW2b are closed. The other switch states remain the same.
Thereby, the voltage on the input terminal side of the sampling capacitor C1a is
VINP (202)
It is. The voltage on the input terminal side of the sampling capacitor C1b is
VINN (203)
It is.

As described above, in the phase T2 of the SCF circuit 11a according to the first embodiment, the voltage on the input terminal side of the sampling capacitor C1a is
VINP (204)
It is. The voltage on the input terminal side of the sampling capacitor C1b is
VINN (205)
It is.
As a result, the voltage on the input terminal side of the sampling capacitors C1a and C1b becomes the same as the voltage expressed by the above-described equations (202) and (203).

Next, when the phase T2b is changed to the phase T3, the MOS transistors SW4a and SW4b are opened, and the MOS transistors SW3a and SW3b are closed. The other switch states remain the same. At this time, it is assumed that the voltage at the non-inverting input terminal and the inverting input terminal of the operational amplifier AMP matches the reference voltage VCOM. For this reason, there is no charge transfer.
When the phase T3 is changed to the phase T4a (phase T0a (transfer phase a)), the MOS transistors SW2a, SW2b, SW3a, SW3b are opened, and the MOS transistors SW5a, SW5b, SW6 are closed. Then, the sampling capacitors C1a and C1b are connected to each other via the MOS transistor SW6.
Thereby, the voltage on the input terminal side of the sampling capacitors C1a and C1b becomes the same as the voltage represented by the above-described equation (201).

When the phase T4a changes to the phase T4b (transfer phase b), the MOS transistor SW6 is opened and the MOS transistors SW1a and SW1b are closed. The other switch states remain the same.
Thereby, the voltage on the input terminal side of the sampling capacitor C1a is
VINN (206)
It is. The voltage on the input terminal side of the sampling capacitor C1b is
VINP (207)
It is.
As described above, in the phase T4 of the SCF circuit 11a according to the first embodiment, the voltage on the input terminal side of the sampling capacitor C1a is
VINN (208)
It is. The voltage on the input terminal side of the sampling capacitor C1b is
VINP (209)
It is.

As a result, the voltage on the input terminal side of the sampling capacitors C1a and C1b becomes the same as the voltage expressed by the above-described equations (206) and (207).
That is, in phases T0b and T2b (transfer phase b), the voltages on the input terminal side of the sampling capacitors C1a and C1b of the SCF circuit 21a according to the second embodiment are the phases T0 and T2 of the SCF circuit 11a according to the first embodiment. Is the same as the voltage on the input terminal side of the sampling capacitors C1a and C1b. Accordingly, the charges transferred from the sampling capacitors C1a and C1b to the integrating capacitors C2a and C2b are the same in the SCF circuit 11a according to the first embodiment and the SCF circuit 21a according to the second embodiment.

  On the other hand, when considering the charge required for the operational amplifier AMP3 to charge the sampling capacitor C1a, when the SCF circuit 11a according to the first embodiment shifts from the phase T1 to the phase T2, the input terminal side of the sampling capacitor C1a Is changed from VINN to VINP by being charged by the operational amplifier AMP3. However, in the SCF circuit 21a according to the second embodiment, in the transition from the phase T1 to the phase T2a, the voltage on the input terminal side of the sampling capacitor C1a is changed from VINN due to mutual charge / discharge of the sampling capacitor C1a and the sampling capacitor C1b. The voltage is changed to (VINN + VINP) / 2, and when the phase T2a is shifted to the phase T2b, the voltage on the input terminal side of the sampling capacitor C1a is changed from (VINN + VINP) / 2 to VINP by being charged by the operational amplifier AMP3.

For this reason, in the SCF circuit 21a according to the second embodiment, the charge required for the operational amplifier AMP3 to charge the sampling capacitor C1a is equal to the charge required for the operational amplifier AMP3 to charge the sampling capacitor C1a in the SCF circuit 11a according to the first embodiment. It becomes 1/2 of the charge required for.
That is, by using the MOS transistor SW6 as described above, the sampling capacitors C1a and C1b can be connected to each other, and the transfer phase is divided into two, whereby the sampling capacitors C1a and C1b are integrated with the integration capacitors C2a, The input impedance of the SCF circuit 21a can be further doubled the input impedance of the SCF circuit 11a according to the first embodiment while keeping the same amount of charge transferred to C2b.

  In the SCF circuit 21a according to the second embodiment, only one MOS transistor SW6 is used to connect the sampling capacitors C1a and C1b to each other. However, for example, two MOS transistors SW6 are connected in series instead of the MOS transistor SW6. A MOS transistor can also be used. Even when a voltage of (VINN + VINP) / 2 is applied to the connection point of the two MOS transistors, the same effect as described above can be obtained.

(Modification)
The configuration of the SCF circuit using the differential integration circuit described in the above embodiment, the elements constituting the circuit, the phase operation time, the reference voltage value, and the like are schematically illustrated to the extent that the present invention can be understood and implemented. It was just what I did.
For example, an analog signal output from the D / A converter can be processed by connecting, for example, a D / A converter to an input circuit connected to the input side of the SCF circuit according to the application. Also, the differential signal input to the SCF circuit is not limited to an inverted signal as long as it is a differential signal. In addition, various input circuits such as impedance conversion, level shift, and amplification can be used in combination according to the application and characteristics of the SCF circuit.

Similarly, the differential SCF circuit is not limited to the integration circuit, and may be a low-pass filter circuit, a high-pass filter circuit, or an all-pass filter circuit.
In addition, although the transistor functioning as a switch for opening and closing the circuit has been described using only the N-type MOS transistor for convenience, it can also be realized using a P-type MOS transistor or a CMOS transistor.
Therefore, the present invention is not limited to the described embodiments, and various modifications can be made without departing from the scope of the technical idea shown in the claims.

  In particular, it is used as an A / D converter or audio decoder LSI for processing an analog signal of music for an audio device or a mobile phone, or as an SCF circuit for performing a filtering process for removing a noise component of the signal. It is mounted on an audio decoder LSI or the like.

10 A / D converter 11a SCF circuit 11b Clock generation circuit 11c A / D conversion circuit VINp Non-inverted signal input terminal VINn Inverted signal input terminal VOUTp Non-inverted signal output terminal VOUTn Inverted signal output terminal C1a, C1b Sampling capacitor C2a, C2b Integration capacitor SW1a to SW5a, SW5b to SW5b MOS transistor AMP operational amplifier

Claims (4)

A fully differential switched capacitor filter circuit that performs filtering of an analog signal,
A first signal input terminal for inputting a first analog signal;
A second signal input terminal for inputting a second analog signal;
A first sampling capacitor for sampling a charge corresponding to a voltage of the first or second analog signal input from the first or second signal input terminal;
A second sampling capacitor for sampling a charge corresponding to the voltage of the first or second analog signal input from the first or second signal input terminal;
A fully differential operational amplifier having an inverting input terminal and a non-inverting input terminal ;
First a feedback circuit connected between the said non-inverting input terminal of the fully differential operational amplifier and the inverting output terminal,
A second feedback circuit connected between the inverting input terminal and the non-inverting output terminal of the fully differential operational amplifier,
A first connection state in which an input terminal of the first sampling capacitor is connected to the first signal input terminal and an input terminal of the second sampling capacitor is connected to the second signal input terminal; Switching between a second connection state in which an input terminal of the first sampling capacitor is connected to the second signal input terminal and an input terminal of the second sampling capacitor is connected to the first signal input terminal First switching means;
A third connection state in which output terminals of the first and second sampling capacitors are connected to a reference voltage; an output terminal of the first sampling capacitor is connected to the inverting input terminal of the fully differential operational amplifier; and A fourth connection state in which an output terminal of the second sampling capacitor is connected to the non-inverting input terminal of the fully differential operational amplifier; and an output terminal of the first sampling capacitor that is not connected to the fully differential operational amplifier. Second switching means for switching between a fifth connection state connected to an inverting input terminal and an output terminal of the second sampling capacitor connected to the inverting input terminal of the fully differential operational amplifier ;
Switching control means for controlling switching of the first and second switching means;
With
The switching control means includes
In the first phase, the first and third connection states are set,
In the second phase immediately after the first phase, the second and fourth connection states are set,
In the third phase immediately after the second phase, the second and third connection states are set,
Total difference characterized by controlling switching of said first and second switching means so that said first and fifth connection states are brought into a fourth connection state immediately after said third phase. Dynamic switched capacitor filter circuit. A fully differential switched capacitor filter circuit that performs filtering of an analog signal,
A first signal input terminal for inputting a first analog signal;
A second signal input terminal for inputting a second analog signal;
A first sampling capacitor for sampling a charge corresponding to a voltage of the first or second analog signal input from the first or second signal input terminal;
A second sampling capacitor for sampling a charge corresponding to the voltage of the first or second analog signal input from the first or second signal input terminal;
A fully differential operational amplifier having an inverting input terminal and a non-inverting input terminal;
A first feedback circuit connected between the non-inverting input terminal and the inverting output terminal of the fully differential operational amplifier;
A second feedback circuit connected between the inverting input terminal and the non-inverting output terminal of the fully differential operational amplifier;
A first connection state in which an input terminal of the first sampling capacitor is connected to the first signal input terminal and an input terminal of the second sampling capacitor is connected to the second signal input terminal; A second connection state in which an input terminal of a first sampling capacitor is connected to the second signal input terminal and an input terminal of the second sampling capacitor is connected to the first signal input terminal; First switching means for switching between an unconnected state in which the input terminals of the first and second sampling capacitors are not connected to any of the first and second signal input terminals;
A third connection state in which output terminals of the first and second sampling capacitors are connected to a reference voltage; an output terminal of the first sampling capacitor is connected to the inverting input terminal of the fully differential operational amplifier; and A fourth connection state in which an output terminal of the second sampling capacitor is connected to the non-inverting input terminal of the fully differential operational amplifier; and an output terminal of the first sampling capacitor that is not connected to the fully differential operational amplifier. Second switching means for switching between a fifth connection state connected to an inverting input terminal and an output terminal of the second sampling capacitor connected to the inverting input terminal of the fully differential operational amplifier;
A connection state in which the input terminal of the first sampling capacitor and the input terminal of the second sampling capacitor have the same potential; the input terminal of the first sampling capacitor; and the second sampling capacitor A third switching means for switching between a state in which the input terminal is not connected ;
Switching control means for controlling switching of the first, second and third switching means, respectively ,
The switching control means includes
In the first phase, the first and third connection states are set,
The second phase immediately after the first phase includes a first half phase and a second half phase,
In first half phase of the second phase, the input terminals of the first and second sampling capacitors are not connected to any of said first and second signal input terminals the disconnected state and the fourth The connection state is established, and the third switching means connects the input terminal of the first sampling capacitor and the input terminal of the second sampling capacitor so as to have the same potential ,
In the second half of the second phase, the second and fourth connection states are set, and the third switching means inputs the input terminal of the first sampling capacitor and the input of the second sampling capacitor. Do not connect the terminals to each other,
In the third phase immediately after the second phase, the second and third connection states are set,
The fourth phase immediately after the third phase includes a first half phase and a second half phase,
In first half phase of the fourth phase, the input terminals of the first and second sampling capacitors are not connected to any of said first and second signal input terminals the disconnected state and the fifth When connected state together, by the third switching means, an input terminal of the input terminal of the first sampling capacitor and the second sampling capacitor is connected to each other so that the same potential,
In the latter half of the fourth phase, the first and fifth connection states are set, and the third switching means inputs the input terminal of the first sampling capacitor and the input of the second sampling capacitor. so as not to connect the terminals to each other, the first, fully differential switched capacitor filter circuit you and controls each of the switching of the second and third switching means. The first and second feedback circuits are:
3. The fully differential switched capacitor filter circuit according to claim 1 or 2, comprising only a capacitor or a switch and a capacitor. The fully differential switched capacitor filter circuit according to any one of claims 1 to 3 ,
A single-ended differential conversion circuit that converts a single-ended analog signal into a differential analog signal and outputs the differential analog signal to the fully-differential switched capacitor filter circuit;
An A / D conversion circuit for converting an analog signal filtered by the fully differential switched capacitor filter circuit into a digital signal;
An A / D converter comprising:

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