JP5088073B2 - DC-DC converter - Google Patents

Description

  The present invention relates to a DC-DC converter that can generate a plurality of output voltages using a single inductor.

  Currently, various power supply devices are used in electronic devices. As one of the power supply devices, there is a DC-DC converter that generates an output voltage having a different voltage value from a DC input voltage using a switching element. A general DC-DC converter will be specifically described with reference to FIGS. 6 and 7. FIG. 6 is a circuit diagram of an inverting DC-DC converter that generates an output voltage in which the polarity of the input voltage is inverted, and FIG. 7 is a circuit diagram of a step-up DC-DC converter that generates an output voltage higher than the input voltage. is there.

First, the inverting DC-DC converter will be specifically described with reference to FIG.
The oscillator (OSC) 61 generates a periodically changing waveform signal such as a sawtooth wave or a triangular wave, and outputs the waveform signal to the comparator CMP11. Further, the output signal of the error amplifying circuit 63 configured by using the resistor R13, the capacitor C12, and the operational amplifier OP12 is input to the comparator CMP11. The resistor R13 and the capacitor C12 are phase compensation elements. Accordingly, the comparator CMP11 sets the output signal to L, for example, during the period of the waveform signal <the output signal, according to the magnitude relationship between the voltage values of the output signal of the error amplification circuit 63 and the waveform signal of the oscillator 61. Therefore, the output signal is for PWM (pulse width modulation) control that changes from L → H → L within the period of the waveform signal output from the oscillator 61.

  The driver circuit DV11 receives the output signal and outputs a drive signal corresponding to the voltage value to the gate of a P-channel MOS FET (hereinafter “PMOS transistor”) PM11. Thereby, the PMOS transistor PM11 is turned on while the output signal is L.

  The PMOS transistor PM11 is a switching element for generating an output voltage. A source voltage (input voltage) VDD is applied to the source of the PMOS transistor PM11, and a drain of the PMOS transistor PM11 is connected to the inductor L1. The other end of the inductor L1 is connected to the ground. Thereby, when the PMOS transistor PM11 is turned on, a current flows through the inductor L1, and magnetic energy is accumulated.

  The cathode of the diode D11 is connected to the drain of the PMOS transistor PM11. The anode of the diode D11 is connected to a capacitor C11, a resistor R11, and an output terminal O11 whose other end is connected to the ground. The resistor R11 forms an inverting amplifier circuit 62 together with the resistor R12 and the operational amplifier OP11.

  The magnetic energy stored in the inductor L1 while the PMOS transistor PM11 is turned on generates a current that flows in the same direction as before even when the PMOS transistor PM11 is turned off. Therefore, when the transistor PM11 is turned off, a current flows through a closed loop circuit formed by the inductor L1 → (ground wiring →) capacitor C11 → diode D11 → inductor L1, and electric charge is accumulated in the capacitor C11. As a result, the output voltage appearing at the output terminal O11 is the negative side of the power supply voltage VDD, that is, the polarity is inverted.

The output signal of the operational amplifier OP11, that is, the output signal of the inverting amplification circuit 62 is input to the operational amplifier OP12 that constitutes the error amplification circuit 63. In addition, a reference voltage Vref is applied to the operational amplifier OP12. The reference voltage Vref has an absolute value that is R12 / R11 times the output voltage that should appear at the output terminal O11 (the resistance values of the resistors R11 and R12 are also R11 and R12), and has a different polarity. is there. This causes the operational amplifier OP12 to output an output signal having a voltage value corresponding to the difference between the voltage value of the output signal of the inverting amplifier circuit 62 and the voltage value of the reference voltage Vref, that is, the error. As a result, the error amplifier circuit 63 (the operational amplifier OP12) outputs an output signal having a voltage value corresponding to the output signal input from the inverting amplifier circuit 62. As a result, the comparator CMP11 has an appropriate output voltage value appearing at the output terminal O11. Output to the driver circuit DV11 an output signal having such a duty ratio (the period during which the PMOS transistor PM11 is turned on is the period of the signal output from the oscillator (OSC) 61, that is, the ratio of the switching period). become.

Next, the step-up DC-DC converter will be specifically described with reference to FIG.
In FIG. 7, the same or basically the same elements as those of the step-up DC-DC converter shown in FIG. Accordingly, the description will be made in a manner in which only the portions different from the step-up type are focused.

  The driver circuit DV21 generates and outputs a drive signal to be supplied to the gate of an N-channel MOS FET (hereinafter “NMOS transistor”) NM11 which is a switching element. The source of the transistor NM11 is connected to the ground, and the power supply voltage VDD is applied to the drain via the inductor L1. Also, the drain of the diode D21 is connected to the drain, and the capacitor C21, the resistor R21, and the output terminal O21 are connected to the cathode of the diode D21.

  The capacitor C21 is an element for smoothing the output voltage applied to the output terminal O21, and the other end is connected to the ground. The resistor R21 constitutes a resistor voltage dividing circuit with the resistor R22. The voltage dividing circuit is arranged between the output terminal O21 and the ground, and the voltage at the connection point of the resistors R21 and R22 is applied to the operational amplifier OP12 that constitutes the error amplifying circuit 63. Thereby, the error amplification circuit 63 (the operational amplifier OP12) outputs an output signal corresponding to the difference between the voltage at the connection point and the reference voltage Vref. The voltage to be compared with the reference voltage Vref by the operational amplifier OP12 is the voltage at the connection point because it is a boost type.

  When the NMOS transistor NM11 is turned on, a current flows through the inductor L1, and magnetic energy is accumulated. The current that has passed through the inductor L1 flows to the ground through the transistor NM11. When the transistor NM11 is turned off, the current flowing from the power supply voltage VDD to the inductor L1 flows to the capacitor C21 via the diode D21, and electric charge is accumulated in the capacitor C21. Thereby, the output voltage appearing at the output terminal O21 can be maintained at a predetermined potential equal to or higher than the power supply voltage VDD by the PWM control for adjusting the duty ratio during a period during which the NMOS transistor NM11 is turned on within one switching cycle. The resistance voltage dividing circuit composed of the resistors R21 and R22 and the error amplifying circuit 63 are for performing PWM control for adjusting the duty ratio.

  Some DC-DC converters can generate a plurality of output voltages (hereinafter referred to as “multi-output DC-DC converters” in order to distinguish them from types that generate one output voltage). Some of them have both boosting and inverting functions.

Both the step-up and inverting DC-DC converters generate an output voltage using the inductor L1. The inductor L1 has a large volume (and area) and is difficult to reduce in size. For this reason, the number of inductors has a great influence on the size of the DC-DC converter. As a result, among the conventional multi-output DC-DC converters, as described in Patent Documents 1 and 2, for example, one inductor is used in a time-sharing manner to realize both boosting and inverting functions. There is something to let me. Further, as a step-up type multi-output DC-DC converter capable of outputting a plurality of output voltages having different voltage values by using one inductor in a time-sharing manner, there is one described in Patent Document 3, for example.
JP 2003-319647 A JP 2003-164143 A JP 2005-117886 A JP 2004-72815 A

  The DC-DC converters shown in FIGS. 6 and 7 and the conventional multi-output DC-DC converters described in Patent Documents 1 to 3 each generate an output voltage having a predetermined potential by PWM control. Yes.

  As is well known, the weight of the load to which the DC-DC converter supplies current is not always constant. The weight usually fluctuates. The DC-DC converter is sometimes mounted on an electronic device using a battery as a power source, and there is a strong demand for always realizing high efficiency. However, with PWM control, it is difficult to maintain high efficiency, particularly in light load situations. From these facts, it is considered important to always maintain high efficiency even in a multi-output DC-DC converter regardless of the weight of the load. In order to increase the efficiency at light load in a normal DC-DC converter, PFM (pulse frequency modulation) control is often applied. However, regarding a multi-output DC-DC converter using one inductor in a time-sharing manner, Since the required frequency differs depending on the output, synchronization between the outputs cannot be established, and accordingly, time division control of the inductor cannot be performed properly, and thus PFM control cannot be applied.

  An object of the present invention is to provide a multi-output DC-DC converter that uses one inductor in a time-sharing manner, which can always maintain high efficiency regardless of the weight of a load.

The DC-DC converter of the present invention includes a series circuit in which a first switching element, an inductor, and a second switching element are connected in this order between a first power supply potential and a second power supply potential. A plurality of output voltages can be generated by using an inductor, and control is performed to turn on the first switching element for a predetermined time in a first switching period in which the second switching element remains on. The second switching period during the second switching period in which the first voltage generating means for generating the first output voltage and the first switching element different from the first switching period remain on. performed elements on / off, in response to the second and the second voltage generating means for generating an output voltage, said first output voltage generated by the first voltage generating means, A cycle changing unit for changing the length of the serial first and second switching cycle, the second switching element in response to the second output voltage generated by the second voltage generating means the second Period changing means for changing the period of turning on within the two switching cycles.

Note that one of the first and second output voltages is a boosted voltage boosted higher than the one on the high potential side of the first power supply potential and the second power supply potential, and the other is the first power supply potential. It is desirable that the inversion voltage is lower than that on the low potential side of the power supply potential and the second power supply potential. Also, the first and second switching elements, the first and second voltage generating means, the period changing means, and the period changing means are mounted on one module, and the module is integrated with an inductor. It is desirable to be configured. This module may be a semiconductor integrated circuit. Moreover, it is desirable that the first and second switching periods continue alternately.

  In the present invention, the lengths of the first and second switching periods in which the first and second voltage generating units turn on / off the switching element within the period in accordance with the generated first output voltage, respectively. And the time for turning on the second switching element within the second switching period is changed from the generated second output voltage. Further, the on-time of the first switching element in the first switching period is constant. Since the PFM control is applied in such a manner, it is possible to always maintain high efficiency regardless of the load weight to which the output voltage is applied.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit diagram of the DC-DC converter according to the present embodiment. The DC-DC converter is realized as one that can generate a plurality of output voltages having different voltage values, each having an inverting type and a step-up type function.

  In the error amplifier (transconductance amplifier is used in this embodiment) TA1, the reference voltage Vref is applied to the + input terminal, and the output signal of the inverting amplifier circuit IA1 is input to the − input terminal. Here, the trans-conductance amplifier discharges current (current source) when the input voltage to the + input terminal is greater than the input voltage to the − input terminal, and the input voltage to the − input terminal is input to the + input terminal. If the voltage is larger than the voltage, current is absorbed (current sink), and the magnitude (absolute value) of the current increases as the absolute value of the difference between the input voltage to the −input terminal and the input voltage to the + input terminal increases. . The output terminal of the error amplifier TA1 is connected to the drain of a P-channel MOS FET (hereinafter “PMOS transistor”) PM1 and the constant current source I0. Usually, since the reference voltage Vref is higher than the output voltage of the inverting amplifier circuit IA1, the output of the error amplifier TA1 serves as a current source, and discharges the current I1 according to the difference between the two input voltage values. With this configuration, a current obtained by subtracting the output current I1 of the error amplifier TA1 from the constant current of the constant current source I0 (also referred to as I0) flows through the drain of the PMOS transistor PM1 (the input voltage to the − input terminal is zero). Output current I1 is equal to or slightly smaller than the constant current I0). The drain and gate of the PMOS transistor PM1 and the gate of the PMOS transistor PM2 are connected in common, and the PMOS transistor PM1 and the PMOS transistor PM2 constitute a current mirror circuit. The power supply voltage VDD is applied to the sources of the PMOS transistors PM1 and PM2. Therefore, a current of (I0−I1) flows through the PMOS transistors PM1 and PM2 with respect to the output current I1 output from the error amplifier TA1.

  The drain of the PMOS transistor PM2 on the current copy side is connected to the inverter INV5, the capacitor C1, and the drain of an N-channel MOS FET (hereinafter “NMOS transistor”) NM1. The other end of the capacitor C1 and the source of the NMOS transistor NM1 are each connected to the ground. The output signal of the inverter INV5 is input to the NOR gate NOR.

  In addition, the output signal of the inverter INV4 is input to the NOR gate NOR. As a result, the NOR gate NOR outputs an output signal representing the negation of the logical sum of the output signals of the two inverters INV4 and 5 to the driver circuit DV1. The output signal output from the NOR gate NOR is H (High: the logical value is only when the output signals (levels) output from the two inverters INV4 and 5 are both L (Low), that is, the logical values are both 0. 1). The node H is a node on the output side of the NOR gate NOR.

  The output signal output from the driver circuit DV1 is a drive signal input to the gate of the PMOS transistor PM3 that is a switching element. The driver circuit DV1 outputs a drive signal at a level for turning on the PMOS transistor PM3 while the output signal input from the NOR gate NOR is L.

  The power supply voltage VDD is applied to the source of the PMOS transistor PM3, and the drain thereof is connected to the inductor L and the cathode of the diode ND. The anode of the diode ND is connected to an output terminal O1, a capacitor Co1 whose other end is connected to the ground, and a resistor R1. The capacitor Co1 is an element for smoothing the output voltage applied to the output terminal O1. The other end of the resistor R1 is connected to the inverting input terminal of the operational amplifier OP1 and the resistor R2, and the other end of the resistor R2 is connected to the output terminal of the operational amplifier OP1, which constitutes an inverting amplifier circuit IA1. As a result, the output signal input to the error amplifier TA1 from the inverting amplifier circuit IA1 is obtained by inverting the polarity of the output voltage applied to the output terminal O1.

  Instead of the diode ND, a PMOS transistor or an NMOS transistor in which diodes are connected may be employed. This is the same for the diode PD described later.

  The other end of the inductor L is connected to the drain of the NMOS transistor NM2, and the source of the transistor NM2 is connected to the ground. That is, the NMOS transistor NM2, the inductor L, and the second switching element are the first switching elements between the ground that is the first power supply potential and the power supply voltage VDD (> ground) that is the second power supply potential. A series circuit connected in the order of the PMOS transistor PM3 is connected. Thus, a closed loop circuit in which the current IL passing through the inductor L flows through the NMOS transistor NM2, the ground (ground wiring), the capacitor Co1, and the diode ND can be formed. With the closed loop circuit, an output voltage obtained by inverting the polarity of the power supply voltage VDD is applied to the output terminal O1.

  The circuit configuration of the above-described part is for functioning as an inverting DC-DC converter, and its output voltage is lower (negative voltage) than the ground which is the first power supply potential. For this reason, an output signal obtained by inverting the polarity of the output voltage applied to the output terminal O1 is input to the error amplifier TA1 using the inverting amplifier circuit IA1. As a result, the current value of the output signal output from the error amplifier TA1 corresponds to the potential difference (error) between the reference voltage Vref and the absolute value of the output voltage. The output voltage applied to the output terminal O1 is hereinafter referred to as “inverted output voltage”.

  The speed at which charges are accumulated in the capacitor C1, that is, the speed at which the voltage at the node E, which is a connection point between the drain of the PMOS transistor PM2 and the capacitor C1, changes according to the magnitude of the current flowing through the PMOS transistor PM2. . Depending on the speed, the timing at which the voltage level shifts from H to L at the node F on the output side corresponding to the output signal of the inverter INV5, that is, the timing at which the voltage at the node E reaches the threshold voltage of the inverter INV5. Change. This timing is earlier as the current flowing through the PMOS transistor PM2 is larger, that is, as the output current I1 output from the error amplifier TA1 is smaller. That is, the timing is earlier as the output voltage of the output terminal O1 is closer to the target value. Conversely, the timing is delayed as the output voltage of the output terminal O1 is farther from the target value.

The charge accumulation itself in the capacitor C1 is performed when the NMOS transistor NM1 is off. Since the output signal of the inverter INV4 is input to the gate,
When the output signal is L, it is turned off, and charge can be accumulated. In order for the output signal output from the NOR gate NOR to become L, the output signal of the inverter INV4 must be L. For this reason, while the output signal of the inverter INV4 is L, it is a period during which the PMOS transistor PM3 can be turned on, that is, a period during which it can operate as an inverting DC-DC converter.

  The timing at which the voltage level shifts from H to L at the node F changes within that period. The transition from L to H occurs at the end of that period. Therefore, the timing changes the time during which the PMOS transistor PM3 is turned on within the period. As a result, the inverted output voltage is maintained by PWM control that adjusts the time during which the PMOS transistor PM3 is turned on during the period.

Circuit configurations other than those described above are mainly for functioning as a step-up DC-DC converter.
A reference voltage Vref and a voltage between the resistors R3 and R4 are applied to the error amplifier (trans-conductance amplifier) TA2, and the error amplifier TA2 outputs an output signal having a current value corresponding to the difference between the voltage values. Is output to the drain of the PMOS transistor PM4. The drain and gate of the PMOS transistor PM4 and the gate of the PMOS transistor PM5 are connected in common, and the PMOS transistor PM4 and the PMOS transistor PM5 constitute a current mirror circuit. The power supply voltage VDD is applied to the sources of the PMOS transistors PM4 and PM5. For this reason, a current having the same value corresponding to the output signal output from the error amplifier TA2 flows through the PMOS transistors PM4 and PM5.

  An inverter INV7 is connected to the drain of the PMOS transistor PM5 on the current copy side, and the transistor PM5 functions as a current source of the inverter INV7. That is, the inverter INV7 is composed of a PMOS transistor and an NMOS transistor connected in series. Further, the drain of the PMOS transistor PM5 is connected to the source of the PMOS transistor constituting the inverter INV7, and the input voltage to the inverter INV7 becomes L. The PMOS transistor and the NMOS transistor constituting the inverter INV7 are turned on and off, respectively, so that the current of the transistor PM5 flows through the capacitor C2 described later.

  In addition to the inverter INV1, a capacitor C2 whose other end is connected to the ground is connected to the output side of the inverter INV7. The output signal of the inverter INV1 is input to the inverter INV2, and the output signal of the inverter INV2 is input to the inverters INV7 and INV6, respectively.

  The speed at which charges are stored in the capacitor C2, that is, the speed at which the voltage at the node A on the output side of the inverter INV7 rises depends on the magnitude of the current supplied from the PMOS transistor PM5 to the inverter INV7. When the voltage at the node A becomes higher than the threshold voltage at which the inverter INV1 operates, the output signal of the inverter INV1 changes from H to L. Due to the change, the output signal of the inverter INV2 changes from L to H, that is, the voltage of the node B on the output side and the input signal of the inverter INV7 changes from L level to H level. Due to the change, the PMOS transistor constituting the inverter INV7 is turned off and the supply of the charge to the capacitor C2 is stopped, and the NMOS transistor constituting the inverter INV7 is turned on to discharge the charge accumulated in the capacitor C2. The voltage of A drops below the threshold voltage (ground level).

When the voltage at the node A drops below the threshold voltage, the output signal of the inverter INV1 changes from L to H. As a result, the output signal of the inverter INV2 changes from H to L. For this reason, the accumulation of charges in the capacitor C2 by the inverter INV7 is resumed.

  As described above, the length of the period (cycle) from when charge accumulation in the capacitor C2 resumes to when it resumes depends on the magnitude of the current supplied from the PMOS transistor PM5 to the inverter INV7. Change. Thereby, the inverters INV1, 2, and 7 and the capacitor C2 function as an oscillator that outputs a pulse at a period corresponding to the magnitude of the current supplied from the PMOS transistor 5. In the present embodiment, PFM control is performed to adjust the period of the oscillator as necessary.

  A constant current is supplied from the constant current source IS to which the power supply voltage VDD is applied to the inverter INV6 that receives the output signal of the inverter INV2. (The relationship between the inverter INV6 and the constant current source IS is the relationship between the inverter INV7 and the PMOS transistor PM5. The output side is connected to the inverter INV3 and the other end is connected to the capacitor C3 connected to the ground. Therefore, after the input voltage to the inverter INV6 changes from H to L, the inverter INV3 outputs the output signal for a time determined by its own threshold voltage, the current supplied from the constant current source IS, and the capacitance of the capacitor C3. To maintain the state.

  The output signal of the inverter INV3 is input to the OR gate OR and the odd / even timing generation circuit FF. The generation circuit FF is, for example, a T flip-flop circuit, and inverts the state of the output signal every time the input signal is switched from L to H, that is, changes from L → H or H → L. The output signal is input to the OR gate OR and the inverter INV4. Node C is a node on the output side of the inverter INV3, and node D is a node on the output side of the generation circuit FF.

  The OR gate OR receives the output signals of the odd / even timing generation circuit FF and the inverter INV3, and outputs an output signal representing the logical sum of them to the driver circuit DV2. The driver circuit DV2 is for driving the NMOS transistor NM2, and turns on the NMOS transistor NM2 when its output signal is H, that is, when the voltage of the node G on the output side of the OR gate OR is H level.

  In addition to the inductor L, the drain of the NMOS transistor NM2 is connected to the anode of the diode PD. The cathode of the diode PD is connected to a capacitor Co2, a resistor R3, and an output terminal O2 whose other end is connected to the ground.

  In the present embodiment, an output voltage obtained by boosting the power supply voltage VDD is applied to the output terminal O2. For this reason, a resistance voltage dividing circuit comprising resistors R3 and R4 is disposed between the output terminal O2 and the ground, and the voltage between these resistors is compared with the reference voltage Vref by the error amplifier TA2. Thus, in the error amplifier TA, if the difference between the voltage between the resistors and the reference voltage Vref increases, it is considered that the load is heavier and outputs an output signal with a larger current. On the contrary, if the difference between the voltage between the resistors and the reference voltage Vref becomes small, it is considered that the load is lighter and an output signal with a smaller current is output. Since the output signal is copied, the capacitor C2 is charged. Therefore, it is possible to realize PFM control in which the cycle becomes longer when the load becomes lighter and the cycle becomes shorter when the load becomes heavier. By adopting such PFM control, high efficiency can always be maintained regardless of the weight of the load.

In the present embodiment, when the output signal of the inverter INV4 is L, the PMOS transistor PM3 is turned on / off according to the output signal of the inverter INV5. At this time, the input signal to the inverter INV4 is H opposite to the output signal, and this is input to the OR gate OR, so the NMOS transistor NM2 remains on. Thereby, the DC-DC converter operates as an inverting type. This means that when the output signal of the odd / even timing generation circuit FF is H, that is, the voltage at the node D is at the H level, it operates as an inversion type. On the other hand, when the output signal of the inverter INV4 is H, this is input to the NOR gate NOR, so that the PMOS transistor PM3 remains on. At this time, the input signal to the inverter INV4 is L opposite to the output signal, and this is input to the OR gate OR, so that the NMOS transistor NM2 is turned on / off according to the output signal of the inverter INV3. Thereby, the DC-DC converter operates as a boost type. This means that when the output signal of the odd / even timing generation circuit FF is L, that is, the voltage at the node D is at L level, it operates as a boost type.

  That is, when the voltage at the node D is at the H level, it operates as an inverting type, and when the voltage at the L level is at the L level, it operates as a boost type. As such, the inductor L is controlled in a time-sharing manner and used to generate each output voltage.

  FIG. 2 is a timing chart showing temporal changes in the voltages of the nodes A to H and the current flowing through the inductor L. Next, the operation of the DC-DC converter according to the present embodiment will be specifically described with reference to FIG. Here, a description will be given in a form that pays attention to a change in operation at each time of times T1 to T5.

  In the node A, when the input signal to the inverter INV7 becomes L, charge accumulation in the capacitor C2 starts as described above, and the voltage gradually increases. When the voltage exceeds the threshold voltage of the inverter INV1, the output signal of the inverter INV1 changes from H to L, and the change causes the output signal of the inverter INV2 (signal of the node B) to change from L to H. Due to the change, when the output of the inverter INV7 is inverted (when the PMOS transistor and the NMOS transistor constituting the inverter INV7 are turned off and on, respectively), the voltage at the node A drops to the ground level. The decrease changes the output signal of the inverter INV2 from H to L. For this reason, the output signal of the inverter INV2 becomes H in a pulse shape. The period from when the output signal becomes H to the next H is controlled by the output signal of the error amplifier TA2.

  When the output signal of the inverter INV2 is H, that is, the voltage of the node B becomes H level, the output of the inverter INV6 is inverted (the PMOS transistor and NMOS transistor that constitute the inverter INV6 are turned off and on, respectively), and the output signal of the inverter INV3 Is changed from L to H. Next, when the voltage at the node B changes from H level to L level, the output of the inverter INV6 is further inverted (this time, the PMOS transistor and NMOS transistor constituting the inverter INV6 are turned on and off, respectively), and the charge to the capacitor C3 Accumulation starts. As a result of the accumulation, the voltage across the capacitor C3 rises, and when the threshold voltage of the inverter INV3 is exceeded, the output signal of the inverter INV3 changes from H to L. Therefore, the voltage of the node C on the output side of the inverter INV3 becomes H level when the voltage of the node B becomes H level, and maintains the H level for a certain time after the voltage of the node B changes to L level. .

  At the time T1 when the output signal of the node D, that is, the odd / even timing generation circuit FF changes from H to L, the voltage of the node C changes from L level to H level, so the voltage of the node G on the output side of the OR gate OR Becomes H level. The voltage at the node H on the output side of the NOR gate NOR is at L level. As a result, both the PMOS transistor PM3 and the NMOS transistor NM2 are turned on, and the current IL flows through the inductor L. When the voltage at the node D is at L level, the NMOS transistor NM1 is turned on via the inverter INV4, so that the voltage at the node E maintains L level (ground level).

  At time T2 when the voltage at the node C changes from H level to L level, the change causes the voltage at the node G to change from H level to L level, and the NMOS transistor NM2 is turned off. When the inductor L is turned off, the current L is supplied by the accumulated magnetic energy, and the current IL flows to the capacitor Co2 via the diode PD, and charges are accumulated. Thereby, the boosted output voltage is applied to the output terminal O2.

  At time T3 when the output signal of the odd / even timing generation circuit FF changes from L to H, the NMOS transistor NM1 is turned off, so that charge accumulation in the capacitor C1 is started and the voltage at the node E starts to rise. Therefore, at that time, the voltage at the node F on the output side of the inverter INV5 is at the H level, and the voltage at the node H on the output side of the NOR gate NOR is at the L level. The voltage at node G is at the H level. As a result, both the PMOS transistor PM3 and the NMOS transistor NM2 are turned on, and the current IL flows through the inductor L. As the output signal of the odd / even timing generation circuit FF changes from L to H, charge accumulation in the capacitor C1 is started. Therefore, the PWM control for maintaining the inverted output voltage constant is synchronized with the PFM control. Done.

  At time T4 when the voltage at the node E exceeds the threshold voltage of the inverter INV5, the output signal of the inverter INV5 changes from H to L, and the voltage at the node F becomes L level. Therefore, the output signal output from the NOR gate NOR changes from L to H, and the voltage at the node H becomes H level. Thereby, the PMOS transistor PM3 is turned off.

  At this time, since the voltage of the node G is maintained at the H level, the NMOS transistor NM2 continues to be on. By continuing the ON state, the current IL flowing through the inductor IL by the accumulated magnetic energy is supplied to the capacitor Co1 via the NMOS transistor NM2 and the ground wiring. As a result, the boosted output voltage is applied to the output terminal O2. Thereafter, at time T5 when the output signal of the odd / even timing generation circuit FF again changes from H to L, the same operation as at time T1 is performed.

  In the conventional multi-output DC-DC converter described in Patent Document 3, as shown in FIG. 1 of Patent Document 3, a switching element is prepared for each output voltage boosted in addition to the switching element SW1. These switching elements and switching switch elements must employ high-capacity transistors with a high breakdown voltage and / or a large current, which causes an increase in the size of the semiconductor chip and an increase in cost. In FIG. 1 of Patent Document 3, three large-capacity transistors SW1, SW2, and SW3 are required for two outputs VO1 and VO2.

  On the other hand, in this embodiment, the PMOS transistor PM3 and the NMOS transistor NM2 which are switching elements are for controlling the current IL flowing through the inductor L, and are prepared regardless of the number of output voltages. When an inverted output voltage and a boosted output voltage are generated as output voltages, the destination of the current IL of the inductor L by the switching elements is a diode ND or PD (these correspond to the diodes 31 and 32 of Patent Document 3). Can be controlled. For this reason, unlike the conventional multi-output DC-DC converter described in Patent Document 3, it is possible to avoid the necessity of preparing a switching element for each output voltage.

Hereinafter, the external appearance of the DC-DC converter according to the present embodiment will be specifically described with reference to FIGS.
FIG. 3 is a sectional view of the DC-DC converter according to the present embodiment. The DC-DC converter is manufactured in a form in which a ferrite substrate 38 on which an inductor L is formed is attached to an IC (semiconductor integrated circuit) 31 as a circuit module by an underfill (for example, epoxy adhesive) 33. All of the IC 31 except the inductor L of the circuit elements shown in FIG.

  FIG. 4 is a diagram for explaining the external appearance of the IC 31. FIG. 4A is a perspective view seen from above (a perspective view seen from the bottom opposite to the side facing the ferrite substrate 38, and the stud bump 32 on the rear side seen through is shown by a solid line). 4 (b) is a cross-sectional view taken along the line XX of FIG. 4 (a). FIG. 5 is a diagram for explaining the appearance of the ferrite substrate 38. 5A is a top view of the ferrite substrate 38 showing the copper wiring on the bottom surface (a plan view on the side facing the IC 31), and FIG. 5B is a cross-sectional view taken along the line XX of FIG. 5A. is there.

As shown in FIGS. 3 and 4, on the rear side of the IC 3 1, is a stud bump 32 is more, placement, the one of the ferrite substrate 38, in accordance with the arrangement of the stud bump 32, the electrode 35 is formed Has been.

  Copper wirings 34 are formed on the front and back surfaces of the ferrite substrate 38, respectively. The copper wiring 34 is a wiring constituting the inductor L and is connected by a conductor inserted into the through hole 36. A portion corresponding to the end portion of the inductor L of the copper wiring 34 is connected to one of the stud bumps 32. As a result, current can be supplied from the IC 31 side. The entire ferrite substrate 38 is covered with a protective film 37.

  As described above, the DC-DC converter according to the present embodiment is manufactured by attaching the ferrite substrate 38 on which the inductor L is formed to the IC 31. Thereby, it can be handled as one module (component). In this way, high handleability is realized and application to electronic equipment is made easier.

  In this embodiment, PFM control is applied to generate a boosted output voltage, and PWM control (PWM control synchronized with PFM control) is applied to generate an inverted output voltage. The reverse is also possible.

It is a circuit diagram of the DCDC converter by this embodiment. 6 is a timing chart showing temporal changes in voltages of nodes A to H and currents flowing through an inductor L; It is sectional drawing of the DC-DC converter by this embodiment. It is a figure explaining the external appearance of IC31. FIG. 3 is a diagram for explaining the appearance of a ferrite substrate 38. It is a circuit diagram of a general inverting DC-DC converter that generates an output voltage in which the polarity of an input voltage is inverted. FIG. 3 is a circuit diagram of a general boost DC-DC converter that generates an output voltage higher than an input voltage.

Explanation of symbols

C1-3, Co1, Co2 Capacitor DV1, DV2 Driver circuit IA1 Inverting amplifier circuit INV1-INV7 Inverter IS Constant current source FF Odd / even timing generation circuit NM1, NM2 NMOS transistor ND, PD diode OP1 Operational amplifier O1, O2 Output terminal PM1-PM5 PMOS transistors R1 to R4 Resistors TA1, TA2 Error amplifier VDD Power supply voltage

Claims (5)

A series circuit in which a first switching element, an inductor, and a second switching element are connected in this order between a first power supply potential and a second power supply potential, and a plurality of output voltages are obtained using the inductor. A DC-DC converter that can be generated,
First voltage generating means for performing control to turn on the first switching element for a predetermined time in a first switching period in which the second switching element remains on, and to generate a first output voltage; ,
The second switching element is turned on / off in a second switching period in which the first switching element that is different from the first switching period remains on, and a second output voltage is generated. Second voltage generating means;
Depending on the generated first output voltage by the first voltage generating means, the period changing means for changing the length of the first and second switching period,
In response to said second voltage and the second output voltage generated by the generation means, and duration changing means for changing the period for turning on the second switching element in the second switching cycle,
The DC-DC converter characterized by comprising. One of the first and second output voltages is a boosted voltage higher than that of the first power supply potential and the second power supply potential on the high potential side, and the other is the first power supply potential and the second DC-DC converter according to claim 1, wherein the lower inversion voltage der Turkey than the low potential side of the power supply potential. The first and second switching elements, the first and second voltage generating means, the period changing means, and the period changing means are mounted on one module, and the module is integrated with the inductor. which do DC-DC converter of claim 1, wherein the Turkey.   4. The DC-DC converter according to claim 3, wherein the module is a semiconductor integrated circuit.   5. The DC-DC converter according to claim 1, wherein the first and second switching periods are alternately continued. 6.

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