JP5089322B2 - Via filling method - Google Patents

Description

  The present invention relates to a via filling method in which a metal is filled in a microhole (via) provided on a substrate by plating.

  In many cases, components used in electronic devices are used by combining circuits having respective functions on a substrate. In that case, by providing an insulating layer on the substrate, opening micro holes (vias) in the insulating layer, and filling the vias with metal by plating (via filling), each circuit of the components used in the electronic device is Connected.

  Components used in the electronic device are further provided with solder connection terminals for mounting on the printed circuit board after filling the vias with metal. For this reason, if unevenness occurs in the filling of the metal into the via, the connection reliability may be reduced. Therefore, it is important to fill the vias flatly with metal.

  On the other hand, in consideration of the further increase in the density of electronic device parts in the future, it is conceivable to form vias of various shapes and connect the circuits. When filling the vias having different shapes by plating with a plurality of times for each via type according to the conditions of each via, costs increase. Therefore, there is a need for a method of performing metal filling in various shapes of vias by plating in parallel.

  Patent Document 1 discloses a technique for performing metal filling in parallel by plating on a substrate in which several non-through vias (via holes) having different opening diameters and through vias (through holes) are mixed. Have been described.

Japanese Patent Application No. 2003-253490

  However, in the method performed in Patent Document 1, the metal can be uniformly deposited in the through hole and the metal can be filled in the via hole. However, the difference in the filling amount in each via hole having a different opening diameter can be obtained. There is no consideration.

  The filling speed depends on the depth of the via and the opening diameter. Therefore, when the metal filling into the via holes having different depths and opening diameters is performed in parallel with the method performed in Patent Document 1, the via hole whose filling speed is faster than the set speed has a raised shape after filling. (FIG. 16A). On the other hand, a via hole whose filling speed is slower than the set speed has a concave shape after filling (FIG. 16B). That is, it is conceivable that irregularities are generated in filling the via hole with metal.

  Further, even when a plurality of vias having the same depth and opening diameter are filled with metal by plating, they are not necessarily filled uniformly. That is, unevenness may occur after filling. Even in such a case, it is required to perform filling without filling the metal via without causing irregularities.

  An object of the present invention is to provide a technique capable of filling a plurality of vias with metal by plating without causing unevenness and in parallel.

The present invention provides a via filling method in which a substrate having a plurality of vias is filled with metal by plating.
The plating bath used in the plating process contains an inhibitor that suppresses the filling rate,
Before filling with metal, a voltage is applied to the substrate at a voltage value at which the inhibitor is fixed to the substrate surface,
When voltage is applied to the substrate at a voltage value for filling the metal, and while filling the metal into the plurality of types of vias, when any of the plurality of vias is filled to a predetermined state,
A voltage value (strike voltage) higher than the voltage value for filling metal is applied to the substrate for a predetermined time,
When the target number of vias are filled to the target state, the application of the voltage to the substrate is terminated.

  According to the present invention, the filling of the metal into the plurality of vias by plating can be performed in parallel without causing unevenness.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(About plating equipment)
FIG. 1 shows an example of a plating apparatus 100 used in the present embodiment.

  The plating apparatus 100 includes a plating tank system 110, a DC voltage control apparatus 120, and an information processing apparatus 130.

  The plating tank system 110 includes a main plating tank 111, a sub plating tank 112, an anode 113, a cathode 114, a shielding plate 115, a first pump 116, a second pump 117, a metal melting unit 118, and a filter. 119.

  The main plating tank 111 is filled with the plating bath A. The plating bath A includes a molten metal supplied from a metal melting unit 118 described later and an inhibitor that suppresses the filling rate. In the plating bath A, an anode 113, a cathode 114, and a shielding plate 115 are disposed. As the anode 113, for example, a titanium plate coated with iridium oxide is used. As the cathode 114, a substrate having a plurality of types of vias having different shapes is used. The anode 113 and the cathode 114 are respectively connected to an anode terminal 122 and a cathode terminal 121 of a DC voltage control device 120 described later, and voltage is applied thereto. When a voltage is applied by the DC voltage controller 120, the metal ions in the plating bath A move toward the cathode 114 and are adsorbed on the cathode 114. The shielding plate 115 is disposed between the anode 113 and the cathode 114 in order for the metal ions to move and adsorb on the cathode electrode 114 at a uniform density.

  The first pump 116, the metal melting unit 118, and the filter 119 are connected to the main plating tank 111. In the metal melting unit 118, the metal is melted. The molten metal in the metal melting unit 118 is supplied to the plating bath A in the main plating tank 111 by the connected first pump 116.

  The second pump 117 and the filter 119 are connected to the sub plating tank 112. The second pump 117 sucks the plating bath A in the sub plating tank 112 and supplies it to the main plating tank 111 through the filter 119. When the plating bath A is supplied from the second pump 117 and the amount of the solution in the plating bath A exceeds a predetermined reference value, the main plating bath 111 flows into the sub plating bath 112.

  The DC voltage control device 120 is connected to an anode 113, a cathode 114, and an information processing device 130 described later. The anode 113 is connected by an anode terminal, and the cathode 114 is connected by a cathode terminal. The information processing apparatus 130 to be described later is connected by a cable or the like.

  The DC voltage control device 120 applies voltage to the anode 113 and the cathode 114 in accordance with an instruction signal from the information processing device 130. Further, the DC voltage control device 120 changes the voltage value applied to the anode 113 and the cathode 114 in accordance with an instruction signal from the information processing device 130.

The information processing apparatus 130 includes a control unit (not shown) and a storage unit (not shown). The control unit supplies an instruction signal to the DC voltage control device 120 according to the voltage control program stored in the storage unit.
(About the substrate to be plated)
Next, description will be made with reference to the schematic diagram of the cathode 114 described above shown in FIG. Hereinafter, a wafer 200 is used as a substrate to be plated. Specifically, a silicon wafer will be described as an example.

  As shown in the figure, the wafer 200 to be plated becomes the cathode 114. The wafer 200 is provided with a via 200a, a via 200b, and a via 200c having different opening diameters (FIG. 2A). Here, the sizes of the opening diameters of the via 200a, the via 200b, and the via 200c are 200 Da, 200 Db, and 200 Dc, respectively, and their relationship is 200 Da <200 Db <200 Dc. Since the cathode 114 is connected to the cathode terminal 121 of the DC voltage controller 120, when a voltage is applied, metal is deposited in the via 200a, the via 200b, and the via 200c, and the via 200a, the via 200b, and the via 200c. Is filled with metal.

  Further, as shown in FIG. 2B, the wafers 200 used for the cathode 114 may be provided with vias 210a, vias 210b, and vias 210c having different via depths. At this time, assuming that the depths of the via 210a, the via 210b, and the via 210c are 210Ha, 210Hb, and 210Hc, respectively, these relationships are 200Da <200Db <200Dc.

Here, in FIG. 2, the number of via holes provided in the wafer 200 is three, but is not limited thereto. Further, vias having different depths and opening diameters may be mixed in the wafer 200. Further, only vias having the same depth and opening diameter may be provided in the wafer 200.
(Filling procedure)
The present inventor performs metal filling when a plurality of types of vias with different opening diameters and depths are filled by plating, when any of the plurality of types of vias is filled. It has been found that when application at a voltage value higher than the voltage value (strike voltage application) is performed, metal deposition in a filled via is suppressed as compared with deposition in a via that is still being filled.

  In the present invention, using this property, metal filling by plating is performed in parallel to a plurality of types of vias having different opening diameters and depths. Hereinafter, the procedure of filling vias according to the present invention will be described with reference to FIGS.

  FIG. 3 shows a schematic view of a wafer 300 in which a plurality of vias having the same depth and different opening diameters are provided. The wafer 300 is provided with a via 300a, a via 300b, and a via 300c having different opening diameters. Here, the opening diameters of the via 300a, the via 300b, and the via 300c are 300 Da, 300 Db, and 300 Dc, respectively, and their relationship is 300 Da <300 Db <300 Dc. The plating of the wafer 300 is performed by using the wafer 300 as the cathode 114 and applying a voltage from the DC voltage controller 120.

  FIG. 4 shows the relationship between the voltage applied by the DC voltage controller 120 and the elapsed time in the plating process of the wafer 300.

  The DC voltage controller 120 applies voltage to the wafer 300 as follows. First, in order to fix the inhibitor in the plating bath A to the surface of the wafer 300, the voltage value Va is applied for Ta seconds. At this time, if the voltage value at the time of metal filling is Vb, Va> Vb.

  Next, the applied voltage is lowered to Vb, and metal filling is performed. When the wafer 300 is applied with the voltage Vb, metal is deposited in the via 300a, the via 300b, and the via 300c, and filling is started. The opening diameters of the via 300a, the via 300b, and the via 300c have a relationship of 300Da <300Db <300Dc. Therefore, it is considered that the via 300a is the fastest, the via 300b is the fastest, and the via 300c is filled next, and the via 300a is first filled with the metal to the vicinity of the wafer surface portion 300Sa (see FIG. 5 (a)). If the filling of the metal into the via 300a is continued as it is, the wafer surface portion 300Sa of the via 300a will rise. Therefore, in the present invention, application (strike voltage application) is performed on the wafer 300 at a voltage value Vc higher than the voltage value Vb for filling the metal for Tc seconds. By applying the strike voltage, the filling speed of the via 300a is suppressed.

  The voltage value Vc for applying the strike voltage is a voltage value close to the voltage value Va applied when the inhibitor in the plating bath A is fixed on the surface of the wafer 300. By applying a voltage value close to the voltage value Va, it is considered that the metal of the wafer surface portion 300Sa of the via 300a is affected by the inhibitor fixed on the surface of the wafer 300 and the filling speed is suppressed.

  Then, the DC voltage controller 120 lowers the applied voltage again to the voltage value Vb at which the metal is filled, and continues the metal filling. Then, the metal is filled up to the vicinity of the wafer surface portion 300Sb of the via 300b (FIG. 5B). If the filling of the metal into the via 300b is continued as it is, the wafer surface portion 300Sb of the via 300b will rise. Therefore, in the present invention, application (strike voltage application) is performed on the wafer 300 at a voltage value Vd higher than the voltage value Vb for filling metal for Te seconds. By applying the strike voltage, the filling speed of the via 300b is suppressed.

  The voltage value Vd for applying the strike voltage is a voltage value close to the voltage value Va applied when the inhibitor in the plating bath A is fixed on the surface of the wafer 300. By applying a voltage value close to the voltage value Va, it is considered that the metal of the wafer surface portion 300Sb of the via 300b is affected by the inhibitor fixed on the surface of the wafer 300 and the filling speed is suppressed.

  Then, the DC voltage controller 120 lowers the applied voltage again to the voltage value Vb for filling the metal, and applies the voltage until the metal is filled up to the wafer surface portion 300Sc of the via 300c (FIG. 5C). ).

  Here, if the application with a high voltage for suppressing the filling rate (strike voltage application) is performed before each via is completely filled, a flatter metal filling can be performed.

In FIG. 4, the strike voltage application is performed under the conditions of the voltage value Vc for Tc seconds and the voltage value Vd for Te seconds, but Vc = Vd and Tc = Te may be applied. The voltage values Vc and Vd may be the same as Va. Further, Tc and Te, which are strike voltage application times, may be the same as Ta.
(Conditions for applying strike voltage)
Next, conditions for applying the strike voltage will be described. The present inventors have filled the vias provided on the wafer 400 as shown in FIG. 6A in order to search for a strike voltage application condition effective for suppressing the filling speed of the vias provided on the substrate. Were performed under various strike voltage application conditions. The wafer 400 is provided with a via 400a and a via 400b having the same depth and different opening diameters (FIG. 6A). The opening diameters of the via 400a and the via 400b are 40 μm and 80 μm, respectively. The depth is 35 μm.

  The strike voltage was applied with an application time in the range of 1 to 300 sec and a voltage value in the range of 0.5 to 10.0 V. The strike voltage was applied in a state where the metal was filled up to the surface portion 400Sa of the wafer 400 in the via 400a. After filling the surface portion 400Sb of the via 400b, the filling state of the wafer 400 was evaluated. Specifically, in the surface portion 400Sb of the via 400b, the via is in a state (M) as shown in FIG. 6C, or a bump is formed in the via as shown in FIG. 6D. It was judged whether it was in the state (K) that occurred or in the state (F) in which it was filled flat as shown in FIG. The determination criterion at this time was determined to be a state (M) in which the via was raised when it had a height of +10 μm or more with respect to the height of the surface portion 400Sb of the wafer 400. On the other hand, when there was metal deposition on the bumps having a diameter of +5 μm or more with respect to the height of the surface portion of the wafer 400, it was determined that the bumps were in the vias (K). Table 1 shows the evaluation results.

表１から、ストライク電圧印加を行う電圧値が高く、印加時間は長いときは、ビアにコブが生じた状態（Ｋ）になることがわかった。

From Table 1, it was found that when the voltage value for applying the strike voltage is high and the application time is long, the vias are in a state (K) with bumps.

  Further, it was found that when the voltage value for applying the strike voltage is low and the application time is short, the via is swelled (M).

  That is, it was found that it takes a long time to obtain the effect of suppressing the precipitation when the voltage value at which the strike voltage is applied is low. On the other hand, it was found that when the voltage value for applying the strike voltage is high, a short time is sufficient.

  Therefore, by applying a strike voltage under the conditions of a voltage value of 1.0 to 10.0 V and 1 to 300 seconds, the filling of the metal by plating into a plurality of types of via holes having different depths and opening diameters can be performed. It can be seen that this can be done in parallel without causing

Hereinafter, each example performed in the present embodiment will be described.
(Example 1: About a wafer having a plurality of types of vias having different opening shapes)
In the first example, for a wafer 700 having a plurality of types of vias having a circular opening shape and different opening diameters as shown in FIG. 7A, the vias are filled with metal by plating.

  The via on the wafer 700 was produced by the following procedure. First, photosensitive polyimide was coated on the wafer, and an insulating layer having a thickness of 35 μm was applied. Next, the wafer coated with the insulating layer was exposed and developed to form a plurality of types of vias having different opening diameters. For vias having a circular opening shape, a via 700a having an opening diameter of 30 μm, a 40 μm via 700b, a 50 μm via 700c, a 60 μm via 700d, an 80 μm via 700e, and a 100 μm via 700f are formed. did.

  Further, before filling the metal by plating, a titanium / copper seed layer was formed on the wafer 700 by sputtering. Thereafter, the entire surface of the wafer 700 was plated using 0.1 μm copper sulfate to form a pattern plating resist.

The plating bath A in this example uses a solution of copper sulfate pentahydrate: 150 g / l, sulfuric acid: 150 g / l, chloride ion: 50 mg / l and an Atotech additive in-plate DI leveler. did. In addition, the area where the plating process of the wafer 700 is performed was approximately 60 cm ² .

  The plating process of the wafer 700 was performed by applying a voltage from the DC voltage controller 120 as the cathode 114 of the plating apparatus 100 of FIG.

  FIG. 8 shows the relationship between the applied voltage from the DC voltage controller 120 and the elapsed time in this embodiment.

  In the plating process of the wafer 700, first, a voltage application 8 a of 3.0 V for 40 seconds was applied to the wafer 700 to adhere the inhibitor in the plating bath A to the surface of the wafer 700.

  Thereafter, the applied voltage was lowered to 1.8V, and a voltage application 8b of 1.8V for 500 seconds was performed. At this time, the via 700a was filled with copper up to the wafer surface (FIG. 7B). And in order to suppress precipitation of copper plating in the via 700a, an applied voltage was 3.0V and a voltage application 8c of 20 seconds was performed.

  Subsequently, the applied voltage was lowered to 1.8 V, and a voltage application 8 d of 1.8 V for 1020 seconds was performed. At this time, the via 700b was filled up to the wafer surface with copper (FIG. 7C). Then, in order to suppress the deposition of copper plating in the via 700b, an applied voltage of 3.0V and a voltage application 8e of 20 seconds were performed (FIG. 7D).

  Subsequently, the applied voltage was lowered to 1.8 V, and a voltage application 8 f of 1.8 V for 500 seconds was performed. At this time, the via 700c was filled up to the wafer surface with copper (FIG. 7D). And in order to suppress deposition of copper plating in the via 700c, the applied voltage was 3.0V, and the voltage application 8g for 20 seconds was performed.

  Subsequently, the applied voltage was lowered to 1.8 V, and a voltage application of 1.8 V for 500 seconds was performed for 8 hours. At this time, the via 700d was filled up to the wafer surface with copper (FIG. 7E). Then, in order to suppress the deposition of copper plating in the via 700d, an applied voltage of 3.0V and a voltage application 8i of 20 seconds were performed.

  Subsequently, the applied voltage was lowered to 1.8 V, and a voltage application 8j of 1.8 V for 800 seconds was performed. At this time, the via 700e was filled up to the wafer surface with copper (FIG. 7F). And in order to suppress precipitation of copper plating in the via 700e, an applied voltage was 3.0 V and a voltage application of 8 k for 20 seconds was performed.

  Subsequently, the applied voltage was lowered to 1.8 V, and a voltage application of 8 V for 1.8 V for 1000 seconds was performed. At this time, the via 700f was filled with copper to the wafer surface (FIG. 7G). After the filling of the via 700f was completed, the filling state was confirmed.

  For confirmation of the filling state into vias of 30 μm, 40 μm, 50 μm, 60 μm, 80 μm, and 100 μm, the rising state was measured with reference to the upper surface of the pattern. The result is shown in FIG.

  When the opening shape is circular and the opening diameter is 30 μm, 40 μm, 50 μm, 60 μm, 80 μm, 100 μm, the filling state of the via is about ± 5 μm when the height of the filling surface of the via is taken as a reference, It turned out that it was able to fill in the almost flat state.

  As described above, plating is performed on a wafer having a plurality of types of vias having a circular opening diameter and different opening diameters, and the filling state is described.

  Further, in this embodiment, a wafer 710 having a via having a square opening shape and a size of one side of the square of 30 μm, 40 μm, 50 μm, 60 μm, 80 μm, and 100 μm manufactured in the same procedure as the wafer 700 ( Also for (not shown), plating was performed under the above conditions. And after the filling to each via was completed, the filling situation was confirmed. The result is also shown in FIG.

Even when the opening diameter is a square, the filling state of a via having a square opening shape and the size of one side of the square being 30 μm, 40 μm, 50 μm, 60 μm, 80 μm, or 100 μm depends on the high filling surface of the via. Looking at the above, it became ± 5 μm when the upper surface of the pattern was used as a reference, and it was found that filling was possible in a substantially flat state.
(Example 2: Substrate having a plurality of vias with different depths)
In the second example, for the substrate 800 having a plurality of types of vias with different depths as shown in FIG. 10B, the vias were filled with metal by plating.

  Vias on the substrate 800 are irradiated with a carbon dioxide laser beam onto a printed wiring board (FIG. 10A) laminated in four layers, and a via 800a having an opening diameter of 80 μm and a depth of 80 μm, and an opening diameter of 80 μm. Thus, a via 800b having a depth of 40 μm was formed.

  Further, before plating the substrate 800, cleaning of vias using an aqueous solution of potassium permanganate, degreasing, soft etching, sulfuric acid immersion, catalyst application, accelerator immersion, electroless copper immersion treatment, I went in order. In that procedure, a copper film was formed in each via.

  The plating bath A in this example is a solution obtained by adding an additive VFII made by Sugawara Eugilite to a solution of copper sulfate pentahydrate: 250 g / l, sulfuric acid: 50 g / l, chloride ion: 50 mg / l. used.

  The plating process of the substrate 800 was performed by applying a voltage from the DC voltage controller 120 as the cathode 114 of the plating apparatus 100 of FIG.

  In the plating process of the substrate 800, a voltage of 2.0 V and 80 seconds was first applied to the substrate 800 to adhere the inhibitor in the plating bath A to the surface of the substrate 800.

  Thereafter, voltage application was performed at a voltage value of 1.2 V for 60 minutes. At this time, the via 800b having a depth of 40 μm was filled with copper up to the surface portion of the substrate 800 (FIG. 10C).

  Subsequently, in order to suppress the filling of the via 800b, the voltage value was increased to 3.0V, and a voltage was applied for 30 seconds.

  Thereafter, the voltage was lowered to 1.2V again, and voltage application was performed for 30 minutes. At this time, the via 800a was filled up to the surface portion of the substrate 800 (FIG. 10D), and the filling was completed.

  After completion of filling, the height of the via filling surface was confirmed with reference to the upper surface of the pattern. As a result, it was found that the via 800b having a depth of 40 μm had no bulge and was in a flat state. It was also found that the via 800a having a depth of 80 μm was flat without any dent.

From each example as described above, when the via filling technique of the present invention is used, the filling of the metal by plating into a plurality of types of vias having different depths and opening diameters does not cause unevenness, and Can be done in parallel.
(Example 3: Wafer having a plurality of types of vias having different depths and opening shapes and circular opening diameters)
In the third example, for a wafer 750 having a plurality of types of vias having different depths and different opening diameters as shown in FIG. 11A, the vias were filled with metal by plating.

  Vias on the wafer 750 are coated on a 8-inch wafer with a polyimide film having a thickness of 35 μm, and irradiated with a carbon dioxide laser beam. Thus, a via 750 a having an opening diameter of 30 μm and a depth of 20 μm, an opening diameter of 50 μm and a depth of 35 μm A via 750b was formed. Thereafter, a titanium / copper seed layer was formed by sputtering (FIG. 11A).

  Moreover, before performing the plating process of the wafer 750, acidic degreasing and acid immersion were performed in order.

  The plating bath A in this example used a solution of copper sulfate pentahydrate: 180 g / l, sulfuric acid: 70 g / l, chloride ion: 50 mg / l and an Atotech additive in-plate DI leveler. .

  The plating of the wafer 750 was performed by applying a voltage from the DC voltage controller 120 as the cathode 114 of the plating apparatus 100 of FIG.

  In the plating process of the wafer 750, first, a voltage of 3.0 V and 20 seconds was applied to the wafer 750 to adhere the inhibitor in the plating bath A to the surface of the wafer 750.

  Thereafter, voltage application was performed at a voltage value of 1.8 V for 30 minutes. At this time, the via 750a having an opening diameter of 30 μm and a depth of 20 μm was filled with copper up to the surface portion of the wafer 750 (FIG. 11B).

  Subsequently, in order to suppress the filling of the via 750a, the voltage value was increased to 4.0V and voltage application was performed for 2 seconds.

  Thereafter, the voltage was again lowered to 1.8 V and voltage was applied for 30 minutes. At this time, the via 750b having an opening diameter of 50 μm and a depth of 35 μm was filled up to the surface portion of the wafer 750 (FIG. 11C), and the filling was completed.

  After the filling, the height of the via filling surface was confirmed with reference to the upper surface of the pattern. As a result, it was found that the via 750a having an opening diameter of 30 μm and a depth of 20 μm had no bulge and was in a flat state. It was also found that the via 750b having an opening diameter of 50 μm and a depth of 35 μm had no dent and was in a flat state.

(Example 4: Regarding a substrate having a plurality of types of through holes having different opening diameters)
In the fourth example, for a substrate 900 having a plurality of types of vias with different opening diameters having a circular opening shape as shown in FIG. 12A, the vias were filled with metal by plating.

  The through-holes on the wafer 900 are obtained by drilling a through-hole 900a having an opening diameter of 0.1 mm and a through-hole 900b having an opening diameter of 0.2 mm on a 0.6 mm glass epoxy substrate having copper foil bonded on both sides. Formed. Thereafter, a copper film was formed on the entire surface including the inside of the through hole by an electroless copper plating process. Moreover, before performing the plating process of the board | substrate 900, acid degreasing and acid immersion were performed in order.

  The plating bath A in this example was prepared by adding a solution of Ebara Eugilite additive VFII to a solution of copper sulfate pentahydrate: 250 g / l, sulfuric acid: 50 g / l, chloride ion: 50 mg / l. used.

  The plating process of the substrate 900 was performed by applying a voltage from the DC voltage controller 120 using the cathode 114 of the plating apparatus 100 of FIG.

  In the plating process of the substrate 900, first, a voltage of 0.7 V for 5 minutes was applied to the substrate 900 to reinforce the conductive film formed by sputtering. Thereafter, a voltage was applied at 2.5 V for 20 seconds, and the inhibitor in the plating bath A was adhered to the surface of the substrate 900.

  Thereafter, voltage application was performed at a voltage value of 2.0 V for 2 hours. At this time, the through-hole 900a having an opening diameter of 0.1 mm was filled with copper up to the surface portions on both sides of the substrate 900 (FIG. 12B).

  Subsequently, in order to suppress filling of the through-hole 900a, the voltage value was increased to 2.5 V, and voltage application was performed for 20 seconds.

  Thereafter, the voltage was lowered again to 2.0 V and voltage was applied for 1 hour. At this time, the through hole 900b having an opening diameter of 0.2 mm was filled up to the surface portion of the substrate 900 (FIG. 12C), and the filling was completed.

As a result of confirming the height of the via filling surface with reference to the height of both sides of the substrate after filling, the through hole 900a having an opening diameter of 0.1 mm and the through hole 900b having an opening diameter of 0.2 mm It was found that there was no excitement and it was flat.
(Example 5: Substrate having both through holes and non-through holes)
In the fifth example, for a substrate 950 having through-holes and non-through-hole mixed vias as shown in FIG. 13A, the vias were filled with metal by plating.

  The through-holes on the wafer 900 are a 0.6 mmt glass epoxy substrate with copper foil attached on both sides, a through-hole 950a having an opening diameter of 0.1 mm by a drill, an opening diameter of 0.1 mm by a laser, and a depth of 50 μm. Non-through-holes 950b. Thereafter, a copper film was formed on the entire surface including the inside of the through hole by an electroless copper plating process.

  Moreover, before performing the plating process of the board | substrate 950, acidic degreasing and acid immersion were performed in order.

  The plating bath A in this example is a solution obtained by adding an additive A of EBII made by Ebara Eugillite to a solution of copper sulfate pentahydrate: 200 g / l, sulfuric acid: 100 g / l, chloride ion: 50 mg / l. used.

  The plating process of the substrate 950 was performed by applying a voltage from the DC voltage control device 120 as the cathode 114 of the plating apparatus 100 of FIG.

  In the plating process of the substrate 950, a voltage of 2.5 V for 1 minute was first applied to the substrate 950, and the inhibitor in the plating bath A was adhered to the surface of the substrate 900.

  Thereafter, voltage application was performed at a voltage value of 2.0 V for 2 hours. At this time, the non-through holes 950b having an opening diameter of 0.1 mm and a depth of 50 μm were filled with copper up to the surface portions on both sides of the substrate 950 (FIG. 13B).

  Subsequently, in order to suppress the filling of the non-through holes 950b, the voltage value was increased to 2.5 V and voltage application was performed for 20 seconds.

  Thereafter, the voltage was lowered to 1.5V again, and voltage application was performed for 4 hours. At this time, the through hole 950a having an opening diameter of 0.1 mm was filled up to the surface portion of the substrate 950 (FIG. 13C), and the filling was completed.

After filling, the height of the via filling surface was confirmed with reference to the height of both surfaces of the substrate. It was found that the hole 950b was flat without being raised.
(Example 6: wafer having vias of the same shape)
In the sixth example, for the wafer 1000 having vias having the same shape as shown in FIG. 14, the vias were filled with metal by plating. 14A is a schematic diagram viewed from the upper surface of the wafer 1000, and FIG. 14B is a schematic diagram viewed from a cross section.

  The via on the wafer 1000 was produced by the following procedure. First, photosensitive polyimide was coated on an 8-inch wafer, and an insulating layer having a thickness of 65 μm was applied. Next, the wafer coated with the insulating layer was exposed and developed to form three vias 1000a, 1000b, and 1000c having an opening diameter of 60 μm.

  Further, before filling the metal by plating, a titanium / copper seed layer was formed on the wafer 1000 by sputtering.

  Moreover, before performing the plating process of the wafer 1000, acid degreasing and acid immersion were performed in order.

  As the plating bath A in this example, a solution in which an Atotech additive in-plate DI leveler was added to a solution of copper sulfate pentahydrate: 200 g / l, sulfuric acid: 100 g / l, chloride ion: 50 mg / l was used. .

  The plating process of the wafer 1000 was performed by applying a voltage from the DC voltage controller 120 as the cathode 114 of the plating apparatus 100 of FIG.

  First, a voltage was applied at 0.8 V for 10 minutes to reinforce the conductive film formed by sputtering. Subsequently, voltage was applied at 2.5 V for 30 seconds, and the inhibitor in the plating bath A was adhered to the surface of the wafer 1000. Thereafter, a voltage was applied at 1.2 V for 1 hour to fill the metal. Subsequently, a strike voltage was applied at 2.5 V for 30 seconds. Thereafter, a voltage was applied at 1.2 V for 1 hour to fill the metal. Thereafter, a strike voltage application of 2.5 V for 30 seconds was performed. Thereafter, a voltage was applied at 1.2 V for 1 hour to fill the metal. At this time, as shown in FIG. 15A, the via 1000b was filled with copper up to the surface portion.

  Then, in order to suppress the deposition of copper plating in the via 1000b, a strike voltage was applied for 2.5 V for 30 seconds. A voltage was applied at 1.2 V for 15 minutes to fill the metal. At this time, as shown in FIG. 15B, the via 1000b and the via 1000c were filled with copper up to the surface portion.

  And in order to suppress deposition of copper plating in the via 1000c, a strike voltage was applied for 2.5 V for 30 seconds. A voltage was applied at 1.2 V for 15 minutes, and the via 1000a was filled up to the surface as shown in FIG.

  After completion of filling, the height of the filling surface of each via was confirmed with reference to the height of both surfaces of the substrate, and as a result, it was found that the via 1000a, the via 1000b, and the via 1000c were not raised and were in a flat state. .

  Even when a plurality of vias having the same depth and opening diameter are filled with metal by plating, the vias are not necessarily filled uniformly, and unevenness may occur after filling. The present embodiment is a metal filling method corresponding to this case.

  When one of the three vias 1000a, 1000b, and 1000c is filled up to the surface portion, the depth and opening diameter of the three vias 1000a, 1000b, and 1000c are the same. The difference in speed is thought to be small. Therefore, in this embodiment, even when the filling of the metal into the via is continued, the strike voltage is applied to the substrate for a predetermined time with a voltage value higher than the voltage value for filling the metal, and each via The filling speed was adjusted.

  As described above, in the present invention, the filling of the metal into the plurality of vias by plating can be performed in parallel without causing unevenness.

It is a block diagram which shows an example of the plating apparatus in this embodiment. It is explanatory drawing explaining the structure of the cathode in this embodiment. It is a mimetic diagram showing an example of a wafer which performs plating processing in this embodiment. It is explanatory drawing explaining the relationship between the applied voltage of plating processing and elapsed time in this embodiment. It is explanatory drawing explaining the procedure of the plating process in this embodiment. It is the schematic diagram of the wafer which performed strike voltage application on various conditions. It is a schematic diagram of a wafer having a plurality of types of vias having different opening diameters. It is explanatory drawing explaining the relationship between an applied voltage and elapsed time in the plating process of the wafer which has several types of vias from which opening diameter differs. It is a graph which shows the relationship between the opening diameter of the via | veer after metal filling, and a swelling state in the plating process of the wafer which has several types of vias from which opening diameter differs. It is a schematic diagram of a wafer having a plurality of types of vias having different depths. It is a schematic diagram of a wafer having a plurality of types of vias having different depths and opening diameters. It is a schematic diagram of the board | substrate which has multiple types of through-hole from which opening diameter differs. It is a schematic diagram of the board | substrate with which a through-hole and a non-through-hole are mixed. It is a schematic diagram of a wafer having a plurality of vias having the same shape. It is a schematic diagram of a wafer having a plurality of vias having the same shape. It is a schematic diagram of the board | substrate with a bulge or a dent in a surface part.

Explanation of symbols

  100: Plating apparatus, 110: Plating tank system, 120: DC voltage controller, 130: Information processing apparatus 130, 111: Main plating tank, 112: Sub plating tank, 113: Anode, 114: Cathode, 115: Shielding plate, 116: first pump, 117: second pump, 118: metal melting unit, 119: filter, 200: wafer, 200a to 200c: via, A: plating bath

Claims (13)

In a via filling method in which a substrate having a plurality of vias is filled with metal by plating,
Plating baths used in the plating process includes a suppression agent,
Before filling with metal, a voltage is applied to the substrate at a voltage value at which the inhibitor is fixed to the substrate surface,
When voltage is applied to the substrate at a voltage value for filling the metal, and while filling the metal into the plurality of types of vias, when any of the plurality of vias is filled to a predetermined state,
A voltage value (strike voltage) higher than the voltage value for filling metal is applied to the substrate for a predetermined time,
A via filling method comprising: terminating application of a voltage to a substrate when a target number of vias are filled in a target state. The via filling method according to claim 1,
A voltage value (strike voltage) higher than the voltage value for filling the metal can be determined in advance while applying a voltage to the substrate at a voltage value for filling the metal and continuing filling the metal into the plurality of types of vias. And applying to the substrate for a predetermined time. The via filling method according to claim 1 or 2,
A plurality of vias having different depths exist as the plurality of vias. The via filling method according to claim 1 or 2,
A plurality of vias having different opening diameters exist as the plurality of vias. The via filling method according to claim 1 or 2,
A plurality of vias having different depths and opening diameters exist as the plurality of vias. The via filling method according to claim 1 or 2,
There is a plurality of vias having the same depth and opening diameter as the plurality of vias. The via filling method according to any one of claims 1 to 6,
A plurality of vias that are at least non-through holes exist as the plurality of vias. The via filling method according to any one of claims 1 to 5,
Any of the plurality of vias is a through hole. A via filling method, wherein: The via filling method according to any one of claims 1 and 4,
The via filling method, wherein the plurality of vias are all through-holes. The via filling method according to any one of claims 1 to 9,
A via filling method, wherein the metal filled in the via is copper. The via filling method according to any one of claims 1 to 10,
A via filling method in which the substrate is a wafer. In a via filling method in which a substrate having a plurality of vias is filled with metal by plating,
Plating baths used in the plating process includes a suppression agent,
Before filling with metal, a voltage is applied to the substrate at a voltage value at which the inhibitor fixes to the substrate surface,
A voltage value (strike voltage) higher than the voltage value for filling the metal at a constant cycle while applying the voltage to the substrate at the voltage value for filling the metal and continuing to fill the plurality of vias with the metal. Applying to the substrate for a predetermined time,
A via filling method comprising: terminating application of a voltage to a substrate when a target number of vias are filled in a target state. The via filling method according to claim 12, wherein
There is a plurality of vias having the same depth and opening diameter as the plurality of vias.

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