JP5093148B2 - Over-input determination circuit and amplifier - Google Patents

Description

  The present invention relates to an overinput determination circuit that detects an excessive input to an amplifier used in a transmitter in a microwave band, and an amplification device having the overinput determination circuit.

  If an excessive level signal is input to an amplifier such as a power amplifier, the amplifier may be damaged. Therefore, an over-input determination circuit that determines whether the level of the signal input to the amplifier is excessive is provided (for example, see Patent Documents 1 and 2).

JP-A-5-267945 (paragraph 0002) Japanese Patent Laid-Open No. 11-266123 (paragraphs 0012 and 0016, FIG. 1)

  FIG. 9 is a block diagram showing a circuit for detecting an excessive input to the amplifier in the transmitter in the microwave band together with the amplifier. In the circuit configuration shown in FIG. 9, an RF (radio frequency) signal (radio frequency signal) is input to the input port 11 as an input signal, and an output signal obtained by amplifying the input signal by the amplifier 13 is output from the output port 12. Is done.

  The branch circuit 14 detects the power of the input signal to the amplifier 13 and outputs a signal corresponding to the detected power. The detection circuit 15 outputs a detection voltage (Vout1) corresponding to the signal from the branch circuit 14. The voltage comparison / determination circuit 16 compares the detection voltage with a threshold value, and determines that the input voltage is “over-input” when the detection voltage is higher than the threshold value.

  FIG. 10 is an explanatory diagram showing an example of the relationship between the input signal level (input power) “Pin” to the input port 11 and the detection voltage “Vout1” that is the output voltage of the detection circuit 15 in the circuit configuration shown in FIG. It is. In FIG. 10, the horizontal axis indicates the input signal level “Pin” to the input port 11, and the vertical axis indicates the value of the detection voltage “Vout1” by the detection circuit 15. As shown in FIG. 10, the input power-detection voltage characteristics vary due to variations in the output voltage of the detection circuit 15 (see characteristics 201, 202, 203). Note that the variation in the output voltage of the detection circuit 15 is caused by, for example, the variation in the characteristics of the elements constituting the detection circuit 15.

  The voltage comparison / determination circuit 16 compares the detection voltage “Vout1” from the detection circuit 15 with the voltage value Vthre as the threshold illustrated in FIG. It is determined whether or not there is an excessive input. As illustrated in FIG. 10, when the output voltage of the detection circuit 15 varies, the input signal level regarded as “over-input” also varies. As a result, the overinput determination function may be degraded. For example, where it should be determined that it is originally “over-input”, it may be determined that it is not yet “over-input”. That is, an erroneous determination may occur in the excessive input determination.

  Further, it is necessary to provide a branch circuit 14 for extracting the input signal level to the amplifier 13 and a voltage comparison / determination circuit 16 for comparing the detection voltage “Vout1” by the detection circuit 15 with a threshold value regarded as “excess input”. Therefore, the circuit configuration of the over-input determination circuit becomes complicated.

  Therefore, the present invention provides an overinput determination circuit capable of simplifying the circuit configuration and preventing erroneous determination in overinput determination even when the circuit for detecting the input signal level varies. An object is to provide an amplification device.

  An over-input determination circuit according to the present invention includes a gate resistance provided between a gate constant voltage source for supplying a gate voltage and a gate terminal of the FET, a drain constant voltage source for supplying a drain voltage, and a drain terminal of the FET. A drain resistor provided between the drain resistor, a rectifier circuit connected to the drain terminal side of the drain resistor, and a determination circuit for determining whether or not the input is excessive based on the value of the output voltage of the rectifier circuit. The resistance value of the drain resistance is selected to a value that causes the amount of gate current to rise when the input signal level exceeds a determination level that is determined to be an excessive input. The value is selected to change the output voltage of the rectifier circuit when the value exceeds the value.

  An amplifying apparatus according to the present invention includes an FET, an input signal is input to the gate terminal of the FET, and an output signal is output from the drain terminal of the FET, and an overinput determination circuit that determines an overinput to the amplifier, An over-input determination circuit is provided between the gate constant voltage source for supplying the gate voltage and the gate terminal of the FET, and between the drain constant voltage source for supplying the drain voltage and the drain terminal of the FET. A resistance value of the gate resistance, including a drain resistance provided on the drain terminal, a rectifier circuit connected to the drain terminal side of the drain resistance, and a determination circuit for determining whether or not the input voltage is excessive based on the output voltage value of the rectifier circuit Is selected so that the amount of gate current rises when the input signal level exceeds the judgment level at which it is determined that the input is excessive. Characterized in that the issue level is selected to a value to change the output voltage of the rectifier circuit when exceeding the judging level.

  According to the present invention, the circuit configuration of the overinput determination circuit can be simplified, and erroneous determination in overinput determination can be prevented even if the circuit for detecting the input signal level varies. .

It is a block diagram which shows the circuit for detecting the excessive input to the amplifier in the transmitter of a microwave band with an amplifier. It is explanatory drawing which shows an example of a Pin-Id characteristic and a Pin-Ig characteristic. It is explanatory drawing which shows an example of the relationship between the input signal level (Pin) to an input port, and the output voltage (Vout3) of a rectifier circuit. It is explanatory drawing which shows an example of the relationship between the voltage Vgs and the gate current Ig. It is explanatory drawing which shows the relationship between the voltage VGG by the side of a constant voltage source, and gate current Ig. It is explanatory drawing which shows a VGG-Vgs characteristic. It is explanatory drawing which shows the example which the voltage Vds is fluctuating with a fixed period. It is a block diagram which shows the principal part of the amplifier containing the overinput determination circuit by this invention. It is a block diagram which shows the circuit for detecting the excessive input to the amplifier in the transmitter of a microwave band with an amplifier. FIG. 10 is an explanatory diagram illustrating an example of a relationship between an input signal level (Pin) and a detection voltage (Vout1) in the circuit configuration illustrated in FIG. 9.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a circuit for detecting an excessive input to an amplifier in a microwave band transmitter together with the amplifier. In the circuit configuration shown in FIG. 1, an RF signal is inputted to the input port 31 as an input signal, and an output signal obtained by amplifying an input signal from an output port 32 by an amplifier (FET amplifier) 33 using a FET (field effect transistor). Is output.

  The constant voltage source 34 is a constant voltage source for supplying a gate voltage to the FET amplifier 33. The capacitor 36 plays a role of DC cut for preventing the DC component from the constant voltage source 34 from leaking to the input port 31. The constant voltage source 35 is a constant voltage source for supplying a drain voltage to the FET amplifier 33. The capacitor 37 plays a role of DC cut for preventing the DC component from the constant voltage source 35 from leaking to the output port 32.

  In the present embodiment, the resistor 38 is connected between the point 39 and the point 40 (between the constant voltage source 34 and the gate terminal of the FET amplifier 33). Hereinafter, the resistor 38 is referred to as a gate resistance of the FET amplifier 33. The resistor 41 is connected between the point 42 and the point 43 (between the constant voltage source 35 and the drain terminal of the FET amplifier 33). Hereinafter, the resistor 41 is referred to as a drain resistance of the FET amplifier 33.

  In FIG. 1, the voltage at point 39 (the output side of the constant voltage source 34) is VGG. The voltage at the point 40 (the gate terminal side of the FET amplifier 33) is Vgs. The voltage at the point 42 (the output side of the constant voltage source 35) is set to VDD. The voltage at the point 43 (on the drain terminal side of the FET amplifier 33) is Vds.

  The gate current flowing between the points 39 and 40 is Ig, and the drain current flowing between the points 42 and 43 is Id. The direction of the gate current Ig is assumed to be the direction indicated by the arrow in FIG. 1 (the direction from the constant voltage source 34). The direction of the drain current Id is assumed to be the direction indicated by the arrow in FIG. 1 (the direction from the constant voltage source 35).

  In the circuit configuration shown in FIG. 1, a rectifier circuit 45 is connected to a point 43 via a capacitor 44. The capacitor 44 plays a role of DC cut for preventing the DC component from the constant voltage source 35 from leaking to the rectifier circuit 45. The determination circuit 46 is a circuit for determining whether or not the input signal level to the FET amplifier 33 is an excessive input based on the value of the voltage Vout3 output from the rectifier circuit 45.

  FIG. 2 shows an example of Pin-Id characteristics and Pin-Ig characteristics when the resistance value of the gate resistor 38 in the circuit configuration shown in FIG. 1 is fixed to a certain value and the value of the drain resistance 41 is set to 0Ω. It is explanatory drawing shown. In FIG. 2, the horizontal axis indicates the input signal level “Pin” to the input port 31, and the vertical axis indicates the value of the drain current Id between the point 42 and the point 43 and the gate between the point 39 and the point 40. The value of current Ig is shown. In FIG. 2, the solid line indicates the Pin-Id characteristic, and the broken line indicates the Pin-Ig characteristic.

  In the example shown in FIG. 2, when the input signal level “Pin” to the input port 31 is near P401, the gate current Ig suddenly flows out. When the gate current Ig between the point 39 and the point 40 increases rapidly, the voltage Vgs at the point 40 decreases rapidly and the drain current Id starts to flow out rapidly. Note that “shallow” means a lower voltage in the case of PMOS, and a higher voltage in the case of NMOS. Further, when the resistance value of the gate resistor 38 changes, P401 moves to the right or left in FIG.

  When the resistance value of the gate resistor 38 is determined so that the Pin-Id characteristic and the Pin-Ig characteristic shown in FIG. 2 are obtained, and the resistance value of the drain resistance 41 is fixed to a value other than 0Ω, the input signal shown in FIG. When an input signal level greater than level P401 is applied to port 31, voltage Vds at point 43 fluctuates at a constant period. In other words, in this embodiment, when the resistance value of the drain resistor 41 is applied to the port 31 with an input signal level higher than the input signal level P401 shown in FIG. Use a value that fluctuates.

  The rectifier circuit 45 rectifies and detects the RF component in the periodic fluctuation of the voltage Vds. Then, the detection output is output to the determination circuit 46. That is, the output voltage corresponding to the periodic variation of Vds is input to the determination circuit 46 as the output voltage Vout3 of the rectifier circuit 45.

  FIG. 3 is an explanatory diagram showing an example of the relationship (Pin-Vout3 characteristic) between the input signal level “Pin” to the input port 31 and the output voltage “Vout3” of the rectifier circuit 45. In FIG. 3, the horizontal axis indicates the input signal level “Pin” to the input port 31, and the vertical axis indicates the value of the output voltage “Vout3” of the rectifier circuit 45. The input signal level P501 in FIG. 3 is the same level as the input signal level P401 in FIG. 2, and is an input signal level that is regarded as “over-input”.

  As shown in FIG. 3, when the input signal level to the input port 31 is higher than P501, the output voltage “Vout3” of the rectifier circuit 45 shows a certain voltage value that is not 0V. However, the Pin-Vout3 characteristics vary due to variations in the output voltage of the rectifier circuit 45 (see characteristics 501, 502, and 503). Note that the variation in the output voltage of the rectifier circuit 45 is caused by, for example, the variation in the characteristics of the elements constituting the rectifier circuit 45.

  However, the rectifier circuit 45 does not depend on variations in the Pin-Vout3 characteristic, and outputs a voltage other than 0 V when the input signal level to the input port 31 is higher than P501. Therefore, if the determination circuit 46 determines that the input signal level to the FET amplifier 33 is “excessive input” when a voltage other than 0 V is input, the correct determination result is obtained even if the Pin-Vout3 characteristic varies. Can be obtained. Then, the determination circuit 46 does not execute a process of comparing the input voltage with a threshold value for regarding “over-input”.

  In the circuit configuration of the present embodiment, even if the value of the output voltage Vout3 of the rectifier circuit 45 varies, no erroneous determination occurs in the excessive input determination. Further, a circuit for extracting a part of the input signal level such as the branch circuit 14 in the circuit configuration shown in FIG. 9 is not necessary. In addition, since the determination circuit 46 in the circuit configuration shown in FIG. 1 does not need to have a function of comparing with a threshold value, it is possible to prevent an erroneous operation of an excessive input determination with a simple circuit configuration.

  Next, the operation of the overinput determination circuit in the circuit configuration shown in FIG. 1 will be described more specifically.

  FIG. 4 is an explanatory diagram showing an example of the relationship (Vgs-Ig characteristics) between the voltage Vgs at the point 40 in FIG. 1 and the gate current Ig flowing between the point 39 and the point 40. In FIG. 4, the horizontal axis indicates the voltage Vgs at the point 40, and the vertical axis indicates the value of the gate current Ig flowing between the points 39 and 40. Note that the input signal level at the input port 31 at this time is the same level as the input signal level regarded as “excess input” in FIG. 3. Further, it is assumed that the resistance value of the gate resistor 38 between the point 39 and the point 40 and the resistance value of the drain resistor 41 between the point 42 and the point 43 are 0Ω. From FIG. 4, it can be seen that the gate current Ig flows out as the value of the gate voltage Vgs applied to the FET amplifier 33 becomes shallower (in the example shown in FIG. 4, it approaches 0V).

  FIG. 5 is an explanatory diagram showing the relationship between the voltage VGG at the point 39 and the gate current Ig (VGG-Ig characteristics). In FIG. 5, the horizontal axis indicates the voltage VGG at the point 39, and the vertical axis indicates the value of the gate current Ig flowing between the point 39 and the point 40. In FIG. 5, a characteristic 701 by a broken line indicates a voltage VGG at a point 39 calculated by the equation (1), where Rg is the resistance value of the gate resistor 38 in the FET amplifier 33 showing the Vgs-Ig characteristic illustrated in FIG. 4. And the gate current Ig.

  VGG = Vgs + Ig × Rg (1)

  The characteristic 702 by the solid line is measured when a resistance having the same resistance value as the resistance value Rg of the gate resistance 38 when VGG in the characteristic 701 is calculated is actually inserted between the points 39 and 40. VGG-Ig characteristics are shown. However, the resistance value of the drain resistor 41 between the point 42 and the point 43 is 0Ω.

  As shown in FIG. 5, the measured characteristic 702 is substantially the same as the characteristic 701 obtained by calculation. That is, when the value of the voltage VGG at the point 39 is near V703, the gate current Ig starts to flow abruptly. The voltage value V703 of VGG shown in FIG. 5 is a voltage value at which the drain current Id of the FET amplifier 33 shows a desired value when the input signal level to the input port 31 does not become an excessive input.

  In this embodiment, when the input signal level to the input port 31 becomes a level that is regarded as “excess input” at such a voltage value V703 (when Pin is a value of P401 in FIG. 2 or P501 in FIG. 3), The resistance value of the gate resistance Rg between the point 39 and the point 40 is determined so that the gate current Ig flows out rapidly.

  FIG. 6 is an explanatory diagram showing the VGG-Vgs characteristic. In FIG. 6, the horizontal axis represents the voltage VGG at the point 39, and the vertical axis represents the voltage Vgs at the point 40. When the characteristic 702 shown in FIG. 5 is expressed as a relation between the voltage VGG at the point 39 and the voltage Vgs at the point 40 using the relationship of the expression (1), the characteristic 801 shown by a solid line in FIG. A characteristic 802 indicated by a broken line indicates a VGG-Vgs characteristic when the voltage Vds at the point 43 is lower than the characteristic 702 shown in FIG. The characteristics 801 and 802 are characteristics when the resistance value of the drain resistance 41 between the point 42 and the point 43 is 0Ω.

  In FIG. 6, the value V803 of VGG when the voltage Vgs at the point 40 changes rapidly with respect to the voltage VGG at the point 39 shows the same value as V703 in FIG. As shown in FIG. 6, in the region where the voltage VGG at the point 39 is deeper than V803 (in the example shown in FIG. 6, the region on the negative side far from 0 V), the characteristics 801 and 802 show substantially the same characteristics. In a region where the voltage VGG of the contact 39 is shallower than V803, the characteristics 801 and 802 show different values of Vgs with respect to the value of VGG.

  Next, the drain resistance 41 between the point 42 and the point 43 is given a resistance value which is not 0Ω. At this time, the input signal level at which the gate current Ig of the FET amplifier 33 flows out suddenly is the input port 31. Consider the case where the voltage is applied to.

  In that case, the state transitions as follows.

(1) When the gate current Ig of the FET amplifier 33 suddenly starts to flow, the voltage Vgs at the point 40 suddenly becomes shallow.

(2) When the voltage Vgs at the point 40 suddenly becomes shallow, the drain current Id flowing through the FET amplifier 33 suddenly flows out.

(3) When the drain current Id begins to flow, a voltage drop occurs at the drain resistance 41 between the point 42 and the point 43.

(4) When the voltage drops at the drain resistor 41, the voltage Vds at the point 43 decreases.

(5) The fact that the voltage Vds at the point 43 becomes low means that the characteristic 801 shown in FIG. The fact that the voltage VGG at the point 39 changes from the characteristic 801 to the characteristic 802 at V803 means that the voltage Vgs at the point 40 is abruptly deepened, so the drain current Id flowing through the FET amplifier 33 is abruptly reduced.

(6) When the drain current Id decreases rapidly, the voltage drop at the drain resistance 41 between the point 42 and the point 43 decreases, so the voltage Vds at the point 43 increases.

(7) The increase in the voltage Vds at the point 43 means that the characteristic 802 shown in FIG. When the voltage VGG at the point 39 changes from the characteristic 802 to the characteristic 801 at V803, the voltage Vgs at the point 40 rapidly decreases.

  Since the voltage Vgs at the point 40 suddenly becomes shallow, the state returns to the above (2). Thereafter, since the states (2) to (7) are repeated, the voltage Vds at the point 43 fluctuates at a certain cycle.

  FIG. 7 is an explanatory diagram showing an example in which the voltage Vds fluctuates at a constant cycle at the point 43. In FIG. 7, the horizontal axis indicates time, and the vertical axis indicates the voltage Vds at the point 43. In the example shown in FIG. 7, the voltage Vds at the point 43 fluctuates with a period of 2 MHz.

  As described above, the rectifier circuit 45 rectifies and detects the RF component in the periodic fluctuation of the voltage Vds, and outputs the output voltage Vout3 corresponding to the periodic fluctuation of Vds to the determination circuit 46. The determination circuit 46 determines “over-input” when a voltage other than 0 V is input from the rectifier circuit 45.

  As described above, in the present embodiment, the gate current Ig with respect to the voltage Vgs at the point 40 shown in FIG. 1 has the characteristics shown in FIG. As shown by the characteristic 702 illustrated in FIG. 5, when the voltage VGG at the point 39 becomes the desired voltage V703, the resistance of the gate resistor 38 between the point 39 and the point 40 so that the gate current Ig flows out rapidly. Determine the value. The desired voltage is the value of the voltage VGG corresponding to the input signal level that is desired to be regarded as an excessive input. Then, when the gate current Ig suddenly flows out, the resistance value of the drain resistor 41 between the point 42 and the point 43 is determined so that the voltage Vds at the point 43 fluctuates at a constant period.

  Then, the value of the output voltage Vout3 of the rectifier circuit 45 indicates 0 V when an input signal level equal to or lower than the level regarded as an excessive input enters the input port 31, and an input signal level larger than the level regarded as an excessive input is applied to the input port 31. Since a voltage value other than 0V is indicated when the voltage is input, even if the output voltage Vout3 of the rectifier circuit 45 varies, the over-input determination function is maintained.

  Further, a circuit for extracting a part of the input signal level is not required like the branch circuit 14 shown in FIG. 9, and the determination circuit 46 shown in FIG. Therefore, it is possible to prevent malfunction of over-input determination with a simple circuit configuration.

  FIG. 8 is a block diagram showing a main part of an amplifying apparatus including an overinput determination circuit according to the present invention. As shown in FIG. 8, the amplifying device includes an amplifier 1 using an FET and an over-input determination circuit 2 that determines over-input to the amplifier 1, and the over-input determination circuit 2 supplies a gate voltage. A gate resistor 22 provided between the source 21 and the gate terminal of the FET, a drain constant voltage source 23 for supplying a drain voltage, and a drain resistor 24 provided between the drain terminal of the FET; It includes a rectifier circuit 25 connected to the drain terminal side and a determination circuit 26 that determines whether or not the input is excessive based on the value of the output voltage of the rectifier circuit 25. The resistance value of the gate resistor 22 is selected so that the amount of gate current rises when the input signal level exceeds the determination level determined to be an excessive input, and the resistance value of the drain resistor 24 is determined by the input signal level. A value that changes the output voltage of the rectifier circuit 25 when the level is exceeded is selected.

DESCRIPTION OF SYMBOLS 1 Amplifier 2 Over-input determination circuit 21 Gate constant voltage source 22 Gate resistance 23 Drain constant voltage source 24 Drain resistance 25 Rectifier circuit 26 Determination circuit 31 Input port 32 Output port 33 FET amplifier 34 Constant voltage source 35 Constant voltage source 36 Capacitor 37 Capacitor 38 Resistance (Gate resistance)
39, 40, 42, 43 Point 41 Resistance (drain resistance)
44 Capacitor 45 Rectifier circuit 46 Judgment circuit

Claims (7)

An over-input determination circuit that determines an over-input to an amplifier that uses an FET, an input signal is input to the gate terminal of the FET, and an output signal is output from the drain terminal of the FET,
A gate resistor provided between a gate constant voltage source for supplying a gate voltage and the gate terminal of the FET;
A drain resistance provided between a drain constant voltage source for supplying a drain voltage and the drain terminal of the FET;
A rectifier circuit connected to the drain terminal side of the drain resistor;
A determination circuit for determining whether or not there is an excessive input according to the value of the output voltage of the rectifier circuit,
The resistance value of the gate resistance is selected to a value at which the amount of gate current rises when the input signal level exceeds a determination level determined to be an excessive input,
The over-input determination circuit, wherein the resistance value of the drain resistor is selected to change the output voltage of the rectifier circuit when the input signal level exceeds the determination level. The over-input determination circuit according to claim 1, wherein the resistance value of the drain resistance is selected such that when the input signal level exceeds the determination level, the voltage on the drain terminal side of the drain resistance periodically varies. The over-input determination circuit according to claim 1, wherein the rectifier circuit is connected to a drain terminal side of the drain resistor via a capacitor. The overinput determination circuit according to claim 3, wherein the determination circuit determines that the input signal level to the amplifier circuit is an excessive input when the output voltage of the rectifier circuit rises. The over-input determination circuit according to claim 4, wherein the rectifier circuit determines that the input signal level to the amplifier circuit is an excessive input when the output voltage of the rectifier circuit changes from 0V. Using an FET, an input signal is input to the gate terminal of the FET, and an output signal is output from the drain terminal of the FET;
An over-input determination circuit that determines over-input to the amplifier;
The over-input determination circuit is
A gate resistor provided between a gate constant voltage source for supplying a gate voltage and the gate terminal of the FET;
A drain resistance provided between a drain constant voltage source for supplying a drain voltage and the drain terminal of the FET;
A rectifier circuit connected to the drain terminal side of the drain resistor;
A determination circuit that determines whether or not there is an excessive input according to the value of the output voltage of the rectifier circuit,
The resistance value of the gate resistor is selected to a value at which the amount of gate current rises when the input signal level exceeds a determination level at which it is determined that the input is excessive.
The amplifying apparatus characterized in that the resistance value of the drain resistor is selected to change the output voltage of the rectifier circuit when the input signal level exceeds the determination level. The amplifying apparatus according to claim 6, wherein the resistance value of the drain resistance is selected such that the voltage on the drain terminal side of the drain resistance periodically varies when the input signal level exceeds the determination level.

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