JP5098517B2 - Power consumption analysis method and power consumption analysis apparatus - Google Patents

Description

  The present invention relates to a power consumption analysis method and a power consumption analysis device, and more particularly to a power consumption analysis method and a power consumption analysis device for analyzing power consumption of a semiconductor integrated circuit.

In the development of a system LSI (Large Scale Integrated circuit) chip, it is necessary to calculate the power consumption of the chip with high accuracy at the design stage.
In order to estimate the power consumption of the LSI chip, it is necessary to measure the number of operations of each gate constituting the internal logic circuit. Therefore, the number of operations of the combinational circuit and the register is measured from the logic simulation, and the power consumption is calculated from the load capacity and the current formula of the basic circuit (for example, see Patent Document 1).

  There is also a technique for analyzing power consumption with high accuracy and high speed for the characteristic parts constituting the system LSI. For example, a test pattern for calculating an operating rate of a gate is created from 0/1 probability data for each register in the logic circuit and operating rate data for each register, and the created test pattern is edited for calculating the operating rate. There is a method of calculating the gate operation rate by simulation using a netlist (see, for example, Patent Document 2). If the power consumption of a large-scale LSI such as SoC (System on Chip) with a large-capacity or multi-port memory inside is calculated, the number of memory accesses and the current consumption during memory access are calculated by simulation. There is also a method of calculating memory average power consumption by performing measurement and executing memory average power consumption calculation using the measurement result (see, for example, Patent Document 3).

In recent years, a gated clock buffer (hereinafter referred to as GCB) effective for reducing power consumption has been incorporated into an LSI. The GCB has a function of stopping clock input to a register in a circuit block when the circuit block is not operating. Such an operation rate of the GCB has been measured by manually setting a measurement circuit for each GCB and performing a simulation.
Japanese Patent Laid-Open No. 2-136755 JP 2001-350815 A JP 2003-256495 A

However, in the conventional power consumption analysis method, it is necessary to embed a counter for each measurement signal in order to measure the number of operations of the circuit to be measured.
When power consumption analysis is performed using an FPGA (Field Programmable Gate Array) or an emulator device, the counter for measuring the operation rate is also synthesized with the target circuit, so that the synthesized circuit amount increases. was there. In addition, the measurement data of the counter needs to be dumped in order to predict the power consumption. As the number of counters increases, the dump output also increases, which causes a problem that the speed of power consumption analysis decreases. Also, in the power consumption analysis by simulation, a decrease in simulation speed due to an increase in dump data is a problem.

  By the way, the GCB that has been manually inserted by a designer in the past has been embedded by a designer who knows the GCB insertion position manually when measuring the operation rate. However, in recent years, it has been automatically generated by a logic synthesis tool, and it has become difficult for a designer to embed a measurement counter manually. In order to measure the operation rate with high accuracy, it is necessary to provide a measurement counter for each GCB and dump the data of the measurement counter. However, in the case of a large-scale LSI, since a large amount of GCB exists, it is difficult to insert a measurement counter manually. In addition, the measurement counter provided for each GCB causes problems such as lack of emulation resources and emulation speed delay.

  The present invention has been made in view of the above points, and provides a power consumption analysis method and a power consumption analysis apparatus capable of reducing the analysis time without reducing the estimation accuracy of power consumption. Objective.

  In order to solve the above problems, the present invention provides a power consumption analysis method for a semiconductor integrated circuit as shown in FIG. According to the power consumption analysis method according to the present invention, the design circuit information related to the analysis target semiconductor integrated circuit stored in the design information storage unit 1a is analyzed. Then, in a circuit block that operates in a common operation mode, a measurement target circuit that defines the operation mode is extracted, and feature information that characterizes the measurement target circuit is extracted. Next, the measurement target circuits are grouped based on the grouping policy designated for grouping according to the characteristics of the measurement target circuit and the characteristic information of the measurement target circuit. Then, the number of operations is measured for each group divided by the grouping unit 1d, and the operation rate of the measurement target circuit belonging to the measurement group is calculated based on the measurement result.

  According to such a power consumption analysis method, design circuit information is analyzed, and a circuit to be measured that defines an operation mode in a circuit block having a common operation mode and its feature information are extracted. Next, the extracted measurement target circuits are grouped based on a grouping policy for grouping the measurement target circuits according to characteristics. Then, the number of operations is measured for each grouped measurement group, and the operation rate of each measurement target circuit is calculated based on the measurement result.

  In order to solve the above problems, in a power consumption analysis apparatus for analyzing power consumption of a semiconductor integrated circuit, design information storage means for storing design circuit information related to the semiconductor integrated circuit, and analysis stored in the design information storage means Analyzes the design circuit information of the target semiconductor integrated circuit, extracts the measurement target circuit that defines the operation mode in the circuit block that operates in the common operation mode, and extracts the characteristic information that characterizes the measurement target circuit The measurement target circuits are grouped into measurement groups based on the analysis unit and the grouping policy designated for grouping the measurement target circuits according to the characteristics of the measurement target circuits and the characteristic information of the measurement target circuits. The number of operations is measured for each grouping means and measurement group, and the measurement group is based on the measurement result. Power analysis apparatus characterized by having a toggle rate measuring means for calculating an operation ratio of belonging measured circuit, is provided.

  In such a power consumption analyzer, design circuit information of a semiconductor integrated circuit to be analyzed is analyzed, and a circuit to be measured and its characteristic information are extracted. The measurement target circuits are grouped based on the feature information, the number of operations is measured for each measurement group, and the operation rate of each measurement target circuit is calculated.

  In the present invention, in the operation rate measurement for power consumption analysis, the measurement target circuits extracted based on the design circuit information are grouped based on the characteristics of the measurement target circuit. Then, the number of operations is measured for each grouped measurement group, and the operation rate of each measurement target circuit is calculated based on the measurement result. In this way, by measuring the number of operations for each measurement group, the number of measurement circuits embedded for measurement can be reduced and emulated. As a result, a shortage of emulation resources and emulation speed delay caused by embedding the measurement circuit can be reduced, and the analysis time can be shortened without degrading the estimation accuracy of power consumption.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a conceptual diagram of the invention applied to the embodiment. The power consumption analysis apparatus 1 according to the present invention includes a design information storage unit 1a, an analysis information storage unit 1b, a measurement target circuit analysis unit 1c, a grouping unit 1d, an operating rate measurement unit 1e, and a power consumption calculation unit 1f.

  The design information storage unit 1a is a storage unit that stores design information of a semiconductor integrated circuit that is a target of power consumption analysis. The design information is information generated for circuit design, and includes design circuit information related to the circuit, test information used for logic simulation, and the like. The design circuit information includes, for example, a chip net list expressing the connection state of the circuit, a flip-flop (hereinafter referred to as FF), an RTL (Register Transfer Level) expressing the circuit at the combinational logic circuit level, and the like. is there. The test information includes, for example, a test bench used for logic simulation.

  The analysis information storage unit 1b is a storage unit that stores information referred to in the power consumption analysis process and analysis result information. Information referred to for analysis includes a grouping policy for grouping. The analysis result information includes information such as an analysis result by the measurement target circuit analysis unit 1c and a grouping result by the grouping unit 1d.

  The measurement target circuit analysis unit 1c reads design circuit information stored in the design information storage unit 1a, analyzes this, and extracts a measurement target circuit. Here, a circuit that defines an operation mode in a circuit block that operates in a common operation mode is a measurement target circuit. Further, feature information characterizing the extracted measurement target circuit is also extracted. The analysis result is stored in the analysis information storage unit 1b.

  The grouping unit 1d groups the measurement target circuits extracted by the measurement target circuit analysis unit 1c based on a predetermined grouping policy. In the grouping policy, rules for grouping are specified based on the characteristics of the circuit to be measured. For example, the number of predetermined circuit elements constituting the circuit block, the clock frequency, the module configuration of the circuit block, and the like are designated. The grouping policy may be set in advance by the user, or may be arbitrarily set by the user based on the analysis result of the measurement target circuit analysis unit 1c. Further, based on the analysis result, the power consumption analysis apparatus 1 may set a grouping policy. The grouping unit 1d groups the measurement target circuits into a plurality of measurement groups based on the grouping policy stored in the analysis information storage unit 1b and the characteristic information of the measurement target circuit. Note that the feature information referred to in the grouping process is not limited to the feature information extracted by the measurement target circuit analysis unit 1c. It is appropriately extracted from the design information corresponding to the set grouping policy. The grouping result is stored in the analysis information storage unit 1b.

  The operation rate measuring unit 1e measures the number of operations for each measurement group, and calculates the operation rate of the measurement target circuit belonging to the measurement group based on the measurement result. For example, one measurement circuit corresponding to the measurement group is embedded in the design circuit described in the design circuit information, and emulation is executed by the emulator device based on the circuit information of the design circuit in which the measurement circuit is embedded. The measurement circuit is a circuit that measures the number of operations of the measurement target circuit belonging to the measurement group, and the number of operations of the entire measurement group can be obtained by emulation. Based on the number of operations of the entire measurement group, the operation rate of the measurement target circuit in the group is calculated.

The power consumption calculation unit 1f calculates an estimate of power consumption based on the calculated operation rate.
A power consumption analysis method executed by the power consumption analysis apparatus 1 having such a configuration will be described. Prior to the start of processing, design information of a semiconductor integrated circuit to be subjected to power consumption analysis is stored in the design information storage unit 1a. When the process is started, the measurement target circuit analysis unit 1c analyzes the design circuit information and extracts a measurement target circuit that defines the operation mode of the circuit block having a common operation mode. Further, feature information of the circuit to be measured is also extracted. Next, the grouping unit 1d groups the extracted measurement target circuit based on the grouping policy and the characteristic information of the measurement target circuit. The operating rate measuring means 1e prepares a measuring circuit for each grouped measuring group, performs emulation to measure the number of operations, and calculates the operating rate of each measurement target circuit based on the obtained measurement result. Then, the power consumption calculation unit 1f calculates an estimate of power consumption based on the calculated operation rate.

  As described above, the number of measurement circuits embedded in the design circuit for measurement of the number of operations is reduced by arranging measurement circuits in units of measurement groups and measuring the number of operations. Can do. As a result, it is possible to reduce the shortage of emulation resources and emulation speed delay, and the analysis time can be shortened without reducing the power consumption estimation accuracy. In addition, since it is possible to automatically arrange measurement circuits that have been often inserted manually by hand at an appropriate location, the labor and time required for power consumption analysis can be greatly reduced.

  Hereinafter, embodiments will be described in detail with reference to the drawings, taking as an example the case of analyzing the power consumption of an LSI incorporating a GCB. The GCB is a circuit that defines the operation mode of the circuit block connected to the GCB. When the GCB stops the clock input, the operation mode of the circuit block is OFF, and the operation mode when the clock input is performed is Turn on. In order to analyze the power consumption, the number of GCB operations is measured and the operation rate is calculated.

FIG. 2 is a diagram illustrating an example of a hardware configuration of the power consumption analysis apparatus according to the embodiment of this invention. Here, the power consumption analysis apparatus is configured by a host computer.
The entire power consumption analysis apparatus (host computer) 100 is controlled by a CPU (Central Processing Unit) 101. A random access memory (RAM) 102, a hard disk drive (HDD) 103, a graphic processing device 104, an input interface 105, and a communication interface 106 are connected to the CPU 101 via a bus 107.

  The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data necessary for processing by the CPU 101. The HDD 103 stores an OS and application programs. The design information and analysis information of the semiconductor integrated circuit are stored in the HDD 103 or an external HDD connected via an HDD interface (not shown). A monitor 108 is connected to the graphic processing device 104, and an image is displayed on the screen of the monitor 108 in accordance with a command from the CPU 101. A keyboard 109 a and a mouse 109 b are connected to the input interface 105, and signals transmitted from the keyboard 109 a and the mouse 109 b are transmitted to the CPU 101 via the bus 107. The communication interface 106 is connected to the emulator device 200.

  The power consumption analysis apparatus 100 transmits the design data of the target semiconductor integrated circuit and the entire test bench to the emulator apparatus 200, thereby causing the emulator apparatus 200 to execute logic emulation. Then, the emulation result executed by the emulator device 200 is sent to the CPU 101 via the communication interface 106.

  Next, the procedure of power consumption analysis processing will be described. Each process described below is executed by the power consumption analysis apparatus 100 or the emulator apparatus 200 that receives an instruction from the power consumption analysis apparatus 100. In the embodiment, the power consumption analysis apparatus 100 and the emulator apparatus 200 execute each process according to a start instruction from the user, and display the process result on the monitor 108 screen when the process ends. Of course, each process can be automatically executed. The emulation result is displayed on the monitor 108 by the power consumption analysis apparatus 100 that has acquired the result from the emulator apparatus 200.

FIG. 3 is a flowchart illustrating a procedure of power consumption analysis processing according to the embodiment.
First, data referred to in the power consumption analysis process will be described. The design information storage unit 1a stores a chip net list 301, an RTL 302, and an overall test bench 303, which are design information of a chip to be analyzed. The chip net list 301 is a net list of target chips for power consumption analysis. The RTL 302 is circuit information of the target chip described at the RTL level. The overall test bench 303 is a test bench used for logic emulation. The analysis information storage unit 1b stores analysis result information 310, grouping constraints 320, grouping information 330, GCB operation rate 340, waveform data 350, and average operation rate 360 as information related to analysis. The analysis result information 310 includes a GCB extracted as an analysis result, GCB feature information, a threshold for grouping derived from the feature information, and the like. The grouping constraint 320 is constraint information referred to in grouping processing such as a grouping policy. The grouping information 330 is information regarding grouped GCBs. The GCB operation rate 340 is information regarding the calculated operation rate of each GCB. The waveform data 350 is waveform data of a signal generated when the emulator device 200 executes emulation. Since the average operation rate 360 is used for estimating power consumption, it is a calculated average data operation rate by time.

Subsequently, the flow of processing will be described. The power consumption analysis process is started in response to a start instruction from the user.
[Step S01] The chip net list 301 relating to the target chip is read out, and a net list analysis is performed. In the analysis, GCB is extracted, and subsequently extracted GCB feature information is extracted. Here, the number of FFs connected to each GCB and the number of clock buffers (CLKBUF) are calculated as feature information. Hereinafter, the number of FFs connected to the GCB and the number of CLKBUFs are expressed as the number of connected FFs. Further, the number of GCBs is associated with the number of connected FFs, the distribution situation of the number of GCBs for each number of connected FFs is analyzed, and a threshold for grouping the GCBs is determined. The obtained information is managed as analysis result information 310. Details will be described later.

  [Step S02] When grouping is instructed, the GCB acquired in step S01 is grouped based on the number of connected FFs as the feature information and the determined threshold for grouping. Details will be described later.

  [Step S03] A counter for measuring the number of operations is embedded in each grouped GCB group. The counter counts the number of gate enables of all grouped GCBs. Details will be described later.

  [Step S04] Data of the design circuit for emulation in which the counter is embedded in step S03 is transmitted to the emulator device, and the first entire emulation is executed. After the entire emulation is completed, the measured count value is dumped from the embedded counter as the emulation result. Then, the GCB operation rate of the entire chip by time is calculated from the dumped data, and the data average operation rate by time is predicted from the calculated GCB operation rate.

  [Step S05] Based on the time-averaged data average operation rate prediction calculated in step S04, a point for waveform acquisition is selected. Based on the time-based data average operating rate prediction, waveform acquisition is not performed for a period in which the operating rate prediction does not change, and data of the previous period is used. Thereby, the waveform acquisition point which acquires waveform data can be decreased. In this way, the emulation time is shortened.

[Step S06] The entire emulation (second time) is executed in a mode in which the number of waveform acquisition points is reduced, and waveform data for only the period specified in step S05 is acquired.
[Step S07] An average operating rate is calculated from the waveform data acquired by the entire emulation (second time), and power consumption is estimated from the calculated time-based data average operating rate.

  By executing the above processing procedure, the power consumption estimate of the analysis target chip is calculated. Since the measurement counter for measuring the number of operations used for estimating the power consumption is provided for each GCB group including a plurality of GCBs having similar operations, the total number of measurement counters can be reduced.

Next, the measurement target circuit analysis process (step S01), the grouping process (step S02), and the counter embedding process (step S03) will be described in detail.
First, the measurement target circuit analysis process will be described. FIG. 4 is a flowchart showing the procedure of the measurement target circuit analysis process.

[Step S11] The chip net list 301 is input and analyzed, and the GCB is extracted.
[Step S12] Further, based on the chip net list 301, the number of connected FFs of the GCB extracted in step S11 is calculated. The power consumed by the clock buffer in the circuit block has a correlation with the number of connected FFs. In order to measure the number of operations with a common counter with high accuracy, it is desirable to group GCBs having similar characteristics. Therefore, the number of connected FFs is calculated and used as feature information for grouping.

  [Step S13] The relationship between the number of connected FFs calculated in step S12 and the number of GCBs is graphed. That is, the number of FFs connected to each GCB and the distribution of the number of GCBs indicating the number of GCBs having such a configuration in the analysis target chip are graphed and provided to the user. Note that when automatically determining a threshold value for grouping, it is only necessary to be able to grasp the distribution status, and it is not always necessary to create a graph.

  [Step S14] Based on the graph (the diagram showing the number of FFs connected to the GCB and the distribution of the GCB number), the threshold of the number of connected FFs for grouping (grouping policy) by human or automatic setting ) Is registered and registered in the grouping constraint 320. Of course, a counter for measuring the number of operations can be provided for each number of connected FFs, but depending on the distribution of the number of connected FFs for each GCB, it may not be efficient. Therefore, the number of connected FFs is divided by a predetermined threshold value to achieve grouping. When a person determines the threshold value for the number of connected FFs according to the distribution status, the power consumption analysis apparatus 100 displays the created graph on the monitor 108 and waits for a user input. When a grouping policy is input via the keyboard 109a or the mouse 109b, it is registered in the grouping constraint 320. For automatic setting, a threshold setting policy is determined in advance. The power consumption analysis apparatus 100 determines a grouping policy based on the distribution status of the GCB for each number of connected FFs and a threshold setting policy. For example, if there is a criterion “a place where the change in the number of GCB is large”, such a value is searched and set as a threshold value.

  By executing the above processing, the chip net list 301 is analyzed, and the grouping policy is determined as the analysis result together with the GCB of the analysis target chip and the number of connected FFs of the GCB.

The determination of the grouping policy will be described with a specific example. FIG. 5 is a diagram illustrating an example of a graph of the measurement target circuit analysis result.
In the graph of the measurement target circuit analysis result, the horizontal axis represents the number of FFs connected to one GCB, and the vertical axis represents the number of GCBs. In the example shown in the figure, when the number of FFs connected to the GCB changes from 8 → 9 and 16 → 17, the number of GCBs changes greatly. Therefore, here, a grouping policy is determined in which the number of connected FFs is 9 and 17 as threshold values. Specifically, the groups are grouped into a group A 401 having 0 to 8 connected FFs for GCB and a group B 402 having 9 to 16 connected FFs. A GCB having 17 or more connected FFs is a GCB that exceeds the grouping range, and an operation rate is measured by individually embedding a counter.

Next, the grouping process will be described.
In the above description, the threshold for grouping is set as the grouping policy based on the analysis result of the circuit to be measured. However, the group can be further divided to improve the measurement accuracy. For example, there are GCBs that are automatically set by logic synthesis and those that are manually inserted by a designer. Since the operation rate of the manually inserted GCB is likely to be important in power estimation, a grouping policy for performing individual measurement can be set for a manually input GCB. Whether it is manual input or not can be determined by whether GCB is set at the time of RTL description.

  In order to improve accuracy, it is better to group GCBs that operate in the same way as much as possible. Therefore, the GCB group can be further divided into subgroups based on the operating frequency, module configuration information, and the like. Such a grouping policy is used when a GCB group grouped according to the number of connected FFs is further divided into sub-GCB groups.

FIG. 6 is a flowchart showing the procedure of the grouping process. The same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.
Here, the data referred to in the power consumption analysis process excluding the data described in FIG. 4 will be described. The individual measurement GCB information 331, grouping GCB information 332, group a information 333, and group b information 334 are included in the grouping information 330 regarding the grouped GCB. The individual measurement GCB information 331 is information on the GCB that performs measurement by providing a counter individually. The grouping GCB information 332 is information related to GCBs grouped based on the number of connected FFs. The group a information 333 and the group b information 334 are information related to GCBs belonging to sub GCB groups obtained by further dividing the GCB group grouped into the grouping GCB information 332. The grouping parameter 321 is included in the grouping constraint 320, and a parameter referred to when grouping is registered.

  [Step S21] The GCB, the number of connected FFs of the GCB, and the grouping policy (threshold for the number of connected FFs for grouping) set in the analysis result information 310 are read, and the GCBs are grouped based on the grouping policy. To do. At this time, if a grouping policy is set, the grouping is performed with reference to the set policy. Grouping is performed based on the number of connected FFs, and it is divided into a GCB in which a measurement counter is individually provided to measure the number of operations and a GCB group in which the number of operations is measured with a common measurement counter. The GCB in which the measurement counter is individually provided is registered in the individual measurement GCB information 331. The generated GCB group and information related to the GCB belonging to the GCB group are registered in the grouping GCB information 332.

  [Step S22] After grouping by the number of connected FFs, each generated GCB group is further divided based on the grouping parameter 321. Here, the GCB groups grouped by the number of connected FFs are further divided into sub-GCB groups of group a and group b. Information on the GCB belonging to the divided group a is registered in the group a information 333, and information on the GCB belonging to the group b is registered in the group b information 334.

  By executing the above processing procedure, the GCB groups grouped based on the number of connected FFs are further divided into groups based on the grouping parameters. Thus, the accuracy of measurement can be improved by configuring a GCB group with GCBs having similar power effects.

  Here, each process will be described in more detail. In the overall procedure of the power consumption analysis process shown in FIG. 3, after all the grouping processes are completed, the process for calculating the operation rate calculation counter is performed in each group. When the group to which the user belongs is determined (including the case where it is determined not to belong to the group and to perform independent measurement), it may be performed as needed. In the following description, it is assumed that the operation rate calculation counter is embedded every time a group is determined.

First, the grouping process based on the number of connected FFs will be described. FIG. 7 is a flowchart showing a grouping process procedure in the grouping process.
Here, it is assumed that “manually input GCBs are individually measured” and “grouping by threshold based on the number of connected FFs” are set as the grouping policy.

The grouping process is started from the GCB set at the head of the analysis result information 310.
[Step S211] It is determined whether or not the GCB is a manually input GCB. Whether it is a manually input GCB is determined by whether it is described in the RTL 302 or not. If it is a manually input GCB, the process proceeds to step S214. If it is not manually input GCB, the process proceeds to step S212.

[Step S212] If the GCB is not a manually input GCB, the number of connected FFs is examined based on the analysis result information 310.
[Step S213] The number of connected FFs of the GCB read in step S212 is compared with a threshold value. If the number of connected FFs exceeds the threshold value, the process proceeds to step S214. If the number of connected FFs is smaller than the threshold value, the process proceeds to step S215.

  [Step S214] If the GCB is manually input, or if the number of connected FFs is larger than the threshold value, the number of operations is measured alone, and an operation rate calculation counter is inserted independently. Also, this GCB is registered in the individual measurement GCB information 331, and the process proceeds to step S216.

  [Step S215] When the GCB is not manually input and the number of connected FFs is smaller than the threshold, grouping based on the number of connected FFs is performed. That is, the GCB is registered in the grouping GCB information 332. In the example shown in the figure, there is one threshold value. However, when a plurality of threshold values are set, it is determined which group belongs to the threshold value and registered in the corresponding group.

  [Step S216] It is determined whether grouping processing has been performed for all GCBs. If all the GCBs are not completed, the next GCB is designated and the process returns to step S211. When all the GCBs are finished, the process is finished.

  By executing the above processing procedure, a grouping process is performed based on the number of connected FFs, and the GCB is divided into an individual measurement target GCB and a GCB group corresponding to the number of connected FFs. For the GCB to be individually measured, an operation rate calculation counter is inserted independently.

  For the GCB group corresponding to the number of connected FFs, group division processing is further performed. FIG. 8 is a flowchart showing the procedure of group division in the grouping process. In the figure, an example of a group generated for each process is shown together with a flowchart.

  Assume that grouping based on the number of connected FFs is completed, and two GCB groups with group ID = 1 and group ID = 2 are generated based on the number of connected FFs. Further, it is assumed that an operating frequency and a circuit configuration are specified as group parameters for group division.

  [Step S221] When the process is started, the GCB groups grouped based on the number of connected FFs are divided into groups based on the GCB operating frequency. As a result, the group with group ID = 1 is divided into two groups with group ID = 1_1 and group ID = 1_2. Similarly, the group with group ID = 2 is divided into two groups with group ID = 2_1 and group ID = 2_2.

  [Step S222] Subsequently, the group divided based on the operating frequency is further divided into groups based on the circuit configuration (module unit). As a result, the group with group ID = 1_1 is divided into two groups with group ID = 1_1_1 and group ID = 1_1_2. The same applies to the other groups.

  [Step S223] An operation rate calculation counter is inserted for each group divided into groups. Here, the operation rate calculation counter is set for each of group ID = 1_1_1, group ID = 1_1_2, group ID = 1_2_1,...

  By executing the above processing procedure, the groups grouped according to the number of connected FFs are further divided into groups based on the grouping parameters. Thereby, since GCB which operate | moves similarly is put together as a group, it becomes possible to improve a measurement precision.

  Next, an example of the operation rate calculation counter embedded for each group will be described. FIG. 9 is a diagram showing an example of an emulation design circuit in which a counter is embedded for each group GCB.

  Measurement circuits 510 and 520 for measuring the operation rate of the GCB (GCB-1, GCB-2, GCB-3, GCB-4, GCB-5) are inserted in the emulation design circuit 500.

  In the illustrated example, the GCBs to be measured are grouped into two types of GCB groups based on the clock frequency. The first group is a group consisting of GCB-1, GCB-2, and GCB-3 to which clock-A (a clock signal having a frequency of fclock / 2 with respect to the frequency of the fastest fclock) is input. The corresponding measurement circuit 510 includes registers 511 and EXOR 512 that detect a change in GCLK-1 output from GCB-1 and registers 513 that detect a change in GCLK-2 output from GCB-2. An EXOR 514, a register 515 and an EXOR 516 for detecting a change in GCLK-3 output from the GCB-3, an Add-A 517 for adding outputs from the EXORs 512, 514 and 516, and a counter A518 are included. The second group is a group of GCB-4 and GCB-5 to which clock-B (a clock signal having a frequency of fclock / 4 with respect to the frequency of the fastest fclock) is input. The corresponding measurement circuit 520 includes registers 521 and EXOR 522 that detect changes in GCLK-4 output from GCB-4, registers 523 and EXOR 524 that detect changes in GCLK-5 output from GCB-5, and EXORs 522 and 524. Add-B 525 for adding the outputs of, and a counter B 526.

  The operation of the measurement circuits 510 and 520 will be described using the measurement circuit 510. The register 511 holds the previous output of GCLK_1, which is the output signal of GCB-1, and the EXOR 512 compares the values of the current GCLK_1 and the register 511 and monitors the change. When capturing the signal change of GCLK_1, the EXOR 512 outputs 1 for one processing cycle. EXOR 514 and EXOR 516 operate similarly. The output signals of EXORs 512, 514, and 516 are output to Add_A517. Add-A 517 adds the input signals and outputs them to counter A 518. Therefore, if one output of EXORs 512, 514, and 516 is 1, 1 is output, and if two outputs are 1, 2 is output. Similarly, if all are 1, 3 is output. Since the counter A518 adds the output of Add-A517, as a result, the number of operations of the grouped GCB-1, GCB-2, and GCB-3 is collectively counted. According to such a circuit, the total number of operations of the GCBs belonging to the group can be measured with high accuracy without arranging a counter in each GCB.

Based on the measurement result thus obtained, an average GCB operation rate for each group is calculated. The average GCB operation rate is calculated from the number of operations (count value of the counter of each group), the number of GCBs (GCB number) belonging to the group, and the measurement time.
Average GCB operation rate = (count value of counter / number of GCBs) / measurement time.

As described above, the operation rate is calculated for each grouped GCB, and the power consumption of the entire chip is predicted based on the calculated operation rate.
The above processing functions can be realized by a computer. In that case, a program describing the processing contents of the functions that the power consumption analyzer should have is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic recording device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic recording device include a hard disk device (HDD), a flexible disk (FD), and a magnetic tape. Optical disks include DVD (Digital Versatile Disc), DVD-RAM, CD-ROM (Compact Disc Read Only Memory), CD-R (Recordable) / RW (ReWritable), and the like. Magneto-optical recording media include MO (Magneto-Optical disk).

  When distributing the program, for example, portable recording media such as a DVD and a CD-ROM in which the program is recorded are sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. Further, each time the program is transferred from the server computer, the computer can sequentially execute processing according to the received program.

(Appendix 1) In a power consumption analysis method for analyzing power consumption of a semiconductor integrated circuit,
Analyzing design circuit information relating to the semiconductor integrated circuit stored in the design information storage means, and extracting a measurement target circuit that defines the operation mode in a circuit block that operates in a common operation mode. A procedure for extracting feature information to be characterized;
The measurement target circuits are grouped into measurement groups based on a grouping policy designated for grouping the measurement target circuits according to characteristics of the measurement target circuits and the feature information of the measurement target circuits. And the steps to
A procedure for measuring the number of operations for each measurement group and calculating an operation rate of the measurement target circuit belonging to the measurement group based on a measurement result;
A power consumption analysis method characterized by comprising:

(Supplementary Note 2) The procedure for extracting the feature information of the circuit to be measured is as follows:
Analyzing the design circuit information to calculate a predetermined number of circuits connected to the measurement target circuit, and characterizing the measurement target circuit according to the number of the predetermined circuits;
The power consumption analysis method according to supplementary note 1, wherein:

(Supplementary Note 3) The measurement target circuit is a gated clock buffer, and the predetermined circuit is a flip-flop circuit and a clock buffer connected to the gated clock buffer.
The power consumption analysis method according to supplementary note 2, wherein:

(Supplementary Note 4) The procedure of extracting the feature information of the measurement target circuit is based on the calculated number of the predetermined circuits and the number of the predetermined circuits per measurement target circuit and the corresponding measurement target Analyzing the relationship with the number of circuits, setting a threshold value for the number of the predetermined circuits dividing the group of the circuit to be measured,
In the grouping procedure, the measurement target circuits are grouped by comparing the threshold of the number of the predetermined circuits with the number of the predetermined circuits calculated for each of the measurement target circuits.
The power consumption analysis method according to supplementary note 2, wherein:

(Additional remark 5) The procedure which extracts the said feature information of the said measurement object circuit further graphs the relationship between the number of the said predetermined circuits per said measurement object circuit, and the corresponding number of said measurement object circuits, and produces | generates Display the displayed graph on the display device,
The power consumption analysis method according to appendix 4, wherein:

(Additional remark 6) The procedure which extracts the said feature information of the said measuring object circuit sets the designated value input with reference to the said graph displayed on the said display apparatus to the threshold value of the said predetermined number of circuits,
The power consumption analysis method according to appendix 5, characterized in that:

(Supplementary note 7) In the procedure of extracting the feature information of the measurement target circuit, a value that greatly changes the number of the measurement target circuits with respect to the number of the predetermined circuits is set as a threshold value of the number of the predetermined circuits.
The power consumption analysis method according to appendix 4, wherein:

(Appendix 8) The procedure for grouping is as follows.
When there is a measurement target circuit that exceeds a grouping range defined by a threshold set to the predetermined number of circuits, the measurement target circuits are not grouped.
The power consumption analysis method according to appendix 4, wherein:

(Appendix 9) The procedure for grouping is as follows.
Whether or not the measurement target circuit corresponds to a circuit set by the intention of the designer is determined based on the design circuit information, and when determined to be applicable, do not group the measurement target circuits,
The power consumption analysis method according to appendix 4, wherein:

(Supplementary Note 10) The procedure for grouping is as follows.
When the division policy for further dividing the measurement group grouped based on the threshold value of the number of the predetermined circuits is set as the grouping policy, the division policy and the design circuit of the measurement target circuit Dividing the measurement target circuit divided into the measurement groups into sub measurement groups based on the information,
The power consumption analysis method according to appendix 4, wherein:

(Supplementary Note 11) In the division policy, an operation frequency serving as a reference to be divided into the sub measurement groups or the configuration of the circuit block, or the operation frequency and the circuit block configuration are designated.
The power consumption analysis method according to supplementary note 10, wherein

(Supplementary Note 12) The procedure for calculating the operation rate of the measurement target circuit is as follows:
In the design circuit of the semiconductor integrated circuit, one measurement circuit is embedded for each measurement group, logic emulation is performed using an emulator device, and the number of operations of all the measurement target circuits belonging to the measurement group is performed in the measurement circuit. And calculating the number of operations of each of the measurement target circuits belonging to the measurement group based on the number of operations counted by the measurement circuit.
The power consumption analysis method according to supplementary note 1, wherein:

(Additional remark 13) In the power consumption analyzer which analyzes the power consumption of a semiconductor integrated circuit,
Design information storage means for storing design circuit information relating to the semiconductor integrated circuit;
Analyzing design circuit information of a semiconductor integrated circuit to be analyzed stored in the design information storage means, extracting a measurement target circuit that defines the operation mode in a circuit block that operates in a common operation mode, and performing the measurement Measurement target circuit analysis means for extracting feature information characterizing the target circuit;
The measurement target circuits are grouped into measurement groups based on a grouping policy designated for grouping the measurement target circuits according to characteristics of the measurement target circuits and the feature information of the measurement target circuits. Grouping means to
An operation rate measuring means for measuring the number of operations for each measurement group, and calculating an operation rate of the measurement target circuit belonging to the measurement group based on a measurement result;
A power consumption analysis apparatus comprising:

It is a conceptual diagram of the invention applied to embodiment. It is the figure which showed an example of the hardware constitutions of the power consumption analyzer of embodiment of this invention. It is the flowchart which showed the procedure of the power consumption analysis process of embodiment. It is the flowchart which showed the procedure of the measurement object circuit analysis process. It is the figure which showed an example which graphed the measurement object circuit analysis result. It is the flowchart which showed the procedure of the grouping process. It is the flowchart which showed the process sequence of the grouping in a grouping process. It is the flowchart which showed the process sequence of the group division | segmentation in grouping processing. It is the figure which showed an example of the design circuit for emulation which embedded the counter for every group GCB.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Power consumption analyzer 1a Design information storage means 1b Analysis information storage means 1c Measurement object circuit analysis means 1d Grouping means 1e Operation rate measurement means 1f Power consumption calculation means

Claims (5)

In a power consumption analysis method for analyzing power consumption of a semiconductor integrated circuit,
Analyzes the design circuit information about the semiconductor integrated circuit to be stored in the design information storage unit, the measurement target circuit for controlling the input of the clock to the clock and the clock circuit block receives a signal for controlling the output of the A procedure for extracting a plurality of feature information that characterizes each of the measurement target circuits,
A procedure for grouping a plurality of measurement target circuits into a measurement group including a plurality of measurement target circuits based on the feature information;
A procedure for measuring the number of operations for each measurement group and calculating an operation rate of the measurement target circuit belonging to the measurement group based on a measurement result;
A power consumption analysis method characterized by comprising: The procedure for extracting the feature information of the measurement target circuit is as follows:
Analyzing the design circuit information to calculate a predetermined number of circuits connected to the measurement target circuit, and characterizing the measurement target circuit according to the number of the predetermined circuits;
The power consumption analysis method according to claim 1. The procedure for extracting the feature information of the measurement target circuit is based on the calculated number of the predetermined circuits, the number of the predetermined circuits per the measurement target circuit, and the corresponding number of the measurement target circuits. The threshold of the number of the predetermined circuits that divide the group of the circuit to be measured is set,
In the grouping procedure, the measurement target circuits are grouped by comparing the threshold of the number of the predetermined circuits with the number of the predetermined circuits calculated for each of the measurement target circuits.
The power consumption analysis method according to claim 2. The procedure for calculating the operation rate of the measurement target circuit is as follows:
In the design circuit of the semiconductor integrated circuit, one measurement circuit is embedded for each measurement group, logic emulation is performed using an emulator device, and the number of operations of all the measurement target circuits belonging to the measurement group is performed in the measurement circuit. And calculating an operation rate of each measurement target circuit belonging to the measurement group based on the number of operations counted by the measurement circuit.
The power consumption analysis method according to claim 1. In a power consumption analyzer that analyzes the power consumption of a semiconductor integrated circuit,
Design information storage means for storing design circuit information relating to the semiconductor integrated circuit;
It analyzes the design circuit information of the semiconductor integrated circuit to be analyzed stored in the design information storage unit, the measurement for controlling the input of the clock to the clock and the clock of the circuit block by inputting a signal for controlling the output A plurality of target circuits, and measurement target circuit analysis means for extracting feature information characterizing each of the measurement target circuits;
Grouping means for grouping a plurality of measurement target circuits into measurement groups including the plurality of measurement target circuits based on the feature information;
An operation rate measuring means for measuring the number of operations for each measurement group, and calculating an operation rate of the measurement target circuit belonging to the measurement group based on a measurement result;
A power consumption analysis apparatus comprising:

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