JP5112359B2 - Power converter - Google Patents

Description

  The present invention is an IP rectifier that supplies DC power of several V to 48 V to routers, servers, etc. of data centers, and a DC power source of 400 V to 800 V used in DC sputtering equipment, particularly AC 400 V to 480 V. The present invention relates to a power conversion apparatus that performs power conversion of a high-voltage commercial AC power supply system.

  IP rectifiers for data centers supply DC power of several V to 48 V to routers, servers, etc. In recent years, power consumption has increased to several hundred kW with the spread of the Internet, and multiple unit rectifiers of about 20 kW are connected in parallel. I'm driving.

  In addition, DC sputtering devices are used in liquid crystal panel manufacturing devices and solar cell panel manufacturing devices. Due to the increase in the size of glass or silicon substrates, the rated power of sputtering DC power supply devices used has been several hundred kW in recent years. A plurality of unit rectifiers of about 20 kW are operated in parallel.

  The AC input voltage of such a rectifier or sputtering power supply is generally AC 200V to 220V. However, in recent large capacity rectifiers and sputtering DC power supplies, in order to reduce the AC input current of the AC power receiving equipment. In many cases, an AC input voltage of 400 V to 480 V is employed. Hereinafter, the AC input voltage 400V to 480V (high voltage commercial AC power supply voltage) is referred to as “HVAC”.

  In these large-capacity rectifiers and DC power supplies for sputtering, a DC / DC converter is generally connected after a rectifier circuit that rectifies an AC power supply voltage, and input / output insulation and output control are generally performed by the DC / DC converter. It is.

  In AC200V to 220V, the rectified output voltage obtained by simply rectifying the AC power supply voltage is about 300V, and the output voltage of the power factor correction circuit is equal to or higher than the peak value of AC200V to 220V (for example, about 360V). If a voltage-type converter circuit in which the voltage applied to the switching element used is limited to the power supply voltage, such as a half or full bridge system, a general-purpose FET (low on-resistance, low withstand voltage, and low cost as a switching semiconductor element of the converter circuit) For example, a general-purpose FET having a withstand voltage of 500 V can be used.

  However, when the input voltage is HVAC of AC 400 V to 480 V, the rectified output voltage of the rectifier circuit is about 620 V to 744 V at the maximum in consideration of fluctuations, and the output voltage of the power factor correction circuit is AC 400 V to 480 V. The converter input voltage is equal to or higher than the peak value (DC high voltage close to 800V) (the peak value of AC 400V to 480V is HVDC). Therefore, the withstand voltage of the switching semiconductor element of the converter circuit is required to be at least about 1000V. However, when the breakdown voltage increases, the on-resistance of the FET increases with the square of the breakdown voltage ratio, and the on-resistance of the 1000V withstand voltage FET becomes nearly four times that of the 500V withstand voltage FET. Although it is conceivable to use an IGBT instead of an FET, the IGBT has a drawback that the switching frequency cannot be increased.

  For this purpose, two converters using 500V withstand voltage FETs are connected in series between the HVDC inputs, the input voltage of each converter is reduced to 1/2 of the HVDC input (for example, 800V), and the DC output of each converter Is used to output a DC output voltage Vo.

  However, in this series system, unless the input impedance (that is, input current) of each converter is controlled to be the same, the input voltage of each converter becomes unbalanced and cannot be maintained at 1/2 of the HVDC input. Input voltage will rise too high, which can destroy the converter.

  In order to correct this voltage imbalance, the inputs of a plurality of converters are connected in series between the HVDC input terminals, and the input voltage of each converter is divided to cope with a high voltage. Further, the converters connected in series A circuit that corrects the imbalance of the input voltage by detecting the imbalance of the input voltage and individually controlling the on-pulse width input to each converter is known (see, for example, Patent Document 1).

JP 2005-033967 A

  FIG. 11 is a diagram showing a conventional equivalent circuit 900.

  The reason why the input voltage of each converter is unbalanced in the conventional example will be described below.

  The conventional equivalent circuit 900 is a circuit in which individual choke input filter circuits 30a and 30b are provided for each of the unit converters 10a and 10b.

  In the conventional parallel connection shown in FIG. 11, if the circuit constants of the two converters are exactly the same, and the switching time for the same drive signal of the FET is the same, the input currents of the two converters are the same. The voltages of the DC input capacitors C1a and C1b are equal, and the output current sharing is also the same.

  However, in practice, even if the circuit constants of the two converters are exactly the same, the variation in switching time for the same drive signal of the FETs of the two converters cannot be made zero.

  FIG. 12 is a time chart showing the operation of the conventional example.

  Now, it is assumed that the circuit impedance (resistance, leakage inductance, diode forward voltage) of the converter 10a is substantially the same as the circuit impedance of the converter 10b. However, it is assumed that the ON time of this set is relatively long and Δt (for example, 10%) longer than the ON time of the set of FETs 12b and 15b due to the switching characteristics of the FETs 12a and 15a. As a result, when the same signal is applied to the FETs 12a and 15a and the FETs 12b and 15b and turned on, as shown in (1) and (2) of FIG. The voltage time product of the illustrated polarity applied to the choke 31b is larger. When an off signal is simultaneously applied to the FETs 12a and 15a and the FETs 12b and 15b, the chokes 31a and 31b turn on the flywheel diodes 23a and 23b and reset them with the output voltage Vo. A reset generates a reverse voltage of the same voltage time product as the applied voltage time product, or reduces the current flux by decreasing the current until the increased current increment at the applied voltage is zero. It is to restore.

  However, since the output voltage Vo is common, Vo = E1 × t1 / T = E2 × (t1−Δt) / T. That is, V1 / V2 = (t1−Δt) / t1, and when Δt = 10%, V1 / V2 = 0.9. Since E1 and E2 are proportional to Vin1 and Vin2, the input voltage of the converter is 10% unbalanced.

  FIG. 13 is a diagram showing a simulation result in the conventional example shown in FIG.

  Vch1 shown in FIG. 13 (1) is the voltage across the DC input capacitor C1a, and Vch2 is the voltage across the DC input capacitor C1b, and the voltage difference becomes large and unbalanced, as shown in FIG. 13 (1). There is a voltage difference of about 40V. 13 (2) shows the voltages of the chokes 31a and 31b, FIG. 13 (3) shows the currents of the chokes 31a and 31b, and FIG. 13 (4) shows the currents of the FETs 12a and 12b. The higher current becomes larger and the lower current becomes smaller.

  However, in the above conventional example, the input voltage becomes unbalanced. For example, when the on-time of each unit converter is controlled to correct the input voltage unbalance of each converter, the control circuit becomes complicated. There is a problem.

  An object of this invention is to provide the power converter device with which the circuit which controls the input voltage balance of the several series connection converter connected in series between HVDC input terminals is simple.

  The present invention is applicable to power conversion of commercial high-voltage AC power supply voltage such as AC400V system using a low-breakdown-voltage switching semiconductor element, IGBT, especially an inexpensive and low on-resistance FET, and between the HVDC input terminals. The idea of connecting a plurality of (two or more natural numbers n) converters in series and dividing the input voltage to each converter to cope with a high voltage is the same as in Patent Document 1, but the output side of each converter The connection point is not the output of the choke input type filter circuit, the so-called final output point, but is connected in common at the input of the choke input type filter circuit, that is, the output of the rectifier circuit. Therefore, the input voltage of each converter is almost equal to the input DC power supply voltage without complicated voltage balance control. Such that 1 / n, automatically take voltage balancing, it is a power conversion device corresponding to the input of the high voltage AC power supply voltage.

  According to the present invention, even when considering fluctuations of DC voltage obtained by rectifying a high-voltage commercial AC voltage such as 400V system, switching such as an FET with a low withstand voltage lower than its maximum value and a low forward voltage drop is possible. When a power conversion device is configured using semiconductor elements, an effect is achieved that the circuit for controlling the input voltage balance of a plurality of series-connected converters connected in series between the HVDC input terminals is simple.

1 is a circuit diagram illustrating a power conversion apparatus 100 that is Embodiment 1 of the present invention. FIG. It is a figure which shows the equivalent circuit 100E of Example 1. FIG. 3 is a time chart showing the operation of the first embodiment. It is a figure which shows the simulation result in Example 1. FIG. It is a circuit diagram which shows the power converter device 200 which is Example 2 of this invention. It is a circuit diagram which shows the power converter device 300 which is Example 3 of this invention. It is a circuit diagram which shows the power converter device 400 which is Example 4 of this invention. It is a circuit diagram which shows the power converter device 500 which is Example 5 of this invention. It is a circuit diagram which shows the power converter device 600 which is Example 6 of this invention. It is a circuit diagram which shows the power converter device 700 which is Example 7 of this invention. It is a figure which shows the equivalent circuit 900 of a prior art example. It is a time chart which shows operation | movement of a prior art example. It is a figure which shows the simulation result in a prior art example.

  The modes for carrying out the invention are the following examples.

  FIG. 1 is a circuit diagram showing a power conversion apparatus 100 that is Embodiment 1 of the present invention.

  The power conversion apparatus 100 includes a communication 48V output rectifier.

  Although the HVAC input is usually three-phase, here, a single-phase block in which the AC input terminal I1 and the terminal I2 are connected to the one-phase line voltage of the three-phase HVAC power supply will be described.

  One single-phase block includes a bridge rectifier BR1 connected between the U-V lines, a smoothing choke coil 81, DC input capacitors C1A and C1B, balance resistors R1 and R2, and a DC-DC converter circuit 5. And have.

  The DC input capacitors C1A and C1B are examples of a plurality of DC input capacitors connected in series between input high-voltage DC power supply terminals.

  A smoothing choke coil 81 and DC input capacitors C1A and C1B formed of electrolytic capacitors are connected in series to the output terminal of the bridge rectifier BR1. When the unit converters 10A and 10B are stopped, balance resistors R1 and R2 are connected in parallel in order to compensate for imbalance due to leakage current of the DC input capacitors C1A and C1B.

  Unit converters 10A and 10B are unit converters connected to both ends of each of the plurality of DC input capacitors and provided in the same number as the number of DC input capacitors, and include a semiconductor switching element, a transformer, and a rectifier circuit. This is an example of a plurality of unit converters including an output terminal connected in parallel to an input terminal of the choke input type filter circuit.

  The output voltage of the bridge rectifier circuit BR1 is about 800V, which is higher than the maximum peak value of the input power supply voltage (AC400V to 480V). Since the normal electrolytic capacitor has a withstand voltage of about 450V, two electrolytic capacitors with a withstand voltage of 450V are connected in series as DC input capacitors C1A and C1B for smoothing the rectified voltage.

  Unit converters 10A and 10B having the same configuration are connected to the DC input capacitors C1A and C1B. Since they have the same configuration, the suffix A is added to the components of the unit converter 10A, and the suffix B is added to the components of the unit converter 10B.

  Unit converter 10A is a converter in which FET 12A, primary winding 14A of transformer 13A, and FET 15A are connected in series across DC input capacitor C1A.

  That is, the DC input capacitors C1A and C1B are examples of a plurality of DC input capacitors connected in series to the output terminal of the bridge rectifier circuit. Unit converters 10A and 10B are unit converters connected to both ends of each of the plurality of DC input capacitors and provided in the same number as the number of DC input capacitors, and include semiconductor switching elements, transformers, and rectifier circuits. Is a unit converter including a plurality of unit converters connected in series between input high-voltage DC power supply terminals and having an output terminal connected in parallel to an input terminal of the choke input type filter circuit.

  Further, the diode 16A is reversely connected from the source electrode of the FET 12A toward the negative electrode (−) of the DC input capacitor C1A, and the diode 17A is connected from the drain electrode of the FET 15A toward the positive electrode (+) of the DC input capacitor C1A. It is connected.

  A rectifier circuit 20A is connected to the secondary winding 21A of the transformer 13A. The rectifier circuit 20A includes a rectifier diode 22A.

  If the choke input type filter circuit 30 common to the unit converters 10A and 10B is connected to the output terminal to which the rectifier circuit 20A and the rectifier circuit 20B are connected, a so-called double forward type converter is configured. The choke input filter circuit 30 includes a choke 31, a filter circuit capacitor 32, and a flywheel diode 23.

  Similarly, the unit converter 10B is a converter in which the FET 12B, the primary winding 14B of the transformer 13B, and the FET 15B are connected in series across the DC input capacitor C1B. Further, a diode 16B is reversely connected from the source electrode of the FET 12B toward the negative electrode (−) of the DC input capacitor C1B. A diode 17B is connected from the drain electrode of the FET 15B toward the positive electrode (+) of the DC input capacitor C1B.

  A rectifier diode 22B and a common flywheel diode 23 are connected to the secondary winding 21B of the transformer 13B.

  By the way, in the conventional example shown in FIG. 11, the unit converters 10a and 10b have choke input type filter circuits in their respective secondary rectifier circuits, and are connected in parallel on the output side of the filter circuits.

  However, in the first embodiment, the unit converters 10 </ b> A and 10 </ b> B are structurally different from the conventional example in that the unit converters 10 </ b> A and 10 </ b> B are connected in parallel by the flywheel diode 23 on the input side of the common choke input filter circuit 30.

  In the first embodiment, the unit converters 10A and 10B are connected to the DC output terminals O1 and O2 through the common choke input type filter circuit 30.

  If the control circuit 60 is a communication rectifier, the control circuit 60 detects the DC output voltage 50, and if it is a sputtering power supply, the control circuit 60 outputs the DC output current 41 or the output power that is the product of the DC output voltage 50 and the DC output current 41. In order to detect and perform constant voltage, constant current, and constant power control, a pulse width signal or a duty signal having the same on / off timing is sent as a drive signal to the FETs 12A, 15A, 12B, and 15B of the unit converters 10A and 10B.

  In the first embodiment, since the converters 10A and 10B are double forward type converters, the two FETs 12A and 15A of the converter 10A or the two FETs 12B and 15B of the converter 10B are turned on with the same signal for the same time. In the first embodiment, all four FETs 12A, 15A, 12B, and 15B in both converters 10A and 10B are turned on for the same time by the same control signal.

  That is, the choke input filter circuit 30 is an example of a choke input filter circuit including a common choke, a capacitor, and a flywheel diode. The unit converters 10A and 10B are unit converters including a semiconductor switching element, a transformer, and a rectifier circuit that are connected in series at both ends of a DC input capacitor. The unit converters 10A and 10B are connected in series between input high-voltage DC power supply terminals, These are examples of a plurality of unit converters connected in parallel to the input terminals of the choke input type filter circuit.

  The current detection means 40 and the DC output voltage 50 are examples of detection means for detecting the DC output current or DC output voltage of the choke input type filter circuit.

  The control circuit 60 controls the output voltage, the output current, or the output power of the choke input type filter circuit by simultaneously turning on and off the semiconductor switching elements in the plurality of unit converters, and the input current of the plurality of unit converters. This is an example of a control circuit that balances the input voltages of the plurality of unit converters by making them substantially equal.

  Next, the current balance in Example 1 will be described.

  FIG. 2 is a diagram illustrating an equivalent circuit 100E according to the first embodiment.

  In the equivalent circuit 100E of the first embodiment, unit converters 10A and 10B are connected to DC input capacitors C1A and C1B, respectively, and a common choke input filter circuit 30 is provided.

  In FIG. 2, the transformer is omitted, the FET of the primary circuit is connected in series with the rectifier diode of the secondary circuit, and the series connection of the DC input capacitors C1A and C1B is ignored. That is, the equivalent circuit 100E as described above is described because the purpose of the equivalent circuit only needs to explain that the input impedances of the unit converters 10A and 10B connected to the DC input capacitors C1A and C1B are equal.

  Next, the operation of the first embodiment will be described.

  FIG. 3 is a time chart illustrating the operation of the first embodiment.

  In the equivalent circuit 100E of the first embodiment, the unit converters 10A and 10B are connected in parallel with the flywheel diode 23 on the input side of the common choke input type filter circuit 30.

  The control circuit 60 detects parameters such as the DC output voltage 50 if the communication rectifier is used, and detects the DC output current 41 or the output power if the power source is a sputtering power supply. In order to perform control, a pulse width signal or a duty signal is sent as a drive signal to the FETs of the unit converters 10A and 10B.

  Next, in the first embodiment, the switching characteristics of the four FETs provided in the unit converters 10A and 10B vary, and the ON time of the FET of the unit converter 10A is the unit converter for the same ON signal. Consider a case where there is a 10% duty difference that is longer than the ON time of the 10B FET.

  For example, if the voltage across the DC input capacitor C1A and the DC input capacitor C1B is the same immediately after being turned on, if the ON time of the FET of the unit converter 10A is larger by Δt than the ON time of the unit converter 10B, Δt For the time, the diode 19B is turned off, the diode 19A is turned on, and the current continues to be discharged from the DC input capacitor C1A, so that the voltage across the DC input capacitor C1A is lower than the voltage across the DC input capacitor C1B.

  At the beginning of the next ON, only the DC input capacitor C1B having a high voltage at both ends is discharged through the diode 19B, and the diode 19A also has a timing when the voltage at both ends of the DC input capacitor C1A and the voltage at both ends of the DC input capacitor C1B are balanced. When it is turned on, the DC input capacitor C1A also starts discharging, and during the time when there is a duty difference, the current continues to be discharged again from the DC input capacitor C1A.

  In this case, the voltage drop ΔV of the DC input capacitor C1B is ΔV = Ip × Δt / (capacity of the DC input capacitor C1A) because CV = IT.

  2 and 3, since the choke 31 is common, E1 = E2. In the Δt time, only the converter 10A discharges current.

  FIG. 4 is a diagram illustrating a simulation result in the first embodiment.

  Vch1 shown in FIG. 4 (1) is the voltage across the DC input capacitor C1A, Vch2 is the voltage across the DC input capacitor C1B, and the waveform shows that the voltage difference is as small as about 12V and is balanced. However, since two waveforms overlap each other, they appear as one waveform. 4 (2) and 4 (3) are diagrams showing the voltage and current of the choke 31, respectively. FIG. 4 (4) shows the currents Ip1 and Ip2 of the FETs 12A and 12B. When the FET is on, the current is supplied only from the higher voltage, and the current from both FETs is supplied after the voltage is balanced. . When the FET is off, current is supplied only from the FET having a long pulse width, and a slight voltage difference occurs. The two parts are different, and what appears to be one is the time when the two waveforms overlap.

  If the simulation of the embodiment shown in FIG. 4 and the simulation of the conventional example shown in FIG. 13 are seen, a large difference occurs in the voltage difference between both ends of the DC input capacitor C1A and the DC input capacitor C1B as a result of measurement under the same conditions. I understand. According to the simulation of the embodiment (FIG. 4), the switching frequency of the converter is 50 kHz, the duty is 0.5, Δt is 1 μs, Ip is 22.5 A × 0.25 = 5.625 A, and the DC input capacitor When the capacitance of C1A is 1 μF, ΔV = 5.625V, which is a voltage difference of about 12V. On the other hand, in the conventional example, a voltage difference of about 40V occurred.

  Further, under the conditions actually used, the DC input capacitor C1A normally has a capacity of several hundreds μF or more for the purpose of smoothing the commercial voltage. In this simulation, an unbalance of the voltage difference occurs only 1/100 or less.

  In the first embodiment, basically, two input capacitors are connected in series across the input DC power supply, and two converters composed of low-voltage FETs are respectively connected to both ends of the input capacitor. In addition, the output of the secondary rectifier circuit of each converter is connected in parallel, and the control signal supplied to the FET of each converter is made the same signal, thereby balancing the voltage of the two input capacitors, and A switching semiconductor element such as an FET is used with a breakdown voltage lower than the voltage.

  Therefore, in the first embodiment, n input capacitors are connected in series across the input DC power supply, and n inverters configured by low-voltage FETs are respectively connected to both ends of the input capacitor, and The control signal supplied to each inverter is controlled so that the input voltage of each inverter is approximately 1 / n of the input DC power supply voltage, and the voltage balance of the n input capacitors connected in series is adjusted. Also good.

  Further, the first embodiment is a single-phase AC input converter circuit, but the first embodiment can be applied to a three-phase case.

  In the first embodiment, one flywheel diode 23 is provided, but the flywheel diode 23 may be provided for each of the unit converters 10A and 10B.

  FIG. 5 is a circuit diagram showing a power conversion apparatus 200 that is Embodiment 2 of the present invention.

  The power conversion device 200 is a device to which a power factor correction circuit (PFC circuit) 70 is added in the power conversion device 100, and the power factor improvement connected between the U-V lines in one single-phase block. A circuit 70 and a DC-DC conversion circuit 5 are included.

  The power factor correction circuit 70 has a bridge rectifier BR1 connected between the U and V lines, and a boost choke coil 81 and an FET 82 are connected in series to the output of the bridge rectifier BR1, and in parallel with the FET 82. In addition, a series circuit of a backflow prevention diode 83 and DC input capacitors C1A and C1B is connected. When the unit converters 10A and 10B are stopped, balance resistors R1 and R2 are connected in parallel in order to compensate for imbalance due to leakage current of the DC input capacitors C1A and C1B.

  The output voltage of the power factor correction circuit 70 is about 800 V, which is higher than the maximum peak value of the input power supply voltage (AC 400 V to 480 V). Since the normal electrolytic capacitor has a withstand voltage of about 450 V, the DC input capacitors C1A and C1B for smoothing the rectified voltage have two electrolytic capacitors with a withstand voltage of 450 V connected in series.

  Unit converters 10A and 10B having the same configuration are connected to the DC input capacitors C1A and C1B. Since they have the same configuration, the suffix A is added to the components of the unit converter 10A, and the suffix B is added to the components of the unit converter 10B. Each DC input capacitor C1A, C1B is a component of the power factor correction circuit 70 and also a component of the unit converters 10A, 10B.

  The power factor correction circuit 70 includes a boost chopper including the DC input capacitor between an input high-voltage DC power supply terminal and input terminals of the plurality of unit converters connected in series. It is an example of the power factor improvement circuit comprised by the circuit.

  FIG. 6 is a circuit diagram showing a power conversion apparatus 300 that is Embodiment 3 of the present invention.

  The power conversion device 300 is an embodiment in which a single forward converter is employed in the power conversion device 200.

  In power converter 200, unit converters 103A and 103B are provided instead of unit converters 10A and 10B.

  Further, a control circuit 61 is provided instead of the control circuit 60, and the control circuit 61 outputs the same control pulse for controlling the FETs 12A and 12B.

  FIG. 7 is a circuit diagram showing a power conversion apparatus 400 that is Embodiment 4 of the present invention.

  The power conversion device 400 is an embodiment that employs a half-bridge converter in the power conversion device 200.

  In power converter 200, unit converters 104A and 104B are provided instead of unit converters 10A and 10B.

  FIG. 8 is a circuit diagram showing a power conversion apparatus 500 that is Embodiment 5 of the present invention.

  The power conversion device 500 is an embodiment in which a half-bridge converter is employed in the power conversion device 200.

  In power converter 200, unit converters 105A and 105B are provided instead of unit converters 10A and 10B.

  FIG. 9 is a circuit diagram showing a power conversion apparatus 600 that is Embodiment 6 of the present invention.

  The power conversion device 600 is an embodiment in which a full-bridge converter is employed in the power conversion device 200.

  In power converter 200, unit converters 106A and 106B are provided instead of unit converters 10A and 10B.

  A rectifier circuit 20A is connected to the secondary winding 21A of the transformer 13A. The rectifier circuit 20A includes a rectifier diode 22A. A rectifier circuit 20B is connected to the secondary winding 21B of the transformer 13B. The rectifier circuit 20B includes a rectifier diode 22B.

  FIG. 10 is a circuit diagram showing a power conversion apparatus 700 that is Embodiment 7 of the present invention.

  The power conversion device 700 is an embodiment in which a full-bridge converter is employed in the power conversion device 200.

  In power conversion device 700, unit converters 107A and 107B are provided instead of unit converters 10A and 10B.

  A rectifier circuit 20A is connected to the secondary winding 21A of the transformer 13A. The rectifier circuit 20A includes rectifier diodes 22A and 23A. A rectifier circuit 20B is connected to the secondary winding 21B of the transformer 13B. The rectifier circuit 20B includes rectifier diodes 22B and 23B.

  In the power conversion circuits 400, 500, 600, and 700 shown in FIGS. 7 to 10, when the transformer secondary voltage is a full-wave converter with positive and negative symmetry, during the idle period when all the primary side FETs are turned off. Since all the diodes are turned on at the same time and the choke current is shunted, and the flywheel diode is not essential, the description of the flywheel diode is omitted in FIGS.

  Each of the unit converters is one of a single forward converter, a double forward converter, a half bridge voltage converter, and a full bridge voltage converter.

  According to each of the above-described embodiments, even if the fluctuation of the DC voltage obtained by rectifying a commercial high-voltage AC voltage such as a 400V system is taken into consideration, it is like an inexpensive FET having a lower withstand voltage and a lower forward voltage drop than its maximum value. A power conversion device can be configured using a simple switching semiconductor element, and high frequency, high efficiency, and low cost can be achieved. Therefore, high frequency, high efficiency, and low cost can be achieved.

  In addition, according to the above-described embodiment, even if the fluctuation of the DC voltage obtained by rectifying the commercial high-voltage AC voltage such as 400V system is taken into consideration, the FET with a low withstand voltage lower than the maximum value and having a low forward voltage drop can be obtained. When a power converter is configured using such switching semiconductor elements, a circuit for controlling the input voltage balance of a plurality of series-connected converters connected in series between HVDC input terminals is simple.

100: power conversion circuit,
10A, 10B ... Unit converter,
20: Rectifier circuit,
23 ... Flywheel diode,
30 ... Choke input type filter circuit,
40: Current detection circuit,
41 ... DC output current,
50: DC output voltage,
60 ... control circuit,
200, 300, 400, 500, 600, 700... Power conversion circuit.

Claims (3)

A choke input type filter circuit comprising a common choke, a capacitor and a flywheel diode;
A plurality of DC input capacitors connected in series between the input high voltage DC power supply terminals;
A unit converter connected to both ends of each of the plurality of DC input capacitors and provided as many as the number of the DC input capacitors, a unit converter including a semiconductor switching element, a transformer, and a rectifier circuit, A plurality of unit converters whose output terminals are connected in parallel to the input terminals of the choke input filter circuit;
Detecting means for detecting a DC output voltage or a DC output current of the choke input filter circuit;
By simultaneously turning on and off the semiconductor switching elements in the plurality of unit converters, the output voltage or output current or output power of the choke input type filter circuit is controlled, and the input currents of the plurality of unit converters are made substantially equal. A control circuit for balancing the input voltages of the plurality of unit converters;
The power converter characterized by having. In claim 1,
A boost chopper including the DC input capacitor is configured between the input high-voltage DC power supply terminal and the input terminals of the plurality of unit converters connected in series, and is configured by the boost chopper and a bridge rectifier circuit. A power conversion device comprising a power factor correction circuit. In claim 1 or claim 2,
The unit converter is any one of a single forward converter, a double forward converter, a half-bridge voltage converter, and a full-bridge voltage converter.

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