JP5128355B2 - Random number generator - Google Patents

Description

  The present invention relates to a random number generation element and a random number generation method using random behavior of elementary charges.

  The random number sequence is a sequence of random numbers that cannot be predicted, and is an important element in calculation simulation and encryption technology. Randomness is random and unpredictable can be said to be a good random number, and a high-quality random number sequence is required for calculation simulation and encryption technology.

  There are two methods for generating a random number sequence, one using a calculation algorithm and the other using a physical phenomenon. A method using a calculation algorithm has an advantage that a random number can be easily generated using a computer, but regularity is generated, so that the quality as a random number is poor. A random number generated by a method using a calculation algorithm is called a pseudo-random number. The quality of pseudo-random numbers increases if a precise calculation algorithm is used, but the computer must have a higher capacity.

  The method using physical phenomena uses essentially random phenomena such as radioactive decay, cosmic rays, resistance and noise of diodes, and can generate high-quality random numbers. A random number generated by a method using this physical phenomenon is called a physical random number. However, the physical random number requires a circuit for converting those signals into signals that can be used by a computer. For example, when using diode noise, a signal amplifier, an analog-digital conversion circuit, a threshold element, and the like are required. Therefore, even if the physical random number itself generates a high-quality random number, it is not guaranteed that the circuit-processed signal is a good-quality random number. Even if an attempt is made to generate a random number at a higher speed, the performance of the circuit is restricted. In addition to the quality of such random numbers, there is a disadvantage in use that the power consumption and size of the entire circuit is increased.

  As an element for solving the disadvantages of these physical random numbers, an element using a single electron has been reported (for example, see Non-Patent Document 1). 19A is a plan view of the random number generator disclosed in Non-Patent Document 1, FIG. 19B is a cross-sectional view taken along line AA ′ of FIG. 19A, and FIG. 19C is a random number generator. FIG. 19D is a diagram showing the change over time of the conduction channel resistance, which is the electrical characteristic of the random number generation element, in the energy band diagram along the line AA ′. 19A to 19D, 100 is an insulator layer, 101 is a semiconductor layer, 102 is a conduction channel, 103 is an energy pocket, 104 is a potential of the conduction channel 102, 105 is a potential of the energy pocket 103, 106 is an electron, R 1 is a conduction channel resistance when the electron 106 is not in the energy pocket 103, and R 2 is a conduction channel resistance when the electron 106 is in the energy pocket 103.

  The random number generating element disclosed in Non-Patent Document 1 is an element having a semiconductor layer 101 with an uneven surface on an insulator layer 100 as shown in FIGS. 19A and 19B. A conductive channel 102 is randomly formed in the semiconductor layer 101. An energy pocket 103 that traps a single electron 106 near the conduction channel 102 is also formed. When the energy pocket 103 is adjacent to the conduction channel 102, electrons 106 enter and leave the energy pocket 103 from the conduction channel 102 as shown in FIG. 19C, so that the conduction channel 102 as shown in FIG. The resistance changes, and the change can be used as a random number. Since the timing at which a single electron enters and exits the energy pocket 103 is completely random, a high-quality random number can be generated. In addition, since the element structure is simple, the power consumption and size of the random number generation element can be reduced.

K. Uchida, T. Tanamoto, R. Ohba, S. Yasuda, S. Fujita, “Single-Electron Random-Number Generator (RNG) for Highly Secure Ubiquitous Computing Applications”, IEDM Tech. Dig., 2002, p. 177 -180

  However, the random number generating element disclosed in Non-Patent Document 1 has a problem in that it is difficult to control the element fabrication because it is necessary to randomly form conduction channels and energy pockets. In addition, there is a problem that control of random number generation and high-speed operation are difficult. As described above, the random number generator disclosed in Non-Patent Document 1 can generate a high-quality random number by using the random behavior of a single electron as a random number. In addition, high controllability and high-speed operation of random number generation are required.

  The present invention has been made to solve such problems, and its purpose is to provide a random number generation element and a random number generation method capable of realizing ease of element fabrication, high controllability of random number generation, and high-speed operation. The purpose is to do.

The random number generator of the present invention includes a first field effect transistor having a thin line channel and one gate, and a gate having a thin line channel and formed separately from the gate of the first field effect transistor. A second field effect transistor having a charge storage section connected to the thin line channel of the second field effect transistor and made of a conductor connected to the thin line channel of the first field effect transistor via a capacitor ; A differentiation circuit for differentiating the output of the first field effect transistor, and a flip-flop having the output of the differentiation circuit as a clock input are provided.
The random number generating element of the present invention is formed separately from a first field effect transistor having a thin line channel and one gate, and having a thin line channel made of an intrinsic semiconductor and the gate of the first field effect transistor. And a second field effect transistor having two gates, and a conductor connected to the thin line channel of the second field effect transistor and connected to the thin line channel of the first field effect transistor via a capacitor. And a differential circuit for differentiating the output of the first field effect transistor, and a flip-flop using the output of the differential circuit as a clock input .
The difference from the conventional random number generator is that it uses FETs to control and detect the movement of elementary charges, can use existing FET fabrication technology, and it enables high controllability and high-speed operation. The point is that the element structure is simple.

  According to the present invention, the first FET and the second FET of nanometer order are used, the elementary charge is injected into the charge storage unit by the gate voltage control of the second FET, and the charge storage unit is randomly selected. By detecting the incoming and outgoing elementary charges based on the change in the electrical characteristics of the first FET, the timing at which the elementary charges enter and exit the charge storage unit can be made a random number sequence, and a highly random (high quality) random number Can be generated. Further, in the present invention, the speed of random number generation can be easily controlled, and high-speed operation is also possible. Further, in the present invention, since the same technology as the silicon transistor can be used for the production technique and material of the random number generation element, not only the production is easy, but also low power consumption, reduction of the electron-emitting device, Expected to be consolidated.

  Further, in the present invention, by using a second FET having two gates, an intrinsic semiconductor can be used for the thin-line channel of the second FET. It can be controlled more precisely.

  In the present invention, a binary random number can be generated by providing a differentiating circuit for differentiating the output of the first FET and a flip-flop using the output of the differentiating circuit as a clock input.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an equivalent circuit diagram showing the configuration of a random number generation element according to the first embodiment of the present invention, FIG. 2A is a plan view of the random number generation element of FIG. 1, and FIG. 2A is a cross-sectional view taken along line AA ′ in FIG. 2A, and FIG. 2C is a cross-sectional view taken along line BB ′ in FIG. Note that in FIG. 2A, the control gate, the thin channel, and the like under the insulating film are seen through.

  The random number generating element of the present embodiment is connected to a field effect transistor (hereinafter referred to as FET) 1, FET 2, an electron reservoir 3 connected to the source electrode S2 of FET 2, and a drain electrode D2 of FET 2. The charge storage unit 4 is capacitively connected to the thin channel CH1 of the FET1. In the present embodiment, the charge accumulated in the charge accumulation unit 4 and the charge flowing in the FETs 1 and 2 are electrons, but accumulation is performed by reversing the polarity of the applied voltage as in the ninth embodiment described later. Holes may be used as the generated charge or the flowing charge.

  The circuit configuration shown in FIG. 1 includes, for example, a silicon substrate 8, an insulating film 9 made of silicon oxide or the like on the silicon substrate 8, and an insulating film 9, as shown in FIGS. It is manufactured using an SOI (Silicon On Insulator) substrate made of a silicon film. The thin channel CH1 of FET1, the drain electrode D1 of FET1, the source electrode S1 of FET1, the electron reservoir 3, the thin channel CH2 of FET2, the drain electrode D2 of FET2, the source electrode S2 of FET2, and the charge storage unit 4 It is formed by processing the upper silicon film. The fine line channel CH1, the drain electrode D1, and the source electrode S1 of the FET 1 are integrally formed, and the electron reservoir 3, the source electrode S2, the thin line channel CH2, the drain electrode D2, and the charge storage part 4 of the FET 2 are integrally formed.

A gate electrode (referred to herein as a control gate CG1) is formed on the thin line channel CH1 of the FET 1 with an insulating film 10 made of, for example, silicon oxide interposed therebetween. Note that it is not essential to form the control gate CG1 above the FET1, and it may be formed in the same plane as the FET1.
A gate electrode (referred to herein as a control gate CG2) of the FET 2 is formed on the thin channel CH2 of the FET 2 with the insulating film 10 interposed therebetween. The control gates CG1 and CG2 may be formed using a conductor such as metal, amorphous silicon, or polysilicon. The charge accumulating section 4 is formed in a portion of the fine silicon line integral with the fine line channel CH2 of the FET 2 that protrudes from the position of the control gate CG2 toward the fine line channel CH1 side of the FET 1.

  The charge storage unit 4 is connected to the thin line channel CH1 of the FET 1 through the capacitor 5 constituted by the insulating film 10. The control gate CG1 is connected to the thin line channel CH1 of the FET 1 through the capacitor 6 constituted by the insulating film 10, and is further connected to the charge storage unit 4 through the capacitor 7 constituted by the insulating film 10.

  The design sizes of the charge storage unit 4 and the FET 2 are 10 nm or more and 60 nm or less in both the width (FIG. 2C, left-right direction) and thickness (FIG. 2C, vertical direction) of the charge storage unit 4 and the thin wire channel CH2. It is desirable to be. Further, the length of the portion where the fine line silicon integral with the fine line channel CH2 protrudes from the control gate CG2 to the fine line channel CH1 side of the FET 1 (the length from the right end of CG2 to the right end of the charge storage unit 4 in FIG. 2B). Is 10 nm or more and 1 μm or less.

  As for the cross-sectional dimension of the control gate CG2, the width (FIG. 2B, left-right direction) and thickness (FIG. 2B, vertical direction) are both several tens of nm. As shown in FIG. 2C, the control gate CG2 may be formed so as to surround the thin line channel CH2 of the FET2. By surrounding the thin-line channel CH2, the movement of elementary charges using the FET 2 can be effectively controlled. Here, the elementary charge means one electron or hole.

  The design size of the FET 1 is such that the width (FIG. 2B, left-right direction) and thickness (FIG. 2B, vertical direction) of the thin-line channel CH1 are both 10 nm to 60 nm and the length of the thin-line channel CH1 (FIG. 2 ( A) the vertical direction) is preferably 10 nm or more and 500 nm or less. However, the size of the FET 1 is not essential. The distance between the thin wire channel CH1 of the FET 1 and the charge storage unit 4 is preferably 1 nm or more and 100 nm or less.

Next, a method for detecting electrons accumulated in the charge accumulation unit 4 using the FET 1 will be described. Electrons are accumulated through the FET2 from the electronic reservoir 3 to the charge accumulation unit 4 in the manner described below, with the accumulation of the electrons, characteristic of the drain current I _d of the FET1, the voltage of the control gate CG1 as shown in FIG. 3 _Shifting in the positive direction with respect to V _cg1 according to the amount of charge. At this time, when the voltage V _cg1 of the control gate CG1 is fixed and the drain current I _d is detected by a detection circuit (not shown), the current changes according to the number of electrons, so that the number of electrons in the charge storage unit 4 can be detected. it can.

As is clear from FIG. 3, the relationship between the number of electrons and the detected current flowing through the FET 1 can be adjusted by the voltage V _cg1 applied to the control gate CG1. In order to accurately detect the number of electrons, the voltage V _cg1 may be set to increase the transconductance (differential value of I _d / V _cg1 ) of the FET 1. Without using the control gate CG1, the relationship between the number of electrons and the detected current flowing through the FET 1 can be adjusted by the shape of the silicon thin wire and the concentration of impurities doped therein.

Next, the principle that single electrons enter and exit the charge storage unit 4 will be described. 4A is a plan view of the random number generation element, FIGS. 4B to 4D are diagrams illustrating how electrons enter and exit the charge storage unit 4, and FIG. 5 is a random number generation characteristic of the random number generation element. there is a graph showing a temporal change of the drain current I _d of the FET1. 4B to 4C show the behavior of electrons in the direction along the line AA ′ in FIG. 4A, and the vertical axis shows energy. Reference numeral 40 denotes electrons, and 41 denotes an energy barrier.

As shown in FIG. 4A, the charge storage unit 4 has a structure connected to the thin line channel CH2 of the FET2.
When the FET 2 is turned off by a voltage V _cg2 applied to the control gate CG2 from a gate voltage application circuit (not shown), an energy barrier 41 is provided in the thin line channel CH2 of the FET 2 below the control gate CG2 as shown in FIG. Is formed. As a result, the charge storage unit 4 and the electron storage unit 3 are electrically disconnected.

When the FET 2 is turned on by the voltage V _cg2 applied to the control gate CG2 from the gate voltage application circuit, the electrons 40 are supplied from the electron reservoir 3 to the charge accumulator 4, and the Fermi of the electron reservoir 3 and the charge accumulator 4 are supplied.・ Energy is available. Next, when the FET 2 is turned off again, the charge storage unit 4 and the electron storage unit 3 are electrically disconnected, and electrons 40 are stored in the charge storage unit 4. At this time, the electrons 40 reciprocate between the charge accumulating unit 4 and the electron accumulating unit 3 over the energy barrier 41 of the thin channel CH2 by the surrounding thermal energy. Since the reciprocating motion of the electrons 40 occurs at a completely random timing, the number of electrons in the charge storage unit 4 changes randomly. By detecting this random change in the number of electrons over time with the FET 1 as described above, the element of the present embodiment functions as a random number generating element.

The amount of change in the number of electrons in the charge storage unit 4 is determined by the energy change amount Ec and thermal energy Et when a single electron is stored in the charge storage unit 4, and is about 1 + 4 Et / Ec. Note that Ec is e ² / 2C (e is the elementary charge amount, C is the total capacitance of the charge storage unit 4), Et is kT (k is the Boltzmann constant, and T is the absolute temperature). Therefore, the amount of change in the number of electrons can be controlled by structurally controlling the total capacitance C of the charge storage unit 4. Also, the amount of change in the number of electrons can be controlled by the height of the energy barrier 41 of the thin channel CH2 formed by the voltage V _cg2 applied to the control gate CG2. A change in the number of electrons of 1 is desirable because the circuit configuration can be simplified, but is not essential.

FIG. 5 shows an operation example of the random number generation element of this embodiment. According to FIG. 5, the drain current I _{d of the} FET 1 changes in a binary manner, which means that a single electron enters and exits the charge storage unit 4. Moreover, since the timing at which electrons enter and exit the charge storage unit 4 is random, it can be seen that the device is operating as a random number generating element. Since the timing at which electrons enter and exit the charge storage unit 4 can be accelerated by using the control gate CG2 to lower the energy barrier 41 of the thin wire channel CH2, the controllability and high speed operation are easy.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 6 is a circuit diagram showing a configuration of a random number generating element according to the second embodiment of the present invention. The random number generation element according to the present embodiment is different from the random number generation element according to the first embodiment in that the current source 11, one input terminal is connected to the source electrode S1 of the FET1, and another input terminal is the current source. 11 and a current comparator 12 connected to 11 are added. Figure 7 (A) is a diagram showing a time variation of the drain current I _d of FET1, FIG. 7 (B) is a random number generation characteristics, a graph showing a temporal change of the output Out of the current comparator 12.

When electrons are moved in and out of the charge storage unit 4 by the method described in the first embodiment, a plurality of electrons may enter and leave the charge storage unit 4 as shown in FIG. When the number of electrons to and from the charge accumulating portion 4 is odd, and supplies the average value of the drain current I _d of the FET1 and I _c, relative to the current source 11 is a current comparator 12, the current I _c as a reference signal . The current comparator 12 compares the drain current I _{d of the} FET ₁ with the current I _c of the current source 11, outputs an “H” level output Out when I _d > I _c , and outputs “H” when I _d <I _c . The output Out of “L” level is output. Thus, as shown in FIG. 7B, the output Out of the current comparator 12 can generate a binary random number.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 8 is a circuit diagram showing a configuration of a random number generating element according to the third embodiment of the present invention. The random number generation element according to the present embodiment is different from the random number generation element according to the first embodiment in that the current sources 13 and 14, one input terminal is connected to the source electrode S1 of FET1, and another input terminal is A current comparator 15 connected to the current source 13 and having another input terminal connected to the current source 14 is added. 9A is a diagram showing the time change of the drain current I _d of the FET 1, FIG. 9B is a diagram showing the time change of the internal output value Out _c1 of the current comparator 15, and FIG. 9C is the current comparator 15 It shows the time change of the internal output value Out _c2 of FIG. 9 (D) is a random number generator characteristics, a graph showing a temporal change of the output Out of the current comparator 15.

When electrons are moved in and out of the charge storage unit 4 by the method described in the first embodiment, an even number of electrons may enter and exit the charge storage unit 4 as shown in FIG. The current source 13 is a reference signal that satisfies 0 <I _C1 −I _d <δI _d , where δI _d is the amount of current that changes when the number of electrons entering and exiting the charge storage unit 4 is even. supplied to the current comparator 15 of the current I _C1 of the. The current source 14 supplies the current comparator 15 with a current I _c2 that is a reference signal that satisfies 0 <I _d −I _c2 <δI _d .

The current comparator 15 compares the drain current I _{d of the} FET ₁ with the current I _C1 of the current source 13, and becomes “H” level when I _d > I _C1 and becomes “L” level when I _d <I _C1. The internal output value Out _c1 is generated (FIG. 9B), and the drain current I _{d of the} FET ₁ and the current I _c2 of the current source 14 are compared. When I _d > I _c2 , it becomes “H” level. _{When d} <I _c2 , an internal output value Out _c2 that is at the “L” level is generated (FIG. 9C), and an exclusive OR (XOR) result of the internal output values Out _c1 and Out _c2 is output Out Output as. In this way, as shown in FIG. 9D, the output Out of the current comparator 15 can generate a binary random number.

Although the current comparators 12 and 15 are used in the second and third embodiments, the drain current I _{d of the} FET 1 is converted into a voltage signal, and the current sources 11, 13, and 14 are replaced with voltage sources. Thus, a similar operation can be realized by using a voltage comparator instead of the current comparators 12 and 15.

  Although the comparators are also used in the prior art using the above-described diode noise, the noise has a high quality because the number of contributing electrons is extremely large and the noise amplitude distribution (Boltzmann distribution) is widespread. It is difficult to obtain random numbers. On the other hand, in the second and third embodiments, the number of electrons entering and exiting the charge storage unit 4 is small, and the frequency of entering and exiting the charge storage unit 4 decreases rapidly as the number of electrons increases. High quality random numbers can be obtained.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 10 is a circuit diagram showing a configuration of a random number generating element according to the fourth embodiment of the present invention. The random number generation element according to the present embodiment is different from the random number generation element according to the first embodiment in that the differentiation circuit 16 whose input terminal is connected to the source electrode S1 of the FET 1 and the output of the differentiation circuit 16 as a clock input. And a D flip-flop 17 to be added. 11A is a diagram showing a time change of the drain current I _d of the FET 1, FIG. 11B is a diagram showing a time change of the output of the differentiating circuit 16, and FIG. 11C is a random number generation characteristic. It is a figure which shows the time change of the output Out of the flip-flop 17.

When a differentiating circuit 16 that outputs a signal proportional to the time differentiation of the drain current I _d of the FET 1 is connected to the source electrode S1 of the FET 1, the differentiating circuit 16 has a drain current I _d as shown in FIG. A positive signal is output at the instant when it increases, and a negative signal is output at the moment when the drain current I _d decreases.

  When the output of the differentiation circuit 16 is used as the clock input of the D flip-flop 17 as shown in FIG. 10 and the output bar Q of the D flip-flop 17 is connected to the input D, the D flip-flop 17 is instantly output at the moment when the output of the differentiation circuit 16 becomes positive. The output bar Q is inverted. In this way, as shown in FIG. 11C, the output bar Q of the D flip-flop 17 generates a binary random number.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. FIG. 12 is a circuit diagram showing a configuration of a random number generating element according to the fifth embodiment of the present invention. The random number generation element of the present embodiment is different from the random number generation element of the fourth embodiment in that a NOT circuit 18 whose input terminal is connected to the output of the differentiation circuit 16 and an output of the NOT circuit 18 as a clock input. And a D flip-flop 19 to be added. 13A is a diagram showing the time change of the drain current I _d of the FET 1, FIG. 13B is a diagram showing the time change of the output of the differentiating circuit 16, and FIG. 13C is a random number generation characteristic. It is a figure which shows the time change of the output Out of the flip-flop 19.

In the present embodiment, a D flip-flop 19 is added, and a signal obtained by logically inverting the output of the differentiation circuit 16 by the NOT circuit 18 is used as a clock input of the D flip-flop 19, and an input D and an output bar Q of the D flip-flop 17 are The input D and the output bar Q of the D flip-flop 19 are connected. As a result, the output bar Q of the D flip-flop 19 is inverted at the moment when the output of the differentiating circuit 16 changes, that is, at the moment when the drain current I _{d of the} FET ₁ changes (FIG. 13C). Thus, in this embodiment, the operation speed can be doubled and generation of high-quality random numbers can be guaranteed.

[Sixth Embodiment]
Next, as a sixth embodiment of the present invention, the principle of random number generation using the case where a large number of electrons enter the charge storage unit 4 will be described with reference to FIGS. 14 (A) to 14 (D). Also in the present embodiment, the configuration of the random number generating element is the same as that of the first embodiment.
First, as in the first embodiment, the electron reservoir 3 and the charge storage unit 4 are electrically disconnected using the FET 2 (FIG. 14A). At this time, the number of electrons in the charge storage unit 4 is preferably zero, but is not essential.

Next, when the energy barrier 41 of the thin channel CH2 is lowered by the voltage V _cg2 applied to the control gate CG2 from a gate voltage application circuit (not shown), the electrons 40 are stored in the electron reservoir 3 by the thermal energy as shown in FIG. The charge storage unit 4 is entered. The electrons 40 accumulate one after another until the Fermi energy of the charge accumulating unit 4 becomes the same as the Fermi energy of the electron accumulating unit 3 (FIG. 14C). Then, as shown in FIG. _14D , when the electrons 40 are _fully accumulated in the charge accumulating unit 4, the FET 2 is turned on by the voltage V _cg2 applied to the control gate CG2, and the voltage of the electron accumulating unit 3 is changed. By increasing the number, the electrons 40 of the charge storage unit 4 can be driven out. The state in which the electrons 40 enter the charge storage unit 4 is detected using the FET 1.

An example of the operation result is shown in FIG. In FIG. 15, 150 is a characteristic when the energy barrier 41 of the thin wire channel CH <b> 2 is increased to make it difficult for electrons to enter the charge accumulation unit 4, and 151 is a low energy barrier 41 to facilitate entry of electrons into the charge accumulation unit 4. Shows the characteristics. According to FIG. 15, the drain current I _{d of the} FET 1 decreases with the same amount of change, which means that a single electron is in the charge storage unit 4. The timing δt at which electrons enter is always random, and the average value can be controlled by the height of the energy barrier formed by the control gate CG2 (two lines in FIG. 15).

[Seventh Embodiment]
Next, a seventh embodiment of the present invention will be described. FIG. 16 is a circuit diagram showing a configuration of a random number generation element according to the seventh embodiment of the present invention. The random number generation element according to the present embodiment is different from the random number generation element according to the sixth embodiment in that the differentiation circuit 16 has an input terminal connected to the source electrode S1 of the FET 1 and the input terminal serves as an output of the differentiation circuit 16. A connected NOT circuit 20 and a D flip-flop 17 using the output of the NOT circuit 20 as a clock input are added.

  By combining the differentiation circuit 16 and the D flip-flop 17 with the output of the FET 1 as in the fourth embodiment, the output Out of the D flip-flop 17 can generate a binary random number. Note that the NOT circuit 20 is not essential.

[Eighth Embodiment]
Next, an eighth embodiment of the present invention will be described. FIG. 17 is an equivalent circuit diagram showing the configuration of the random number generation element according to the eighth embodiment of the present invention, FIG. 18A is a plan view of the random number generation element of FIG. 17, and FIG. 18A is a cross-sectional view taken along line AA ′ in FIG. 18A, and FIG. 18C is a cross-sectional view taken along line BB ′ in FIG. Note that in FIG. 18A, the control gate, the thin line channel, and the like under the insulating film are seen through. In FIG. 17, reference numeral 21 denotes a capacitor constituted by the insulating film 10.

  This embodiment shows a case where one gate electrode is further added to the FET 2 in the random number generating elements of the first to seventh embodiments. In the present embodiment, the control gate CG3 is formed on the thin line channel CH2 and the control gate CG2 of the FET 2, and the thin line channel CH2 of the FET 2 below the control gate CG3 is an intrinsic semiconductor.

By applying a positive voltage V _cg3 to the control gate CG3 from a gate voltage application circuit (not shown), the intrinsic semiconductor channel CH2 can be inverted, so that the same operation as in the first to seventh embodiments is possible. Become. In the present embodiment, by using the thin-line channel CH2 of the FET 2 as an intrinsic semiconductor, the movement of elementary charges entering and exiting between the electron reservoir 3 and the charge storage unit 4 can be controlled more precisely. The control gates CG3 and CG1 can be shared by the same gate.

  FIG. 17 shows only the configuration corresponding to the first embodiment. However, by adding the circuit added in the second to seventh embodiments to the configuration of FIG. It goes without saying that the same configuration and operation as in the seventh embodiment can be realized.

[Ninth Embodiment]
In the first to eighth embodiments, holes may be used as the charge accumulated in the charge accumulation unit 4 or the charge flowing through the FETs 1 and 2. In order to use holes as electric charges, the voltage applied to the FETs 1 and 2 may be reversed.
In the first to ninth embodiments, a semiconductor made of silicon, for example, is used for the charge storage unit 4, but a conductor such as metal may be used.

  The present invention can be applied to a random number generation technique using a random behavior of elementary charges.

1 is an equivalent circuit diagram showing a configuration of a random number generation element according to a first embodiment of the present invention. It is the top view and sectional drawing of the random number generation element which concern on the 1st Embodiment of this invention. It is a figure which shows the drain current characteristic of the 1st field effect transistor in the 1st Embodiment of this invention. It is a top view of the random number generation element which concerns on the 1st Embodiment of this invention, and a figure which shows a mode that an electron goes in and out of a charge storage part. It is a figure which shows the random number generation characteristic of the random number generation element which concerns on the 1st Embodiment of this invention. It is a circuit diagram which shows the structure of the random number generation element which concerns on the 2nd Embodiment of this invention. It is a figure which shows the time change of the drain current of the 1st field effect transistor of the random number generation element which concerns on the 2nd Embodiment of this invention, and the figure which shows the random number generation characteristic of a random number generation element. It is a circuit diagram which shows the structure of the random number generation element which concerns on the 3rd Embodiment of this invention. The figure which shows the time change of the drain current of the 1st field effect transistor of the random number generation element which concerns on the 3rd Embodiment of this invention, the figure which shows the time change of the internal output value of a current comparator, and the random number of a random number generation element It is a figure which shows generation | occurrence | production characteristics. It is a circuit diagram which shows the structure of the random number generation element which concerns on the 4th Embodiment of this invention. The figure which shows the time change of the drain current of the 1st field effect transistor of the random number generation element which concerns on the 4th Embodiment of this invention, the figure which shows the time change of the output of a differentiation circuit, and the random number generation characteristic of a random number generation element FIG. It is a circuit diagram which shows the structure of the random number generation element which concerns on the 5th Embodiment of this invention. The figure which shows the time change of the drain current of the 1st field effect transistor of the random number generation element which concerns on the 5th Embodiment of this invention, the figure which shows the time change of the output of a differentiation circuit, and the random number generation characteristic of a random number generation element FIG. It is a figure which shows a mode that an electron goes in and out of a charge storage part in the 6th Embodiment of this invention. It is a figure which shows the time change of the drain current of the 1st field effect transistor of the random number generation element which concerns on the 6th Embodiment of this invention. It is a circuit diagram which shows the structure of the random number generation element which concerns on the 7th Embodiment of this invention. It is an equivalent circuit diagram which shows the structure of the random number generation element which concerns on the 8th Embodiment of this invention. It is the top view and sectional drawing of a random number generation element which concern on the 8th Embodiment of this invention. It is a figure which shows the top view, sectional drawing, energy band figure, and electrical property of the conventional random number generation element.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 2 ... Field effect transistor, 3 ... Electron storage part, 4 ... Charge storage part, 5-7, 21 ... Capacity, 8 ... Silicon substrate, 9, 10 ... Insulating film, 11, 13, 14 ... Current source, 12 , 15 ... current comparator, 16 ... differentiation circuit, 17, 19 ... D flip-flop, 18, 20 ... NOT circuit, CH1, CH2 ... fine channel, CG1, CG2, CG3 ... control gate, D1, D2 ... drain electrode, S1 , S2: Source electrode.

Claims (2)

A first field effect transistor having a thin wire channel and having one gate;
A second field effect transistor having a thin line channel and having one gate formed separately from the gate of the first field effect transistor;
A charge accumulating portion comprising a conductor connected to the fine line channel of the second field effect transistor and connected to the fine line channel of the first field effect transistor via a capacitor ;
A differentiating circuit for differentiating the output of the first field effect transistor;
A random number generating element comprising: a flip-flop having an output of the differentiating circuit as a clock input . A first field effect transistor having a thin wire channel and having one gate;
A second field effect transistor having a thin line channel made of an intrinsic semiconductor and having two gates formed separately from the gate of the first field effect transistor;
A charge accumulating portion comprising a conductor connected to the fine line channel of the second field effect transistor and connected to the fine line channel of the first field effect transistor via a capacitor ;
A differentiating circuit for differentiating the output of the first field effect transistor;
A random number generating element comprising: a flip-flop having an output of the differentiating circuit as a clock input .

Images