Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JP5134221B2 - Manufacturing method of semiconductor device - Google Patents
[go: Go Back, main page]

JP5134221B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
JP5134221B2
JP5134221B2 JP2006227744A JP2006227744A JP5134221B2 JP 5134221 B2 JP5134221 B2 JP 5134221B2 JP 2006227744 A JP2006227744 A JP 2006227744A JP 2006227744 A JP2006227744 A JP 2006227744A JP 5134221 B2 JP5134221 B2 JP 5134221B2
Authority
JP
Japan
Prior art keywords
semiconductor device
bump
manufacturing
collet
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006227744A
Other languages
Japanese (ja)
Other versions
JP2008053427A (en
Inventor
寛之 木村
聖明 門井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2006227744A priority Critical patent/JP5134221B2/en
Publication of JP2008053427A publication Critical patent/JP2008053427A/en
Application granted granted Critical
Publication of JP5134221B2 publication Critical patent/JP5134221B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231Shapes
    • H10W72/234Cross-sectional shape, i.e. in side view

Landscapes

  • Wire Bonding (AREA)

Description

本発明はバンプを有する半導体装置を半導体基板上に安定して移動できる製造方法および半導体装置に関する。   The present invention relates to a manufacturing method and a semiconductor device that can stably move a semiconductor device having bumps onto a semiconductor substrate.

近年の半導体装置は複雑な機能を備え、バンプなどの接続端子数はますます多くなり、また高度に集積化され、著しく小型化が進行している。一方では、半導体装置を安定して半導体基板上に確実に接続するためには、バンプなどの接続端子には、ある程度の大きさが必要である。そのため、半導体装置の大きさに比してバンプなどの接続端子の大きさが非常に大きくなっている。   In recent years, semiconductor devices have complicated functions, the number of connection terminals such as bumps has increased, and they have been highly integrated and have been remarkably miniaturized. On the other hand, in order to connect the semiconductor device stably and reliably on the semiconductor substrate, the connection terminals such as bumps need to have a certain size. Therefore, the size of connection terminals such as bumps is very large compared to the size of the semiconductor device.

そのため、移動や検査などのために、半導体装置を取り扱う場合、図3に示すように、バンプが形成された面を吸着コレットで吸着するなど、バンプに治具を接触させる方法によって行う。(例えば、特許文献を参照)
特開平11−274205号公報
Therefore, when a semiconductor device is handled for movement or inspection, as shown in FIG. 3, the surface on which the bump is formed is sucked with a suction collet, and a method of bringing the jig into contact with the bump is performed. (For example, see patent literature)
JP-A-11-274205

しかしながら、バンプの材質には、金などの貴金属類や半田などの低融点の金属材料が用いられることが多いが、これらの材料は比較的やわらかく、キズや変形が発生しやすいものが多い。よって吸着コレットには樹脂などの比較的柔らかい材料が用いられることが多い。以上のような構成で、半導体装置のバンプ部を吸着コレットによってピックアップし、半導体装置の移動や検査などを行うと、吸着コレットから半導体装置を離脱させる際に、吸着コレットとバンプが密着したまま保持され、離脱を確実に行わせることが困難な場合が発生する。これは吸着コレットを繰り返し使用すると、バンプとの接触により、柔らかい材料でできている吸着コレットの一部に凹部が形成され、吸着コレットとバンプの接触面積が大きくなり、スムーズに離脱できないからである(図3(b))。この問題は、半導体装置の移動を確実に行うことを困難にするだけでなく、さらに移動後に吸着コレットから離脱されなかった第1の半導体装置が次に移動されるべき第2の半導体装置上に重ねられることとなり、双方の半導体装置を破損するという事故に発展する可能性も有している。これらの不具合は半導体装置が小型、軽量化するに従い、発生頻度が増加する傾向がある。   However, the bump material is often a noble metal such as gold, or a low melting point metal material such as solder, but these materials are relatively soft and often prone to scratches and deformation. Therefore, a relatively soft material such as a resin is often used for the adsorption collet. With the above configuration, when the bump part of the semiconductor device is picked up by the suction collet and the semiconductor device is moved or inspected, the suction collet and the bump are held in close contact when the semiconductor device is removed from the suction collet. In some cases, it is difficult to ensure the withdrawal. This is because, when the suction collet is used repeatedly, a concave portion is formed in a part of the suction collet made of a soft material due to contact with the bump, and the contact area between the suction collet and the bump becomes large and cannot be removed smoothly. (FIG. 3B). This problem not only makes it difficult to reliably move the semiconductor device, but further, the first semiconductor device that has not been detached from the adsorption collet after the movement is placed on the second semiconductor device to be moved next. As a result, the semiconductor devices are likely to be accidentally damaged. These defects tend to increase in frequency as semiconductor devices become smaller and lighter.

本発明は、バンプを有する半導体装置を半導体基板上に安定して移動できる製造方法および半導体装置を提供することを目的とする。   An object of this invention is to provide the manufacturing method and semiconductor device which can move the semiconductor device which has a bump stably on a semiconductor substrate.

バンプの表面を粗面化することにより、吸着コレットとバンプの接触面積を減少させ密着性を低下させる。バンプの表面を粗面化するための第1の方法は、表面に細かな凹凸のある粗い面を備えた治具を押し当て、バンプに治具表面の凹凸を転写する方法である。バンプの表面を粗面化するための第2の方法は、バンプを融点以上の温度まで過熱、溶融することによって、バンプ表面に凹凸を生じさせる方法である。   By roughening the surface of the bump, the contact area between the suction collet and the bump is reduced and the adhesion is lowered. The first method for roughening the bump surface is a method of pressing a jig having a rough surface with fine irregularities on the surface and transferring the irregularities on the jig surface to the bumps. The second method for roughening the surface of the bump is a method for producing irregularities on the bump surface by heating and melting the bump to a temperature equal to or higher than the melting point.

上記のような手段を用いることで、バンプを有する半導体装置を半導体基板上に移動する際の吸着コレットと半導体装置の離脱を確実に行うことができ、半導体装置の移動及び検査の効率が向上する。   By using the means as described above, the suction collet and the semiconductor device can be reliably detached when the semiconductor device having bumps is moved onto the semiconductor substrate, and the efficiency of the movement and inspection of the semiconductor device is improved. .

吸着コレットと半導体装置の離脱が確実に行えない原因は、バンプと吸着コレットとの接触面積が大きく、密着しやすいためであるためであり、バンプの表面に凹凸を形成し、吸着コレットとの接触面積を減少させることで吸着コレットと半導体装置が密着したままになること防止し、半導体装置を吸着コレットから確実に離脱させることが可能になる。   The reason why the suction collet and the semiconductor device cannot be reliably detached is because the contact area between the bump and the suction collet is large and the contact is easy. By reducing the area, the adsorption collet and the semiconductor device can be prevented from remaining in close contact with each other, and the semiconductor device can be reliably detached from the adsorption collet.

まず、本発明の実施形態を図1に基づいて説明する。   First, an embodiment of the present invention will be described with reference to FIG.

半導体装置1の上面に、表面に凹凸形状が形成され、バンプ材料よりも硬質のバンプ表面粗面化治具4を配置する(図1(a))。次いで、バンプ表面粗面化治具4と半導体装置1のバンプ2を接触させ、押し当てることによってバンプ2の上表面に治具表面の凹凸形状を転写し、表面が凹凸形状のバンプ2Aを形成する。バンプには比較的軟質の材料を用いられることが多いため、治具4による転写は容易である(図1(b))。こうすることでバンプ2Aと吸着コレット3との接触面積が減少し、半導体装置1を吸着コレット3から確実に離脱させることが可能になる。(図1(c))
バンプの材料としては表面部分または全部の材質が、すず、または、すずを主な成分とする金属材料であることが望ましい。また、銀、銅、ビスマス、及び、亜鉛のうちの1つまたは複数を含有する材料であることが望ましい。あるいは、共晶点ではない組成比の合金であることが望ましい。
On the upper surface of the semiconductor device 1, a bump surface roughening jig 4 having an uneven shape formed on the surface and harder than the bump material is disposed (FIG. 1A). Next, the bump surface roughening jig 4 and the bump 2 of the semiconductor device 1 are brought into contact with each other to press the bump surface to transfer the uneven shape of the jig surface onto the upper surface of the bump 2 to form the bump 2A having an uneven surface. To do. Since a relatively soft material is often used for the bump, the transfer with the jig 4 is easy (FIG. 1B). By doing so, the contact area between the bump 2A and the suction collet 3 is reduced, and the semiconductor device 1 can be reliably detached from the suction collet 3. (Fig. 1 (c))
As a material for the bump, it is desirable that the surface portion or the entire material is tin or a metal material containing tin as a main component. In addition, a material containing one or more of silver, copper, bismuth, and zinc is desirable. Alternatively, an alloy having a composition ratio other than the eutectic point is desirable.

次に、本発明の第2の実施形態を図2に基づいて説明する。バンプが半田バンプである場合には、その構成材料は低融点金属であり、それを高温に加熱処理することにより表面に凹凸を持ったバンプ2Bを形成することできる。その手法は以下の通りである。   Next, a second embodiment of the present invention will be described with reference to FIG. When the bump is a solder bump, the constituent material is a low melting point metal, and the bump 2B having unevenness on the surface can be formed by heat-treating it to a high temperature. The method is as follows.

メッキ法または印刷法で形成された半田バンプの場合、まず、ウェットバックと呼ばれる高温加熱処理して半田を溶融し、溶融した半田の表面張力によりボール形状に成型する。次いで、再度ウェットバック処理をすることで表面に細かな凹凸ができ、表面が粗面化される。メッキ法で形成した半田バンプのウェットバック処理は通常、フラックスを塗布した状態で行うが、2度目のウェットバック処理の際にフラックスを塗布しない状態のままウェットバック処理を行うことで、より大きな効果を得ることができる。   In the case of a solder bump formed by a plating method or a printing method, first, the solder is melted by a high-temperature heat treatment called a wet back, and then molded into a ball shape by the surface tension of the melted solder. Next, by performing wet back treatment again, fine irregularities are formed on the surface, and the surface is roughened. Wet-back processing of solder bumps formed by plating is usually performed with flux applied, but a larger effect can be achieved by performing wet-back processing without applying flux during the second wet-back processing. Can be obtained.

ここで、本発明の方法は半田バンプの合金組成が所謂共晶点と一致していないことが必要である。共晶点との組成のずれ量は各合金成分比率の10%程度であっても十分である。   Here, the method of the present invention requires that the alloy composition of the solder bumps does not coincide with the so-called eutectic point. Even if the deviation of the composition from the eutectic point is about 10% of the ratio of each alloy component, it is sufficient.

例えば、Sn−Cu合金の場合では、Cu=0.7wt%が共晶点となるが、Cu=0.6wt%の組成比率の場合でも前記方法を用いることが可能である。2度目のウェットバック処理時の温度条件は、半田材料の組成比により異なるが、Snを主成分とした半田材料の場合、概ね半田材料の融点よりも少なくとも20℃程度の高温に加熱された後、30秒間で100℃程度の速度で冷却することが望ましい。   For example, in the case of a Sn—Cu alloy, Cu = 0.7 wt% is the eutectic point, but the above method can be used even when the composition ratio is Cu = 0.6 wt%. The temperature condition during the second wet-back process varies depending on the composition ratio of the solder material, but in the case of a solder material mainly composed of Sn, after being heated to a temperature approximately at least 20 ° C. higher than the melting point of the solder material. It is desirable to cool at a rate of about 100 ° C. for 30 seconds.

本発明の第1の実施形態に係る半導体装置の製造方法を示す模式的断面図 (a)粗面形成前の模式的断面図 (b)粗面形成時の模式的断面図 (c)コレット吸着時の模式的断面図Schematic cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention (a) Schematic cross-sectional view before formation of rough surface (b) Schematic cross-sectional view during formation of rough surface (c) Collet adsorption Schematic cross section of the hour 本発明の第2の実施形態に係る半導体装置の模式的断面図Schematic sectional view of a semiconductor device according to a second embodiment of the present invention 従来の半導体装置のピックアップ動作を示す模式的断面図 (a)コレット吸着前の模式的断面図 (b)コレット吸着時の模式的断面図Schematic sectional view showing pick-up operation of conventional semiconductor device (a) Schematic sectional view before collet adsorption (b) Schematic sectional view at the time of collet adsorption

符号の説明Explanation of symbols

1 半導体装置
2 バンプ
2A 表面に粗面化治具の模様がついたバンプ
2B 熱処理により表面に凹凸が形成されたバンプ
3 吸着コレット
3A 繰り返し使用により、バンプとの接触面に凹部ができた吸着コレット
4 バンプ表面粗面化治具
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Bump 2A Bump 2B with the surface of the roughening jig on the surface Bump 3 with bumps formed on the surface by heat treatment 3 Adsorption collet 3A Adsorption collet with concave portions on the contact surface with the bump by repeated use 4 Bump surface roughening jig

Claims (2)

バンプが形成された半導体装置の製造方法であって、
半田バンプを形成する工程と、
半田バンプにフラックスを塗布してから高温加熱処理を施す第1ウェットバック工程と、
フラックス無しに高温加熱処理を施す第2ウェットバック工程と、
を有する半導体装置の製造方法。
A method of manufacturing a semiconductor device having bumps formed thereon,
Forming solder bumps;
A first wet-back process in which a flux is applied to the solder bump and then a high-temperature heat treatment is performed;
A second wet-back process for performing high-temperature heat treatment without flux;
A method for manufacturing a semiconductor device comprising:
前記半田バンプはSnを主材料とし、前記第2ウェットバック工程は、前記半田バンプの融点よりも20℃の高温に加熱された後、30秒間で100℃の速度で冷却する温度条件によりなされる請求項1記載の半導体装置の製造方法。The solder bump is mainly composed of Sn, and the second wet back process is performed under a temperature condition in which the solder bump is heated to a temperature 20 ° C. higher than the melting point of the solder bump and then cooled at a rate of 100 ° C. for 30 seconds. A method for manufacturing a semiconductor device according to claim 1.
JP2006227744A 2006-08-24 2006-08-24 Manufacturing method of semiconductor device Expired - Fee Related JP5134221B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006227744A JP5134221B2 (en) 2006-08-24 2006-08-24 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006227744A JP5134221B2 (en) 2006-08-24 2006-08-24 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2008053427A JP2008053427A (en) 2008-03-06
JP5134221B2 true JP5134221B2 (en) 2013-01-30

Family

ID=39237194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006227744A Expired - Fee Related JP5134221B2 (en) 2006-08-24 2006-08-24 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP5134221B2 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08316235A (en) * 1995-05-22 1996-11-29 Fujitsu Ltd Method for manufacturing semiconductor device
JPH11214431A (en) * 1998-01-23 1999-08-06 Oki Electric Ind Co Ltd Electronic part and its manufacture
JP3752836B2 (en) * 1998-04-24 2006-03-08 カシオ計算機株式会社 Bonding method for electronic components
JP4089531B2 (en) * 2003-07-09 2008-05-28 富士通株式会社 Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
JP2008053427A (en) 2008-03-06

Similar Documents

Publication Publication Date Title
KR100555354B1 (en) A method of connecting a unified chip to a substrate package, a flip chip method, and a method of forming a contact point on the chip
TWI381462B (en) Direct die assembly using heated bond heads
KR100555395B1 (en) Flip-Chip Interconnect Using No-Clean Flux
US9070671B2 (en) Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing
TWI478255B (en) Solder bump cleaning before reflow
US10014272B2 (en) Die bonding with liquid phase solder
JP2007268613A (en) Diffusion soldering method
CN105938790A (en) Method for manufacturing semiconductor device
TWI497657B (en) Wire structure and its making method
US7534715B2 (en) Methods including fluxless chip attach processes
JPH10163213A (en) Semiconductor device manufacturing method and semiconductor device mounting method
US8713792B2 (en) Method of manufacturing a printed wiring board
JP2004327718A (en) Electronic component mounting method
JP5134221B2 (en) Manufacturing method of semiconductor device
JP5004549B2 (en) Method for mounting electronic component on substrate and method for forming solder surface
TWI647769B (en) Electronic package manufacturing method
JPH05218136A (en) Flip chip bonding method
JP4467260B2 (en) Bump formation method
US6509207B1 (en) Soldering method and apparatus for a chip and electronic devices
KR100952676B1 (en) Template for solder bump formation and manufacturing method thereof
JP2009194357A (en) Semiconductor device and manufacturing method thereof
JPH10321633A (en) Method of forming bump
JP2020512697A5 (en)
JP2007149846A (en) Manufacturing method of semiconductor device
TW201720258A (en) Solder pad and solder pad manufacturing method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090604

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20091105

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20091113

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20091225

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111227

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120223

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20121106

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20121109

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20151116

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5134221

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees