JP5136120B2 - Clamp test apparatus and clamp test method - Google Patents

Description

  The present invention relates to a test technique for causing a pseudo failure in a digital processing device, and in particular, by clamping a digital signal to a voltage level equal to or lower than a threshold to make the signal inactive, The present invention relates to a clamp test apparatus and a clamp test method that cause a general failure.

  Conventionally, as a technique for testing a digital processing apparatus, there is a technique for clamping a digital signal of a target portion on a printed board such as a mother board of a digital processing apparatus or a PCI card to a ground level (0 [V]). In this technology, a line connected to the ground is brought into contact with a clamp target site such as a via or a land on a printed board through which the digital signal to be clamped passes, and the digital signal is less than the threshold voltage. Clamp to the level and perform an operational test at the time of failure by generating a pseudo failure.

  Hereinafter, a test that clamps a digital signal to a voltage level lower than the threshold and causes a pseudo failure is referred to as a clamp test, and a device that generates a pseudo failure by clamping is referred to as a clamp test device. The digital signal becomes inactive when the voltage level is lower than a certain threshold, and at this time, a pseudo failure occurs in the digital processing device.

Japanese Patent Application Laid-Open No. H10-228707 describes a technique for bringing a probe into contact with a predetermined via and clamping to 0 [V] in a printed board test. Japanese Patent Application Laid-Open No. 2004-228667 describes a technique for generating a pseudo-fixed fault by driving a periodic current that repeats drive and drive stop for a certain period to a signal line of an electronic circuit device.
JP 2006-53043 A JP-A-5-274174

  FIG. 5 is a diagram for explaining the problems of the conventional printed board test. The technique disclosed in Patent Document 1 clamps a digital signal with a ground, and when an internal resistance is mounted in a printed board by a hybrid lamination technique (see FIG. 5A), a clamp test apparatus. Since there is also an internal resistance on the side, the digital signal could not be clamped to a voltage level below the threshold. This will be described with reference to the circuit example shown in FIG.

In the circuit shown in FIG. 5B, when the point A of the output signal of the IC is clamped by the ground level, the voltage level of the output signal (hereinafter referred to as the output voltage level) is Vo, and the internal resistance on the circuit side is Assuming that R ₁ is the internal resistance on the clamp testing device side and R ₂ , the output voltage level V _A at point _A is
V _A = Vo−Vo × R ₁ / (R ₁ + R ₂ )
It becomes. In the example of FIG. 5B, the specific values are Vo = 3.3 [V], R ₁ = 5 [Ω], and R ₂ = 5 [Ω]. Substituting
V _A = 3.3 [V] -3.3 [V] × 5 [Ω] / (5 [Ω] +5 [Ω])
= 1.65 [V]
It becomes.

At this time, if the threshold voltage level, which is the boundary between the activation and deactivation of the digital signal, is 1.6 [V], the output voltage level V _A at the point A is made less than the threshold by executing the clamp. Since it has not been removed, a pseudo error cannot be generated in the printed circuit board. FIG. 5C shows the waveform of the output signal before the clamp execution at this time and the waveform of the output signal after the clamp execution.

  An object of the present invention is to provide a technique for reliably deactivating a signal to be clamped by reliably dropping the voltage level of the signal to be clamped below a threshold.

  Clamping is performed by applying a negative voltage to the signal to be clamped. This ensures that even the voltage level of signals passing through vias and lands in printed circuit boards with internal resistance that could not be dropped below the threshold with conventional ground level application is clamped below the threshold. Can do.

  At this time, the negative voltage to be applied is generated using a negative voltage power source or a capacitor. In particular, if a capacitor is used to generate a negative voltage, clamping can be performed without applying a load to the power source of the clamp test apparatus due to overcurrent during clamping.

  In addition, the timing for applying a negative voltage to the signal to be clamped can be controlled. As a result, for example, even when it is desired to perform a clamp test with nanosecond accuracy, the clamp can be executed at an appropriate timing.

Specifically, a clamp test device that generates a pseudo failure in a test target device by clamping a voltage level of a clamp target portion in a test target device that does not have a negative voltage generation circuit includes means for generating a negative voltage. And a probe for applying the negative voltage generated by the means for generating the negative voltage to a signal whose voltage level is to be clamped. Thereby, the voltage level of the signal to be clamped can be reliably clamped below the threshold, and a pseudo failure can be reliably generated in the test target device.

  In the clamp test apparatus, the means for generating a negative voltage generates a negative voltage by accumulating electric charge in a capacitor. As a result, a negative voltage can be applied to a signal to be clamped without applying an overcurrent load to the power source of the clamp test apparatus during clamping.

  Further, the clamp test apparatus includes means for controlling the timing of applying the negative voltage generated by the means for generating the negative voltage to a signal whose voltage level is to be clamped. Thereby, clamping can be executed at an appropriate timing.

  By clamping the signal with a negative voltage, it becomes possible to reliably draw a signal having an influence of an internal resistance, which could not be drawn to a voltage level below the threshold, to a voltage level below the threshold. Therefore, it is possible to reliably generate a pseudo failure even for a digital processing device in which an internal resistance is mounted in a printed board by a hybrid lamination technique, which has not been able to reliably generate a pseudo failure in the past. .

  In addition, in order to generate a negative voltage, it is possible to prevent a load on the power source due to an overcurrent during clamping by using a capacitor instead of using a negative voltage power source.

  In addition, a clamp test can be performed at an appropriate timing by providing means for controlling the timing of applying a negative voltage to the signal to be clamped.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a functional block configuration example of the negative voltage clamp test apparatus according to the present embodiment. The negative voltage clamp test apparatus 10 clamps a digital signal with a negative voltage, so that a signal having an influence of internal resistance as shown in the example of FIG. 5 is reliably clamped to a voltage level lower than the threshold.

For example, in the example of the circuit shown in FIG. 5B, when clamping is performed with a negative voltage level of −3.3 [V] instead of 0 [V],
V _A = 3.3 [V]
− (3.3 [V] +3.3 [V]) × 5 [Ω] / (5 [Ω] +5 [Ω])
≒ 0 [V]
Thus, the voltage level of the signal can be lowered below the threshold.

  The negative voltage clamp test apparatus 10 includes a negative voltage generation unit 11, a relay switch control unit 12, a delay circuit unit 13, and a clamp execution trigger generation unit 14.

  The negative voltage generator 11 generates a negative voltage necessary for clamping the signal to be clamped to a voltage level lower than the threshold. As a method of generating a negative voltage, for example, there are a method of using a negative voltage power source and a method of using a capacitor. In the negative voltage generation unit 11 of the present embodiment, in particular, a negative voltage is generated using a capacitor.

  The relay switch control unit 12 receives a relay switch control instruction from the external control device 20 and performs control such as connection / disconnection of the relay switch of the negative voltage generation unit 11. Although not shown in FIG. 1, the negative voltage generation unit 11 of the present embodiment includes a relay switch that switches between charging of a capacitor and execution of clamping by the charged capacitor.

  The delay circuit unit 13 receives a relay switch control instruction from the external control device 20 at the same time as the relay switch control unit 12 and delays the operation of the relay switch in the negative voltage generation unit 11 to clamp the gate condition. The data is sent to the execution trigger generation unit 14. The gate condition is one of signals for controlling connection / disconnection between the minus voltage generation unit 11 and the clamp line in the clamp execution trigger generation unit 14. A clamp line is a probe that contacts a via or land through which a signal to be clamped passes in order to clamp the voltage level of the signal to be clamped.

  The clamp execution trigger generation unit 14 controls the timing at which a negative voltage is applied to a signal to be clamped. The clamp execution trigger generation unit 14 receives a clamp execution instruction from the external control device 20 and a relay switch drive completion signal as a gate condition from the delay circuit unit 13, and connects / disconnects the negative voltage generation unit 11 to the clamp line. Perform control such as cutting.

  FIG. 2 is a diagram showing a usage example of the negative voltage clamp test apparatus according to the present embodiment. In FIG. 2, a device under test 30 which is a device to be subjected to a clamp test is an image of a printed board of a digital processing device, and a small circle shown inside the device under test 30 represents a via.

  As shown in FIG. 2, when the device under test 30 is clamped using the negative voltage clamp test apparatus 10, one lead wire of the negative voltage clamp test apparatus 10 is connected to a GND (ground) 32, and the other The lead wire, that is, the clamp wire 15 is brought into contact with the via 31 to be clamped. The clamp target via 31 is a part to be clamped with a voltage level, and a signal passing through the clamp target via 31 is a signal to be clamped. In this state, if an instruction to execute clamping is issued to the minus voltage clamp test apparatus 10, a minus voltage can be applied to a signal passing through the point of the via 31 to be clamped.

  FIG. 3 is a diagram showing an example of the internal configuration of the negative voltage clamp test apparatus according to this embodiment. The example of the internal configuration of the negative voltage clamp test apparatus 10 shown in FIG. 3 is a detailed example of the functional block configuration of the negative voltage clamp test apparatus 10 shown in FIG. 1, but the circuit configuration is simply described. It is fastened.

  As shown in FIG. 3, the negative voltage clamp test apparatus 10 includes a negative voltage generation circuit 110, a relay switch drive circuit 120, a delay circuit 130, and a bus switch 140.

  A lead wire extending from the Side B side of the bus switch 140 is connected to the GND 32 of the device under test 30, and the clamp wire 15 is brought into contact with the via to be clamped 31.

  When charging of the capacitor C in the negative voltage generation circuit 110 is instructed by the relay switch control instruction from the external control device 20, the relay switch drive circuit 120 causes the relay switch a and the relay switch in the negative voltage generation circuit 110 to be charged. b is controlled so as to fall to the power source E side. In this state, the capacitor C is charged. As shown in FIG. 3, a negative charge is accumulated on the relay switch a side of the capacitor C, and a positive charge is accumulated on the relay switch b side.

  When the capacitor C is sufficiently charged and the relay switch ON is instructed by the relay switch control instruction from the external control device 20, the relay switch driving circuit 120 turns on the relay switch a in the minus voltage generation circuit 110. Control is performed so that the relay switch b is tilted to the side of the clamp line 15 and the side A of the bus switch 140. In this state, the bus switch 140 is still in a non-conductive state, that is, the state where the Side A and Side B of the bus switch 140 are disconnected. The relay switch ON indicates that the relay switch is controlled to be in a state where clamping can be performed.

  At the same time, the relay switch ON instruction from the external control device 20 is also sent to the delay circuit 130. The delay circuit 130 delays the time when the relay operation is completed and outputs a gate condition to the bus switch 140. For example, since several tens of milliseconds are expected from the start to completion of the relay operation, the gate condition signal is output in consideration of the time. In addition, since the discharge of the capacitor C due to the leakage current can be considered, it is necessary to design the delay circuit 130 so that the delay time does not become too long in consideration of the time.

  When the bus switch 140 is turned on by the clamp execution instruction from the external control device 20 and the gate condition from the delay circuit 130 and the bus switch 140 is in a conductive state, that is, the Side A and Side B of the bus switch 140 are connected. A negative voltage due to the charge of the charged capacitor C is applied to the signal passing through the clamp target via 31 of the device under test 30. Thereby, the voltage level of the signal in the clamp target via 31 can be clamped below the threshold.

  Note that the capacitance of the capacitor C used for applying the negative voltage may be logically calculated or may be experimentally determined. The appropriate capacitance of the capacitor C varies depending on the specifications of the digital processing device to be tested.

  When logically calculated, information such as the specifications of the digital processing device to be tested is necessary. However, even if the specifications of the digital processing device to be tested are known, it is not easy to calculate the capacity of the capacitor C suitable for the clamp test.

  As a method to obtain experimentally, for example, the negative voltage clamp test apparatus 10 is operated while confirming the signal waveform at the clamp target via 31 with an oscilloscope that measures and displays the voltage waveform, and the voltage level is thresholded. There is a method to check whether it has fallen below the hold. Prepare capacitors with a plurality of capacities in advance, perform a trial while exchanging the capacitors attached to the negative voltage clamp test device 10, and actually perform a clamp test on the capacitors for which the signal waveform obtained by the oscilloscope is considered optimal. It is sufficient to use the capacitor C used in the above.

  FIG. 4 is a sequence chart of the clamp test according to the present embodiment. The sequence chart of the clamp test shown in FIG. 4 is an example of the sequence chart of the clamp test by the negative voltage clamp test apparatus 10 shown in FIG.

  First, the capacitor C of the negative voltage generation circuit 110 is charged. At this time, the relay switch a and the relay switch b of the negative voltage generation circuit 110 are in a state of being tilted to the power source E side, and the bus switch 140 is in a non-conducting state, that is, a state in which SideA and SideB are disconnected. Since it is before the execution of clamping, the voltage level of the signal to be clamped exceeds the threshold, and the signal is in an active state.

After completion of charging capacitor C, the relay switch turned ON at time T _a, the relay switch a in the negative voltage generating circuit 110 to the clamp line 15 side, the relay switch b is reclined in SideA side of the bus switch 140. At this time, the bus switch 140 is still in a non-conducting state, that is, the state where Side A and Side B are disconnected. Since clamping is not yet performed at this time, the voltage level of the signal to be clamped exceeds the threshold, and the signal is in an active state. From this time, discharge of the capacitor C due to leakage current begins.

Bus switch 140 is turned ON by the clamp execution instruction and the gate condition at time T _b, the bus switch 140 is in a state in which the conductive state ie SideA and SideB are connected. At this time, a negative voltage is applied to the clamp target signal by the capacitor C, the voltage level of the clamp target signal becomes less than the threshold, and the signal becomes inactive.

  Thereafter, due to the discharge of the capacitor C, there is no voltage applied to the clamp target signal, and the clamping action is lost. However, this sequence is effective in the sense that a momentary clamp can be applied. If it is desired to execute the clamp test again, the capacitor C may be charged again. By charging the capacitor C, the clamp test can be performed as many times as necessary.

  Although the present embodiment has been described above, the present invention is not limited to this embodiment. For example, in this embodiment, a capacitor is used to generate a negative voltage. However, as described above, a negative voltage power source can also be used to generate a negative voltage.

  However, if clamping is performed using a negative voltage power supply, there is a possibility that a load will be applied to the power supply due to the overcurrent flowing, so the clamp testing device may fail. In addition, the negative voltage power supply requires a larger device configuration than the capacitor, which causes a cost problem. Also, if the power supply is used for other purposes, the power supply voltage drops when clamping is performed, and the circuit may not operate normally.

  Therefore, a method using a capacitor to generate a negative voltage is considered suitable. If a capacitor is used to generate a negative voltage, it is possible to prevent a load caused by an overcurrent during clamping. In addition, charging can be performed by using the power source originally provided in the clamp test apparatus, so that the circuit is not complicated compared to the case of using a negative voltage power source, and the power supply voltage does not drop during clamping. When applying a negative voltage due to the capacitor's charge, the voltage level at the point of application may not be constant, and a waveform may appear, but clamping can be performed in an instant and this will affect the target circuit. It is effective in the sense that

  Also, for example, in this embodiment, the relay switch ON instruction and the clamp execution instruction are issued separately, but a series of operations from the relay switch ON to the clamp execution is performed by one clamp execution instruction. Also good. In this case, a signal is sent simultaneously to the relay switch driving circuit 120, the delay circuit 130, and the bus switch 140 in response to the clamp execution instruction, and simultaneously with the output of the gate condition of the delay circuit 130 that allows for the switching time of the relay switch, The switch 140 is turned on and clamping is performed. Furthermore, a series of operations from capacitor charging to clamp execution may be performed by one clamp execution instruction.

  As described above, about several tens of milliseconds are expected from the start to completion of the relay operation. In contrast, a test that clamps the signal with nanosecond accuracy may be required. If a series of operations from the relay switch ON to the clamp execution is performed by one clamp execution instruction, a clamp test with nanosecond accuracy cannot be executed. Since the bus switch 140 can be operated in nanosecond units, the switching of the relay switch ON instruction After switching the relay switch, the bus switch 140 is turned on at an optimal timing according to the clamp execution instruction, so that the nanosecond accuracy clamp is performed. The test can be executed.

  Further, for example, in the present embodiment, the control instruction for the negative voltage clamp test apparatus 10 is issued from the external control apparatus 20, but the control instruction may be issued by the negative voltage clamp test apparatus 10. When it is necessary to perform a clamp test with nanosecond accuracy in accordance with the processing operation of the digital processing device to be tested, the digital processing device is used as the external control device 20 to control the negative voltage clamp test device 10. To.

It is a figure which shows the functional block structural example of the negative voltage clamp test apparatus by this Embodiment. It is a figure which shows the usage example of the negative voltage clamp test apparatus by this Embodiment. It is a figure which shows the example of an internal structure of the negative voltage clamp test apparatus by this Embodiment. It is a sequence chart of the clamp test by this Embodiment. It is a figure explaining the problem of the test of the conventional printed circuit board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Negative voltage clamp test apparatus 11 Negative voltage generation part 12 Relay switch control part 13 Delay circuit part 14 Clamp execution trigger generation part 15 Clamp line 110 Negative voltage generation circuit 120 Relay switch drive circuit 130 Delay circuit 140 Bus switch 20 External control apparatus 30 Device under test 31 Clamp target via 32 GND

Claims (4)

A clamp testing device that generates a pseudo failure in a device under test by clamping a voltage level of a portion to be clamped in a device under test without a negative voltage generation circuit ,
Means for generating a negative voltage;
A clamp test apparatus comprising: a probe that applies the negative voltage generated by the means for generating the negative voltage to a signal whose voltage level is to be clamped. The clamp test apparatus according to claim 1, wherein the means for generating a negative voltage generates a negative voltage by accumulating electric charge in a capacitor. The means for controlling the timing which applies the negative voltage generated by the means for generating the negative voltage to the signal to be clamped with the voltage level. Clamp testing device. A means for generating a negative voltage and a probe for applying the generated negative voltage to a signal whose voltage level is to be clamped are provided, and the voltage level of a clamping target portion in a test target device having no negative voltage generating circuit is determined. A clamp test method by a clamp test device that causes a pseudo failure in a device under test by clamping,
A process of generating a negative voltage by means of generating the negative voltage;
And a step of bringing the probe into contact with the portion to be clamped and applying the generated negative voltage to a signal whose voltage level is to be clamped.

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