JP5137787B2 - Data transmitter / receiver - Google Patents

Description

  The present invention relates to a data transmission / reception device, and more particularly to a data transmission / reception device constituting a network system such as a high-speed PLC (Power Line Communication).

  A wireless LAN defined by IEEE 802.11 employs a TDMA (Time Division Multiple Access) system that secures a transmission band in advance and transmits data. Specifically, HiSWANA (High Speed Wireless Access Networking Type a: ARIB STD-T70 version 1.0) standardized by ARIB (Radio Industry Association) is available.

  Hereinafter, an overview of the TDMA system adopted in the HiSWANA standard will be described. In the TDMA system adopted in HiSWANA, each terminal in the network is managed by one terminal called a management terminal.

  In order to manage time synchronization of the entire network, the management terminal broadcasts packet data called a beacon (hereinafter referred to as BCH: Broadcast CHannel) at a predetermined cycle (2 ms cycle in HiSWANA).

  Upon receiving the BCH, each client terminal arranged in the network resets the reference time information in the terminal and starts preparation for receiving various control packets transmitted from the management terminal.

  After sending the BCH, the management terminal broadcasts network system control packet data (hereinafter referred to as FCH: Frame CHannel) including the data transmission schedule of each client terminal connected to the network to each client terminal. .

  The FCH is added with a data transmission / reception schedule including data transmission / reception slot information (transmission / reception start timing information, data transmission / reception time information, etc.) of each client terminal connected to the network. Detects the timing at which the terminal transmits / receives data upon receiving the FCH.

  After transmitting the FCH, the management terminal transmits packet data (hereinafter referred to as ACH: Access feedback CHannel) of transmission request reception notification to each client terminal. ACH is a response from the management terminal to a bandwidth allocation request from each client terminal (details will be described later).

  When the transmission of the BCH, FCH, and ACH packet data is completed from the management terminal, each client terminal starts receiving and transmitting packet data based on the schedule notified on the FCH (hereinafter, each terminal). The period during which data is transmitted and received between them is expressed as TCH).

  In the TDMA scheme, the management terminal schedules data transmission slots only for client terminals having data to be transmitted. Therefore, the client terminal having data to be transmitted needs to request the management terminal to allocate a slot for transmitting the data of the own terminal. In the TDMA system adopted in the HiSWANA standard, since a transmission request is accepted from each client terminal, the transmission slot request request (bandwidth allocation) from each client terminal is finally received within one beacon period (hereinafter referred to as one frame). A CSMA (Carrier Sense Multiple Access) period (hereinafter referred to as RCH: Random access CHannel period) for receiving a request is prepared.

  The management terminal notifies the terminal that has received the transmission slot request request during the RCH period that the bandwidth allocation request has been received on the ACH within the next one beacon period.

  Here, in the TCH that transmits and receives data between terminals, a MAC (Media Access Control) frame configuration is used so that the transmission band can be efficiently used in conformity with the network system. For example, in Patent Document 1, when a MAC frame is generated, a plurality of pieces of data having the same destination (data constituting the MAC frame: hereinafter referred to as input data) are connected together and the input data is connected. A method for reducing overhead by adding only one MAC header to a column and improving transmission efficiency is described.

  The method disclosed in Patent Document 1 includes information on the number of input data linked in advance to the MAC header (hereinafter referred to as the number of links) and the length thereof, and is linked by referring to the information on the receiving side. The input data is separated and extracted.

  However, in the above method, in the operation of sequentially connecting the input data after generating the MAC header, even if the length of the MAC frame is set to be sufficiently larger than the total length of the input data to be connected, the MAC header Input data more than the number of connections added to cannot be connected, and there is a problem that the available transmission band remains unused, and input data that can be connected to the remaining band is transmitted until the next MAC frame generation However, there was a problem that it was delayed and delayed.

JP-T-2006-527570

  The present invention has been made in order to solve the above-described problems, and in the generation of a MAC frame, a data transmission / reception apparatus capable of additionally connecting input data to a MAC frame according to the input status of the input data. The purpose is to provide.

The data transmission / reception apparatus according to the present invention is a data transmission / reception apparatus constituting a communication network, wherein the data transmission / reception apparatus connects input data having the same destination to generate a MAC frame used in the communication network. a control circuit, wherein the transmission control circuit includes a MAC frame connection control circuit for determining a connection speed of said input data, the MAC frame generating circuit for generating a MAC frame data by connecting the input data based on the number of connections And a MAC header generation circuit for generating a MAC header so as to include the information on the number of connections, generating the MAC frame so as to include the MAC frame data and the MAC header, and connecting the MAC frames The control circuit is configured to link the input data based on the number of connections by the MAC frame generation circuit. When the MAC frame data is generated and the input data is allowed to be additionally connected beyond the number of connections, the input data can be additionally connected in the MAC frame. The presence or absence of an area is detected, and when there is an empty area that can be additionally connected, the MAC frame generation circuit is controlled to regenerate the MAC frame data additionally connected to the input data, and the MAC header generation circuit the control to to include additional coupling flag indicating the existence of additional coupling said input data was Ru is regenerate the MAC header.

  According to the data transmitting / receiving apparatus according to the present invention, when a MAC frame is generated, a transmission band that can be used for the MAC frame remains as a free area even after adding the number of connected input data to the MAC header. In addition, it is possible to add and connect them according to the input status of the input data, so that the transmission band can be efficiently used and the effect of suppressing the stagnation of the input data can be obtained.

<A. Embodiment 1>
<A-1. Network system configuration>
FIG. 1 is a diagram schematically showing a configuration of a high-speed PLC network system including a data transmitting / receiving apparatus according to Embodiment 1 of the present invention. In the following, the data transmitting / receiving apparatus is referred to as a terminal.

  As shown in FIG. 1, the high-speed PLC network system includes a management terminal 1 that manages the entire network, a client terminal A3, a client terminal B5, and a client terminal B7 connected to the PLC network system, and a power line 9 that also serves as a signal line. The management terminal 1, the client terminal A3, the client terminal B5, and the client terminal B7 and the power line 9 are electrically connected by power outlets 2, 4, 6, and 8, respectively.

  The configuration of the high-speed PLC network system shown in FIG. 1 is an example of a system configuration to which the data transmission / reception apparatus of the present invention can be applied. The data transmission / reception apparatus of the present invention includes a high-speed PLC network system having other configurations, The present invention can also be applied to various wired and wireless network systems such as a network system using a wireless LAN.

<A-2. Overview of network system operations>
Next, the schematic operation of the network system will be described with reference to FIG. 1, focusing on the operation of the management terminal 1 in the high-speed PLC network. In the first embodiment, a case will be described as an example where the TDMA method adopted in the HiSWANA standard described as the prior art is adopted as the MAC method.

  Note that the data transmitting / receiving apparatus of the present invention is not limited to application to only the TDMA system, but can be applied to other communication systems that generate MAC frames from a plurality of input data (details will be described later).

<A-2-1. Operation of management terminal>
The management terminal 1 first broadcasts a beacon signal (BCH: Broadcast CHannel) as synchronization information at a predetermined cycle in order to manage time synchronization of the entire network. After the BCH transmission, the management terminal 1 broadcasts data reception and data transmission timing information (FCH: Frame CHannel) of each terminal in the high-speed PLC network. When an RCH (Random access CHannel) output from each client terminal is received in the previous frame after the FCH transmission, an ACH (Access feedback CHannel) for notifying the RCH transmission client terminal of normal reception is output.

  After transmitting the ACH, the management terminal 1, the client terminal A3, the client terminal B5, and the client terminal C7 perform data transmission / reception between the client terminals in the TCH period based on the schedule transmitted on the FCH.

<A-2-2. Operation of client terminal>
Next, the operation of the client terminal will be described. When the client terminal receives the BCH output from the management terminal 1, the client terminal synchronizes the reference time in the client terminal based on the BCH.

  After synchronization of the reference time, each client terminal sets the respective data transmission timing and data reception timing internally based on the FCH output from the management terminal 1, and starts preparation for packet data transmission and reception To do. In the case of packet data transmission, when the transmission time based on the FCH approaches, input data is concatenated to start generating a MAC frame, and the MAC frame is transmitted to the power line 9 at a predetermined timing. In the case of reception of packet data, the MAC frame is demodulated at the reception time based on the FCH, and MAC frame reception operations such as extraction of input data and error detection are performed.

  When the transmission / reception of the MAC frame based on the schedule on the FCH is completed, each client terminal outputs a bandwidth allocation request to the management terminal 1 during the RCH period when it has the MAC frame transmission data.

<A-3. Configuration of high-speed PLC terminal>
<A-3-1. Configuration of data transmitter / receiver>
Next, the configuration of the high-speed PLC terminal will be described with reference to FIGS.
FIG. 2 is a block diagram showing the configuration of the data transmitting / receiving apparatus 10 when the data transmitting / receiving apparatus according to the present invention is applied to a high-speed PLC terminal.

  As shown in FIG. 2, the data transmitting / receiving apparatus 10 includes a CPU (Central Processing Unit) 11, an Ethernet (registered trademark) interface circuit 12, a bridge interface circuit 13, a bridge memory 14, a PLC modem circuit 15, and a PLC transmission memory 16. , A PLC reception memory 17 and a CPU bus 18 are provided.

  Here, the bridge interface circuit 13 includes Ethernet frame data input from the Ethernet interface circuit 12, Ethernet frame data output to the Ethernet interface circuit 12, Ethernet frame data output to the PLC modem circuit 15, and the PLC modem circuit 15. This circuit bridges input Ethernet frame data.

  The bridge memory 14 is a memory in which the Ethernet frame input to the bridge interface circuit 13 is sorted and stored for each destination, and the PLC transmission memory 16 is transmitted via the power line 9 (FIG. 1). The PLC reception memory 17 is a memory for storing MAC frame data received via the power line 9.

  The Ethernet interface circuit 12 is a circuit for inputting Ethernet frame data from the outside to the data transmitting / receiving device 10 via the input terminal 20 and the output terminal 21 and outputting the data from the data transmitting / receiving device 10 to the outside. In this circuit, the frame data is transmitted to the outside through the output terminal 22 and the PLC frame input through the input terminal 23 is received.

  In general, in a high-speed PLC network, each terminal connected to the power line 9 (FIG. 1) uses the concept of a logical port, and the bridge interface circuit 13 uses a destination (the management terminal 1, the client terminal A3, the client in FIG. Data is distributed to each terminal B5 and client terminal C7) and queued in the bridge memory 14.

  Specifically, this is a process of distributing and storing Ethernet frame data input from the Ethernet interface circuit 12 in the bridge memory 14 for each destination.

<A-3-2. Configuration of PLC modem circuit>
FIG. 3 is a block diagram showing a configuration of the PLC modem circuit 15 in the data transmitting / receiving apparatus 10 shown in FIG.
As shown in FIG. 3, the PLC modem circuit 15 includes a PLC transmission control circuit 40 that generates Ethernet MAC frame data by connecting Ethernet data input from the bridge interface circuit 13 via the input terminal 30, and a power line 9. A PLC reception control circuit 50 that separates Ethernet frame data from the PLC MAC frame data received via (FIG. 1) and outputs it to the bridge interface circuit 13 via the output terminal 31 is provided. The PLC transmission control circuit 40 exchanges MAC frame data for transmission with the PLC transmission memory 16, and the PLC reception control circuit 50 exchanges MAC frame data with the reception memory 17. Give and receive.

<A-3-3. Configuration of PLC transmission control circuit>
FIG. 4 is a block diagram showing a configuration of PLC transmission control circuit 40 shown in FIG.
As shown in FIG. 4, the PLC transmission control circuit 40 includes a MAC frame generation circuit 401, a PLC transmission timing generation circuit 402, a MAC frame connection control circuit 403, an encryption circuit 404, a MAC header generation circuit 405, a MAC header addition circuit 406, A PLC transmission memory control circuit 407, a selector 408, and an FCS addition circuit 409 are provided.

  The MAC frame generation circuit 401 connects Ethernet frame data input from the bridge interface circuit 13 via the input terminal 30 under the control of the MAC frame connection control circuit 403, and generates MAC frame data for PLC. The PLC transmission timing generation circuit 402 includes a MAC frame connection control circuit 403, a MAC header generation circuit 405, a PLC based on the reception status of the Ethernet frame data input via the input terminal 30 and the transmission timing notified from the CPU 11. The operation timing control and instruction of the transmission memory control circuit 407 are performed.

  The MAC frame connection control circuit 403 has a function of controlling connection of Ethernet frame data in accordance with an instruction from the PLC transmission timing generation circuit 402, and instructs the MAC frame generation circuit 401 to perform connection.

  The encryption circuit 404 encrypts the MAC frame data generated by the MAC frame generation circuit 401, and the MAC header generation circuit 405 is based on control information provided from the PLC transmission timing generation circuit 402 and the MAC frame connection control circuit 403. To generate a MAC header.

  The MAC header addition circuit 406 is a circuit that adds the output of the MAC header generation circuit 405 to the output of the encryption circuit 404 and matches the MAC frame data.

  The PLC transmission memory control circuit 407 transfers the MAC frame data matched by the MAC header addition circuit 406 to the PLC transmission memory 16 according to the transmission timing of the MAC frame data based on the instruction of the PLC transmission timing generation circuit 402. Control to store. Based on an instruction from the PLC transmission memory control circuit 407, the selector 408 switches the outputs of the MAC header addition circuit 406 and the PLC transmission memory control circuit 407 and applies them to the FCS addition circuit 409. The FCS addition circuit 409 This is a circuit for adding an FCS (Frame Check Sequence) for error detection to the MAC frame data output from 408.

  In addition, when operating as a management terminal, the PLC transmission timing generation circuit 402 generates PLC network control information such as BCH, FCH, and ACH based on an instruction from the CPU 11 in addition to the above-described operation, and as a client terminal When operating, a bandwidth allocation request (RCH) is generated.

<A-3-4. Configuration of PLC reception control circuit>
FIG. 5 is a block diagram showing a configuration of PLC reception control circuit 50 shown in FIG.
As shown in FIG. 5, the PLC reception control circuit 50 includes a MAC header analysis circuit 501, an FCS check circuit 502, a PLC reception timing generation circuit 503, an encryption / decryption circuit 504, a PLC control frame separation circuit 505, a MAC frame separation circuit 506, and a PLC. A reception memory control circuit 507 is provided.

  The MAC header analysis circuit 501 is a circuit that separates a MAC header from received MAC frame data input via the input terminal 23 and analyzes the contents. The FCS check circuit 502 is a circuit that detects an error that has occurred in the received MAC frame data based on the FCS added to the received MAC frame data at the time of transmission.

  The PLC reception timing generation circuit 503 controls and instructs operation timings of the MAC header analysis circuit 501 and the FCS check circuit 502 based on the output of the PLC control frame separation circuit 505 and the reception timing notified from the CPU 11.

  The encryption / decryption circuit 504 is a circuit for decrypting the encrypted MAC frame data output from the MAC header analysis circuit 501, and the PLC control frame separation circuit 505 is a decrypted MAC frame output from the encryption / decryption circuit 504. Among the data, the PLC network control information such as BCH, FCH, and ACH is separated from normal MAC frame data that is not PLC network control information such as Ethernet frame data, and the MAC frame determined by the FCS check circuit 502 Based on the error information, the handling of the MAC frame data is determined.

  The MAC frame separation circuit 506 determines the MAC frame data to which the Ethernet frame data output from the PLC control frame separation circuit 505 is concatenated based on the number of concatenated MAC headers, an additional concatenation flag, a concatenation termination flag, or the like (for details, see FIG. This is a circuit for separating into individual Ethernet frame data.

  The PLC reception memory control circuit 507 generates a control signal for temporarily storing the Ethernet frame data output from the MAC frame separation circuit 506 in the PLC reception memory 17 and performs a read control of the stored Ethernet frame data. It is.

  When operating as a management terminal, the PLC reception timing generation circuit 503 manages the bandwidth allocation request (RCH) from the client terminal based on the output of the PLC control frame separation circuit 505 and the instruction from the CPU 11. Further, when operating as a client terminal, synchronization control, schedule information, a bandwidth allocation request reception notification, and the like are managed based on PLC network control information such as BCH, FCH, and ACH and an instruction from the CPU 11.

<A-4. Transmission timing of data in frame>
As described in the background art, the management terminal 1 periodically outputs BCH, FCH, and the like to manage the PLC network.

  FIG. 6 shows transmission timings of various data in one beacon period (one frame) of the PLC network. As shown in FIG. 6, in one beacon cycle, after transmitting network management information in the order of BCH, FCH, and ACH, N communication slots # 1 to #n are transmitted in the data transmission / reception period, and finally RCH is transmitted. Will be sent.

  In Embodiment 1, when the management terminal 1 sends out BCH, the time information of the management terminal 1 is sent out as payload information. When receiving the BCH, the client terminal that receives the BCH synchronizes the internal reception reference time (client terminal side reference time) with the transmission side reference time (management terminal side reference time) added to the BCH.

  The management terminal 1 transmits FCH (scheduling information) following transmission of BCH. FIG. 7 shows the configuration of schedule information added to the FCH payload. When the management terminal 1 receives a bandwidth allocation request from each client terminal, the management terminal 1 performs scheduling according to the request. In the schedule information, for each communication slot provided in the data transmission / reception period (TCH), transmission start time, transmission time, terminal information indicating from which terminal (transmitting terminal) to which terminal (receiving terminal) data transmission, and Contains related information when sending and receiving data.

  In Embodiment 1, it is assumed that MAC address (Media Access Control Address) information possessed by each terminal is used for transmitting terminal information and receiving terminal information. In addition to the MAC address information, for example, a logical port number in the PLC network or identification information determined privately in the network has the same effect.

  Also, as shown in FIG. 6, after transmission of the FCH, transmission of a bandwidth allocation request reception notification by the management terminal 1 during the ACH period, data transmission / reception between terminals on the TCH based on the schedule information notified by the FCH, RCH One beacon period of the PLC network is completed through transmission of a bandwidth allocation request by the client terminal during the period.

  FIG. 8 shows the structure of the TCH payload. As shown in FIG. 8, one MAC frame is allocated to one communication slot in the TCH.

  The number of the TCH communication slots shown in FIGS. 6 to 8 is an example of N (N ≧ 0). The length of one communication slot, that is, the size of the MAC frame and the number N of communication slots are determined by the management terminal 1 controlling according to the status of the bandwidth allocation request of the client terminal.

<A-5. Configuration of MAC frame>
<A-5-1. Conventional method>
First, an outline of a conventional MAC frame configuration method will be described with reference to FIG. In the first embodiment, an Ethernet frame is used as input data that is a component of a MAC frame. However, the present invention is not limited to this, and the data of the present invention can be used as long as the frame has length information in a similar configuration. A transmission / reception apparatus is applicable.

  As shown in FIG. 9, the MAC frame is configured such that the MAC header M10 is added to the head, and the Ethernet frames are sequentially connected from the back. The MAC header M10 includes transmission source information M20 indicating the transmission source terminal of the MAC frame, destination information M21 indicating the transmission destination terminal of the MAC frame, the number of connected Ethernet frames M22, and other MAC frame transmission related information M23.

  The number of connections M22 is determined by the MAC frame connection control circuit 403 (FIG. 4) by determining the size of the MAC frame determined based on the FCH notified from the management terminal 1 and the status of the Ethernet frame stored as input data. decide. In the example of FIG. 9, the number of connections is P, but P is set to an integer of 0 or more assuming an idle-only communication slot that does not connect Ethernet frames.

  As shown in FIG. 9, following the MAC header M10, the length information M11 of the first (# 1) Ethernet frame and the first Ethernet frame body M12 are sequentially connected, and then the second As described in (# 2), the length information M13 of the Ethernet frame and the second Ethernet frame body M14 are sequentially connected, the length information of the Ethernet frame and the Ethernet frame body are alternately connected. This continues until the connection number P is reached. Then, when the length information M15 of the Pth Ethernet frame and the Ethernet frame body M16 are connected, the connection process of the Ethernet frame ends.

  Here, the length information M11, M13, etc. of each Ethernet frame is added to separate the concatenated Ethernet frames individually on the MAC frame receiving side based on the length information ( Details will be described later).

  When the connection process of the Ethernet frame is completed, the MAC frame may have an empty area (IDLE) M17 in which input data may be further stored. That is, although the size of the MAC frame is determined by the scheduling of the management terminal 1 as described above, the total length of a plurality of Ethernet frames to be connected by the client terminal does not necessarily match the size of the MAC frame. IDLE occurs. When IDLE occurs, processing such as zero padding is usually performed as a period in which the data has no meaning.

  When the MAC frame concatenation process is completed, or when there is IDLE, the FCS information M18 for error detection is added and the generation of the MAC frame is completed.

  Next, a procedure for connecting Ethernet frames in a conventional MAC frame will be described with reference to FIG.

  FIG. 10 shows an example in which the number of connections in the MAC frame is determined to be two when the first (# 1) Ethernet frame and the second (# 2) Ethernet frame are accumulated as input data. Yes. In addition, it is assumed that the third (# 3) Ethernet frame is accumulated until the connection of the Ethernet frame is started after the number of connections to be added to the MAC header is set to 2.

  The MAC frame is connected to the length information of the first (# 1) Ethernet frame and the frame body following the MAC header, and further connected to the length information of the second (# 2) Ethernet frame and the frame body, When the determined number of connections reaches two, the connection of Ethernet frames is terminated. After this, even if there is enough free space to connect the third (# 3) Ethernet frame as IDLE, the third (# 3) Ethernet frame is not concatenated. This completes the generation of the MAC frame.

  For this reason, in the above case, the MAC frame configuration efficiency (transmission band efficiency) decreases, and the third (# 3) Ethernet frame is accumulated until it is linked to the next MAC frame. Transmission of the data of the third (# 3) Ethernet frame stays.

<A-5-2. Method of configuring MAC frame according to invention>
Next, an outline of a MAC frame configuration method according to Embodiment 1 will be described with reference to FIG.

  The MAC frame shown in FIG. 11 also has a configuration in which a MAC header M50 is added to the head as in the conventional MAC frame, and the Ethernet frames are sequentially connected from the back.

  The MAC header M50 includes transmission source information M70 indicating the transmission source terminal of the MAC frame, destination information M71 indicating the transmission destination terminal of the MAC frame, connection number M72 of the Ethernet frame, additional connection flag M73, and other MAC frame transmission related information M74. Is included.

  The concatenated number M72 is determined by the MAC frame concatenation control circuit 403 by determining the size of the MAC frame determined based on the FCH notified from the management terminal 1 and the status of the Ethernet frame stored as input data, as in the conventional case. decide. In the example of FIG. 11, the number of connections is P, but assuming an idle-only communication slot that does not connect Ethernet frames, P is set to an integer greater than or equal to zero.

  In addition, the MAC frame connection control circuit 403 (FIG. 4) sets whether to permit additional connection of Ethernet frames after determining the number of connections from the CPU 11 through the PLC transmission timing generation circuit 402 (FIG. 4). Be notified. This setting is given to the data transmitting / receiving apparatus 10 in advance, and the CPU 11 notifies the MAC frame connection control circuit 403 of the setting.

  When the setting for permitting additional connection is made, the additional connection flag M73 is added as a component of the MAC header regardless of whether or not the connection is actually added. In addition, since it is the same as that of the conventional method of constructing a MAC frame when the setting for permitting additional connection is not made, a case where additional connection is permitted will be described below.

  Following the MAC header M50, the length information M51 of the first (# 1) Ethernet frame and the first Ethernet frame body M52 are sequentially connected, and then the second (# 2) Ethernet frame. The length information M53 and the second Ethernet frame body M54 are sequentially connected. By repeating this, when the connection of the Pth (#P) Ethernet frame body is completed, the P + 1th (# P + 1) Ethernet frame has already been accumulated as input data of the constituent elements of the MAC frame, When there is an empty area (IDLE) in which the P + 1 Ethernet frame can be connected to the MAC frame, the MAC frame connection control circuit 403 exceeds the number of connections added to the MAC header, that is, P, and P + 1 The length information M55 of the Ethernet frame (# P + 1) and the Ethernet frame body M56 are additionally connected.

  Further, when the additional connection flag M73 is added, the Ethernet frame is not necessarily connected with the connection number set by the connection number M72, so that the connection end indicating that it is the end of the connection of the Ethernet frame A flag M57 is added to the MAC frame. The connection end flag M57 is always added when the additional connection flag M73 is added regardless of whether or not the Ethernet frame is actually additionally connected.

  Note that this additional connection of Ethernet frames is not limited to one. If there are additional Ethernet frames that can be connected and IDLE has room, connection of two or more Ethernet frames is performed in the same manner. Is possible.

  When MAC frame concatenation including additional concatenation ends or there is an empty area (IDLE) M58, when the period ends, FCS information M59 for error detection is added, and generation of the MAC frame is completed.

  Next, a procedure for concatenating Ethernet frames in a specific MAC frame will be described with reference to FIG.

  FIG. 12 shows an example in which the number of connections in the MAC frame is determined to be two when the first (# 1) Ethernet frame and the second (# 2) Ethernet frame are accumulated as input data. Yes. In addition, it is assumed that the third (# 3) Ethernet frame is accumulated until the connection of the Ethernet frame is started after the number of connections to be added to the MAC header is set to 2. Furthermore, after determining the number of connections, the Ethernet frame is set to be permitted to be additionally connected beyond the determined number of connections.

  The MAC frame is connected to the length information of the first (# 1) Ethernet frame and the frame body following the MAC header, and further connected to the length information of the second (# 2) Ethernet frame and the frame body, It reaches two of the determined number of connections. At this time, if there is enough IDLE to connect the third (# 3) Ethernet frame, the MAC frame connection control circuit 403 obtains the length information of the third (# 3) Ethernet frame and the frame body first. The number of connections exceeds the determined number.

  After the third (# 3) Ethernet frame is additionally concatenated, if there is no other Ethernet frame to be additionally concatenated, or if there is no IDLE that can further concatenate Ethernet frames in the MAC frame, the concatenation termination flag is set. Add to the MAC frame, and finally add FCS to complete the generation of the MAC frame.

  Controlling the generation of a MAC frame as described above not only prevents the MAC frame configuration efficiency (transmission band efficiency) from being lowered, but also has to be linked to the next MAC frame in the conventional method. Also, Ethernet frames can be connected, and data retention can be suppressed.

<A-5-3. Configuration procedure of MAC frame>
Next, the configuration procedure (MAC frame transmission side) of the MAC frame in Embodiment 1 will be described using the flowchart shown in FIG.

  As shown in FIG. 13, when data transmission is started, first, the CPU 11 confirms schedule information notified by the FCH transmitted from the management terminal 1 (step S11). Then, the PLC transmission timing generation circuit 402 confirms whether or not the MAC frame generation start timing has come (step S12). When the MAC frame generation start timing has come, the PLC transmission timing generation circuit 402 and the MAC frame generation The circuit 401 confirms the input data (Ethernet frame) which is an element constituting the MAC frame (step S13), and the MAC frame connection control circuit 403 is based on the confirmation information of the Ethernet frame of the PLC transmission timing generation circuit 402. The connection number P is determined (step S14).

  It is confirmed in the MAC frame connection control circuit 403 whether or not the connection number P determined above is set to permit the connection of Ethernet frames beyond the connection number P (step S15).

  If excess connection is not permitted, the MAC header generation circuit 405 generates a MAC header including information on the number of connections P under the instruction of the MAC frame connection control circuit 403 (step S16).

  Thereafter, under the instruction of the MAC header generation circuit 405, the MAC header addition circuit 406 adds the MAC header generated by the MAC header generation circuit 405, and subsequently the MAC frame before encryption generated by the MAC frame generation circuit 401 The encryption circuit 404 encrypts the frame (P Ethernet frames), and the MAC header addition circuit 406 concatenates the Ethernet frame length information and the Ethernet frames until the number reaches P (step S17). ).

  Here, the transmission timing is generated in the PLC transmission timing generation circuit 402, the transmission timing is output to the PLC transmission memory control circuit 407, and whether or not the PLC transmission memory control circuit 407 has reached the MAC frame transmission start timing. Is confirmed (step S18).

  When the MAC frame transmission start timing comes, the FCS addition circuit 409 generates the FCS and adds it to the MAC frame (step S27), and the MAC frame is transmitted by transmission control by the PLC transmission memory control circuit 407. (Step S28) The process in one beacon period is completed (step S29), and the process returns to step S11 to perform the process in the next beacon period.

  On the other hand, in step S15, when it is confirmed that the setting for permitting the connection of the Ethernet frame exceeding the connection number P is made, the MAC header generation circuit is instructed by the MAC frame connection control circuit 403. 405 creates a MAC header including the connection number P and an additional connection flag (step S19).

  Thereafter, under the instruction of the MAC header generation circuit 405, the MAC header addition circuit 406 adds the MAC header generated by the MAC header generation circuit 405, and subsequently the MAC frame before encryption generated by the MAC frame generation circuit 401 The encryption circuit 404 encrypts the frame (P Ethernet frames), and the MAC header addition circuit 406 concatenates the Ethernet frame length information and the Ethernet frames until P frames are generated (step S20). ).

  At this time, it is confirmed in the PLC transmission memory control circuit 407 whether or not the MAC frame transmission start timing has come (step S21). If it is not yet the transmission start timing, the PLC transmission timing generation circuit 402 and the Ethernet frame The MAC frame generation circuit 401 that performs concatenation checks the P + 1th and subsequent Ethernet frames (step S22).

  Then, the MAC frame concatenation control circuit 403 first confirms the state of the MAC frame generated by concatenating P Ethernet frames, confirms whether there is an IDLE that can be additionally concatenated with the MAC frame, and PLC transmission timing. Whether or not additional connection is possible is determined together with the confirmation content of the Ethernet frame from the generation circuit 402 (step S23).

  If there is an Ethernet frame that can be additionally connected and is to be connected, the MAC frame generation circuit 401 connects the Ethernet frame to the MAC frame under the instruction of the MAC frame connection control circuit 403 (step S24).

  On the other hand, if it is determined in step S23 that there is no IDLE that can be additionally connected to the Ethernet frame, or that there is no Ethernet frame that can be additionally connected, the process proceeds to step S25 to determine whether or not the transmission start timing of the MAC frame has come. This is confirmed by the transmission memory control circuit 407.

  In step S21 or step S25, when the MAC frame transmission start timing is reached, the MAC header addition circuit 406 adds a connection termination flag to the MAC frame under the instruction of the MAC header generation circuit 405 (step S26). . Thereafter, the processing in step S27 and subsequent steps is performed to complete the processing in one beacon cycle.

<A-5-4. Ethernet Frame Extraction Procedure>
Next, a procedure for extracting an Ethernet frame from a MAC frame (MAC frame receiving side) will be described with reference to the flowchart shown in FIG.

  As shown in FIG. 14, when data transmission is started, first, the CPU 11 confirms schedule information notified by the FCH transmitted from the management terminal 1 (step S101). Then, the PLC reception timing generation circuit 503 confirms whether or not the MAC frame reception timing is reached (step S102). If the MAC frame reception timing is reached, the MAC header analysis circuit 501 is included in the MAC frame. The MAC header is analyzed (step S103), and the connection number P is confirmed (step S104). The MAC header analysis circuit 501 also checks whether or not an additional connection flag is added to the analyzed MAC header (step S105).

  In step S105, when the additional connection flag is not added to the MAC header, it is determined that P Ethernet frames are connected to the MAC frame according to the number of connections. The decryption circuit 504 decrypts the MAC frame, and the PLC control frame separation circuit 505 outputs PLC network control information such as BCH, FCH, and ACH among the decrypted MAC frames output from the decryption circuit 504. A normal MAC frame that is not PLC network control information, such as an Ethernet frame, is separated, and the concatenated Ethernet frame is separated and extracted by the MAC frame separation circuit 506 (step S106), and the process proceeds to step S110.

  In order to extract each Ethernet frame from the MAC frame, length information added before each Ethernet frame is used when generating the MAC frame. That is, for example, the length of the first (# 1) Ethernet frame can be recognized by the length information of the first (# 1) Ethernet frame added immediately before, so that the length information can be obtained. The number of data corresponding to the determined length is counted in the MAC frame separation circuit 506, and the first (# 1) Ethernet frame is extracted by performing separation when reaching a predetermined count number. Similarly, in the second and subsequent Ethernet frames, the Ethernet frames are separated and extracted by the above method.

  On the other hand, if the additional concatenation flag is added to the MAC header in step S105, since at least P Ethernet frames are concatenated to the MAC frame, first, P Ethernet frames are processed in the same procedure as in step S106. Is extracted (step S107).

  In step S107, if an additional concatenation flag is added, a concatenation termination flag is always added. Therefore, after extracting P Ethernet frames, it is determined whether or not the MAC frame separation circuit 506 has detected it. Confirm (step S108).

  If the connection end flag is not detected when the P-th (#P) Ethernet frame is extracted, it is further determined that the Ethernet frame is connected, and the length of the next Ethernet frame is detected. Based on this, an Ethernet frame is extracted (step S109). And it returns to step S108 again and the detection operation of a connection termination flag is performed. These operations are repeated until the connection end flag is detected. When the connection end flag is detected, the process proceeds to step S110.

The PLC reception timing generation circuit 503 receives a report from the PLC control frame separation circuit 505 and the MAC frame separation circuit 506 that the separation and extraction of the Ethernet frame is completed, and controls the FCS check circuit 502 to detect an error in the MAC frame. The FCS added for the purpose is checked (step S110).
The FCS is added to the end of the MAC frame for one MAC frame. If no error is detected by the FCS, it is determined that there is no error in all the extracted Ethernet frames, and data is received. Normal processing is performed (step S111).

  On the other hand, if an error is detected in step S110, the integrity of the MAC frame is not guaranteed, and therefore there may be an error in the separated Ethernet frame. In this case, step S (S112) is executed to perform processing when data reception fails. Specifically, error correction processing, data retransmission request processing, or the like.

  Through the above process, the process for one beacon period is completed (step S113), and the process returns to step S101 to perform the process for the next beacon period.

<A-6. Effect>
As described above, according to the data transmitting / receiving apparatus of the first embodiment, when a MAC frame is generated, it can be used in the MAC frame even after the connection number of input data such as an Ethernet frame is set in the MAC header. If there is a remaining transmission band, input data can be added and connected according to the input status of the input data, so that the transmission band can be used efficiently and data is unnecessary. The effect which suppresses stagnation is acquired.

  Further, since the connection end flag is added to the MAC frame, the receiving side can uniquely end the extraction operation of the Ethernet frame by detecting the connection end flag. In addition, when additional connection flags are added, if the connection end flag cannot be detected even after extraction of Ethernet frames for the number of connections is completed, it becomes an indicator that there is an additional connected Ethernet frame, and there is an interruption. Instead, it is possible to shift to an operation of extracting an additionally connected Ethernet frame.

  Since the MAC frame has an FCS at the end of the MAC frame, when an error is detected, the accuracy of the input data can be improved by performing processing when data reception fails.

<B. Second Embodiment>
<B-1. Configuration of MAC Frame According to Invention>
The configuration of the MAC frame in the data transmitting / receiving apparatus according to the second embodiment of the present invention will be described below. The configuration of the data transmitter / receiver is based on the data transmitter / receiver 10 shown in FIG.

  In the second embodiment, in the configuration of the MAC frame described in the first embodiment, the method of adding a flag related to the additional connection of the Ethernet frame is different from the method of separating the Ethernet frame on the MAC frame receiving side. .

<B-1-1. MAC frame configuration method>
The MAC frame configuration method in Embodiment 2 will be described with reference to FIG.
The MAC frame shown in FIG. 15 also has a configuration in which a MAC header M100 is added to the head as in the conventional MAC frame, and the Ethernet frames are sequentially connected from the back.

  The MAC header M100 includes transmission source information M120 indicating the transmission source terminal of the MAC frame, destination information M121 indicating the transmission destination terminal of the MAC frame, the number of connections M122 of Ethernet frames, and other MAC frame transmission related information M123.

  The concatenation number M122 is determined by the MAC frame concatenation control circuit 403 by determining the size of the MAC frame determined based on the FCH notified from the management terminal 1 and the status of the Ethernet frame stored as input data, as in the conventional case. decide. In the example of FIG. 15, the number of connections is P, but P is set to an integer equal to or greater than 0 assuming an idle-only communication slot that does not connect Ethernet frames.

  Following the MAC header M100, the length information M101 of the first (# 1) Ethernet frame and the first Ethernet frame body M102 are sequentially connected, and then the second (# 2) Ethernet frame. The length information M103 and the second Ethernet frame body M104 are sequentially connected. By repeating this, at the stage when the connection of the Pth (#P) Ethernet frame body is completed, it is permitted to additionally connect Ethernet frames beyond the number of connections P, and the P + 1th (# When the P + 1) Ethernet frame has already been accumulated as input data of the constituent elements of the MAC frame, and there is an IDLE of an empty area in which the P + 1 Ethernet frame can be connected to the MAC frame, the MAC frame connection control circuit 403 Adds an additional connection flag M105, and additionally connects the length information M106 of the (P + 1) th Ethernet frame and the Ethernet frame body M107.

  Similarly, the P + 2 (# P + 1) Ethernet frame has already been accumulated as input data of the MAC frame component, and there is an IDLE of an empty area in which the P + 2 Ethernet frame can be connected to the MAC frame. In this case, the MAC frame connection control circuit 403 adds the additional connection flag M108, and additionally connects the length information M109 of the P + 2 Ethernet frame and the Ethernet frame body M110.

  When MAC frame concatenation including additional concatenation ends or when there is an empty area (IDLE) M111, FCS information M112 for error detection is added when the period ends, and generation of the MAC frame is completed.

  As described above, in the MAC frame in the data transmitting / receiving apparatus according to the second embodiment, a flag indicating that the Ethernet frame is additionally concatenated is not added to the MAC header portion but additionally concatenated. A configuration is employed in which each frame is added before each Ethernet frame.

  That is, how many MAC frames are concatenated at the time of generating the MAC header is added as a concatenation number to the MAC header header, but when adding beyond the concatenation number, each time an Ethernet frame is additionally concatenated, the Ethernet A configuration in which an additional connection flag indicating that the frames are additionally connected is added.

  Next, the configuration procedure (MAC frame transmission side) of the MAC frame in Embodiment 2 will be described using the flowchart shown in FIG.

  As shown in FIG. 16, when data transmission is started, first, the CPU 11 confirms schedule information notified by the FCH transmitted from the management terminal 1 (step S31). Then, the PLC transmission timing generation circuit 402 confirms whether or not the MAC frame generation start timing has come (step S32). If the MAC frame generation start timing has come, the PLC transmission timing generation circuit 402 and the MAC frame generation The circuit 401 confirms input data (Ethernet frame) which is an element constituting the MAC frame (step S33), and the MAC frame connection control circuit 403 is based on the confirmation information of the Ethernet frame of the PLC transmission timing generation circuit 402. The connection number P is determined (step S34).

  Then, under the instruction of the MAC frame connection control circuit 403, the MAC header generation circuit 405 generates a MAC header including information on the number of connections P (step S35).

  Thereafter, under the instruction of the MAC header generation circuit 405, the MAC header addition circuit 406 adds the MAC header generated by the MAC header generation circuit 405, and subsequently the MAC frame before encryption generated by the MAC frame generation circuit 401 The encryption circuit 404 encrypts the frame (P Ethernet frames), and the MAC header addition circuit 406 concatenates the Ethernet frame length information and the Ethernet frames until P frames are generated (step S36). ).

  Next, it is confirmed in the MAC frame connection control circuit 403 whether or not the connection number P connected as described above is set to allow connection of Ethernet frames beyond the connection number P (step S37). ).

  If excess connection is not permitted, the PLC transmission memory control circuit 407 confirms whether or not the MAC frame transmission start timing has come (step S38). When the MAC frame transmission start timing comes, the process proceeds to step S44.

  In step S44, after the FCS addition circuit 409 generates the FCS and adds it to the MAC frame, the MAC frame is transmitted by transmission control by the PLC transmission memory control circuit 407 (step S45), and the processing in one beacon cycle is completed. Then (step S46), the process returns to step S31 to perform processing in the next beacon period.

  On the other hand, even when it is confirmed in step S37 that the Ethernet frame is allowed to be connected beyond the connection number P, the PLC transmission memory control circuit 407 determines the MAC frame transmission start timing. It is confirmed whether or not (step S39).

  If the transmission start timing is not yet reached, the PLC transmission timing generation circuit 402 and the MAC frame generation circuit 401 that connects the Ethernet frames confirm the P + 1 and subsequent Ethernet frames (step S40).

  Then, the MAC frame concatenation control circuit 403 first confirms the state of the MAC frame generated by concatenating P Ethernet frames, confirms whether there is an IDLE that can be additionally concatenated with the MAC frame, and PLC transmission timing. Whether or not additional connection is possible is determined together with the confirmation content of the Ethernet frame from the generation circuit 402 (step S41).

  Then, when there is an Ethernet frame that can be additionally connected and is a connection target, the MAC header addition circuit 406 adds an additional connection flag to the MAC frame under the instruction of the MAC frame connection control circuit 403, and generates a MAC frame. The circuit 401 additionally connects Ethernet frames (step S42), and the process returns to step S39.

  On the other hand, if it is determined in step S41 that there is no IDLE that can be additionally connected to the Ethernet frame or that there is no Ethernet frame that can be additionally connected, the process proceeds to step S43, and the PLC determines whether or not the transmission start timing of the MAC frame has come. This is confirmed by the transmission memory control circuit 407.

  If the MAC frame transmission start timing is reached in step S39 or step S43, the process proceeds to step S44, and thereafter, the process in step S44 and subsequent steps is performed to complete the process in one beacon cycle.

<B-1-2. MAC Frame Separation Method>
Next, a method of separating the Ethernet frame connected from the MAC frame in the data transmitting / receiving apparatus 10 on the receiving side will be described.

  The number is separated in the same manner as in the conventional example up to the number (P in the example of FIG. 15) described in the number of connections M122 of the MAC header M100. When the P-th separation is completed, an additional connection flag is detected. If an additional connection flag is detected, it is determined that one Ethernet frame is additionally connected, and is added after the additional connection flag. The additional connected Ethernet frame length information is extracted, and the additional connected Ethernet frame body is separated based on the extracted length information. When the separation of the additionally connected Ethernet frame is completed, the additional connection flag is detected again, and the same processing as described above is performed. If the additional concatenation flag is no longer detected, it is assumed that there are no more concatenated Ethernet frames, and the extraction of the Ethernet frame from the MAC frame is terminated.

  Next, a procedure for extracting an Ethernet frame from a MAC frame (MAC frame receiving side) will be described with reference to the flowchart shown in FIG.

  As shown in FIG. 17, when data transmission is started, first, the CPU 11 confirms schedule information notified by the FCH transmitted from the management terminal 1 (step S201). Then, the PLC reception timing generation circuit 503 confirms whether or not the MAC frame reception timing is reached (step S202). If the MAC frame reception timing is reached, the MAC header analysis circuit 501 is included in the MAC frame. The MAC header is analyzed (step S203), and the number of connections P is confirmed (step S204).

  Thereafter, the encryption / decryption circuit 504 decrypts the MAC frame, and the PLC control frame separation circuit 505 outputs PLC network control information such as BCH, FCH, and ACH among the decrypted MAC frames output from the encryption / decryption circuit 504, and A normal MAC frame that is not PLC network control information, such as an Ethernet frame, is separated, and the concatenated Ethernet frame is further separated and extracted by the MAC frame separation circuit 506 (step S205).

  When the P-th separation is completed, the MAC frame separation circuit 506 detects an additional connection flag (step S206). If an additional connection flag is detected, one Ethernet frame is additionally connected. The length information of the additional connection Ethernet frame added after the additional connection flag is extracted, and the additional connection Ethernet frame body is separated based on the extracted length information (step S207). Thereafter, the operations after step S206 are repeated.

On the other hand, when the additional connection flag is not detected in step S206, the PLC reception timing generation circuit 503 reports from the PLC control frame separation circuit 505 and the MAC frame separation circuit 506 that the separation and extraction of the Ethernet frame has been completed. In response, the FCS check circuit 502 is controlled to check the FCS added to the MAC frame for error detection (step S208).
The FCS is added to the end of the MAC frame for one MAC frame. If no error is detected by the FCS, it is determined that there is no error in all the extracted Ethernet frames, and data is received. Normal processing is performed (step S209).

  On the other hand, if an error is detected in step S208, the integrity of the MAC frame is not guaranteed, so there may be an error in the separated Ethernet frame. In this case, step S (S210) is executed to perform processing when data reception fails. Specifically, error correction processing, data retransmission request processing, or the like.

  Through the above process, the process for one beacon period is completed (step S211), and the process returns to step S201 to perform the process for the next beacon period.

<B-2. Effect>
As described above, according to the data transmitting / receiving apparatus of the second embodiment, when a MAC frame is generated, it can be used in the MAC frame even after the connection number of input data such as an Ethernet frame is set in the MAC header. If there is a remaining transmission band, input data can be added and connected according to the input status of the input data, so that the transmission band can be used efficiently and data is unnecessary. The effect which suppresses stagnation is acquired.

  Further, in the MAC frame configuration method according to the second embodiment, it is not necessary to add a flag related to additional concatenation to the MAC header, and it is concatenated at the end of the concatenated Ethernet frame (including those additionally concatenated). Since it is not necessary to add a termination flag, there is a feature that even if additional connection of Ethernet frames is permitted, if there is no additional connection of Ethernet frames, a MAC frame configuration similar to the conventional one can be used. Simple things are enough.

  Since the MAC frame has an FCS at the end of the MAC frame, when an error is detected, the accuracy of the input data can be improved by performing processing when data reception fails.

<C. Modification>
In Embodiments 1 and 2 described above, the case where the present invention is applied to a high-speed PLC terminal has been described. However, the application of the present invention is not limited to this, and a wireless LAN or UWB (Ultra Wideband) is applied. ), Or any other transmission method regardless of the TDMA method.

It is a figure which shows the structure of the high-speed PLC network system to which the data transmission / reception apparatus which concerns on this invention is applied. It is a block diagram explaining the structure of the data transmitter / receiver which concerns on this invention. It is a block diagram which shows the structure of the PLC modem circuit in the data transmitter / receiver based on this invention. It is a block diagram which shows the structure of the PLC transmission control circuit in a PLC modem circuit. It is a block diagram which shows the structure of the PLC reception control circuit in a PLC modem circuit. It is a figure which shows roughly the structure format of the PLC network 1 beacon period at the time of performing data transmission / reception with the data transmission / reception apparatus using high-speed PLC. It is a figure which shows roughly the structure format of the scheduling information (FCH) of a PLC network 1 beacon period. It is a figure which shows roughly the structure format of the data transmission / reception period (TCH) of a PLC network 1 beacon period. It is a figure which shows the structure of the conventional MAC frame roughly. It is a figure explaining the specific structure of the conventional MAC frame. It is a figure which shows schematically the structure of the MAC frame of Embodiment 1 which concerns on this invention. It is a figure explaining the specific structure of the MAC frame of Embodiment 1 which concerns on this invention. It is a flowchart explaining the structure operation | movement (transmission side) of the MAC frame of Embodiment 1 which concerns on this invention. 6 is a flowchart illustrating an operation of extracting an Ethernet frame from a MAC frame according to the first embodiment of the present invention (receiving side). It is a figure which shows schematically the structure of the MAC frame of Embodiment 2 which concerns on this invention. It is a flowchart explaining the structure operation | movement (transmission side) of the MAC frame of Embodiment 2 which concerns on this invention. It is a flowchart explaining the extraction operation | movement (reception side) of the Ethernet frame from the MAC frame of Embodiment 2 which concerns on this invention.

Claims (7)

A data transmitting / receiving device constituting a communication network,
The data transmission / reception device includes:
A transmission control circuit that generates a MAC (Media Access Control) frame used in the communication network by connecting input data having the same destination;
The transmission control circuit includes :
A MAC frame connection control circuit for determining a connection number of the input data ;
A MAC frame generation circuit that generates MAC frame data by concatenating the input data based on the number of connections;
A MAC header generation circuit that generates a MAC header so as to include the information on the number of connections, and generates the MAC frame so as to include the MAC frame data and the MAC header,
The MAC frame connection control circuit
When the MAC frame generation circuit concatenates the input data based on the number of connections to generate the MAC frame data, and then is allowed in advance to additionally connect the input data beyond the number of connections. In addition, the presence or absence of a free area to which the input data can be additionally connected is detected in the MAC frame, and if there is the free area to which the additional connection can be added, the input data is added by controlling the MAC frame generation circuit. The MAC frame data that is concatenated is regenerated, and the MAC header generation circuit is controlled to regenerate the MAC header to include an additional concatenation flag indicating the presence of the additionally concatenated input data. Data transmission / reception device. The MAC header generation circuit includes:
Together with the MAC frame generation circuit to add connecting the entering force data regenerates the MAC header to include the additional connection flag indicating the existence of additional coupling said input data,
Of additional concatenated the input data, after the input data of the last, that further to adding a coupling end flag indicating the end of the connection, the data transmission and reception apparatus according to claim 1. The MAC header generation circuit includes:
Wherein when the MAC frame generation circuit adds connecting the entering-force data, each time the MAC frame generation circuit adds coupling the input data, you adds the additional connection flag, data transmission and reception according to claim 1, wherein apparatus. The transmission control circuit includes:
FCS (Frame Check Sequence) with the FCS adding circuit for adding, claim 2 or data transmission and reception equipment according to claim 3, wherein for the last error detection of the MAC frame.
The data transmission / reception device includes:
A reception control circuit for separating the input data from the MAC frame received via the communication network;
The reception control circuit includes:
MAC header analysis circuit for extracting the information on the number of connections added to the MAC header and checking the presence or absence of the additional connection flag;
A MAC frame separation circuit that extracts the input data for the number of connections from the MAC frame based on the extracted number of connections;
The MAC frame separation circuit includes:
The extraction of the additionally connected input data is repeated until the connection termination flag is detected after extracting the input data for the number of connections when the MAC header includes the additional connection flag. The data transmitting / receiving apparatus as described. The data transmission / reception device includes:
A reception control circuit for separating the input data from the MAC frame received via the communication network;
The reception control circuit includes:
A MAC header analysis circuit for extracting information on the number of connections added to the MAC header;
A MAC frame separation circuit that extracts the input data for the number of connections from the MAC frame based on the extracted number of connections;
The MAC frame separation circuit includes:
The extraction of the additionally connected input data is repeated until the connection end flag is no longer detected when the connection end flag is detected after extracting the input data for the number of connections. Data transmission / reception device. The reception control circuit includes:
7. The data transmission / reception apparatus according to claim 5, further comprising an FCS check circuit that detects an FCS (Frame Check Sequence) added for error detection at the end of the MAC frame.

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