JP5141122B2 - Switching power supply - Google Patents

Description

  The present invention relates to a switching power supply device that includes a switching element and an inductor connected to the switching element, and controls an output voltage by driving the switching element for each switching period.

As a conventional technique, there is known a switching power supply apparatus in which an LC circuit is configured in an output circuit and supplies stable power to a load by turning on / off a switching element (see, for example, Patent Documents 1 and 2). The control device of the switching power supply device generates a PWM signal (pulse width modulation signal) for turning on / off the switching element by feeding back the output voltage, and feeds back the output current flowing through the inductor by current mode control. The phase lead compensation is performed by
JP 2004-297943 A JP 2005-176547 A

  However, since a delay according to the carrier cycle actually occurs in the voltage feedback control, the phase shift of the output of the switching power supply may become conspicuous as the control frequency region approaches the carrier frequency of PWM control.

  Accordingly, an object of the present invention is to provide a switching power supply device that can suppress a phase shift of an output.

In order to achieve the above object, a switching power supply device according to a first invention
A switching power supply device that includes a switching element and an inductor connected to the switching element, and controls the output voltage by driving the switching element for each switching cycle,
Current detecting means for detecting an inductor current flowing through the inductor;
Storage means for storing the detection result of the current detection means;
Error amplifying means for amplifying an error between the output voltage and a predetermined reference voltage;
The carrier signal is superimposed on the superimposition result obtained by superimposing the carrier signal on either the amplification result of the error amplification means or the detection result before m (m is an integer of 1 or more) stored in the storage means. Drive signal generating means for generating a drive signal for the switching element based on a comparison result with the other one that is not.

A second invention is a switching power supply device according to the first invention,
A flip-flop having a clock signal that generates the switching period as a set input and a signal based on the comparison result as a reset input,
The drive signal is generated based on the output of the flip-flop.

3rd invention is the switching power supply device which concerns on 1st or 2nd invention, Comprising:
The detection result of the current detection means is sequentially stored in the storage means in synchronization with the switching period.

  According to the present invention, an output phase shift can be suppressed.

  Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic diagram showing a circuit configuration of a step-down switching power supply 100 according to an embodiment of the present invention. The step-down switching power supply 100 is a power supply device that supplies power to a load 14 using an input voltage VIN from a reference power supply connected to a reference voltage input terminal 1, and includes voltage fluctuations of the input voltage VIN and consumption of the load 14. This is a power supply device (so-called step-down switching regulator) that outputs a constant voltage obtained by stepping down the input voltage VIN from the reference power supply to the load 14 side in response to fluctuations in current (load current). When the step-down switching power supply 100 is mounted on a vehicle, for example, the reference power supply corresponds to an in-vehicle battery, and the load 14 corresponds to an in-vehicle electric load (for example, a microcomputer, an IC, a resistance load, a motor, etc.). To do. Since there are a wide variety of electric loads mounted on a vehicle, and the voltage of the on-vehicle battery is likely to fluctuate due to the difference in current consumption of each electric load, it is effective to mount a step-down switching power supply like this embodiment. is there. The step-down switching power supply 100 is also effective when used as a converter that performs voltage conversion between both voltage systems in a vehicle having a plurality of voltage systems (for example, 14V system and 42V system).

  The error amplifier 8 outputs an amplified voltage obtained by amplifying an error between the output voltage VOUT applied to the load 14 and its target voltage with a predetermined amplification degree. The ramp signal generation circuit 9 outputs a ramp signal (sawtooth wave) as a carrier signal for generating a drive signal (PWM signal) for driving the switching element 2 (2A, 2B). The adder 10 outputs a superimposed voltage obtained by adding the amplified voltage from the error amplifier 8 and the ramp signal from the ramp signal generation circuit 9. The superimposed voltage from the adder 10 is input to the non-inverting input terminal of the comparator 17.

  On the other hand, the current detection unit 5 detects a current (inductor current) flowing through the inductor 4. The inductor current detected by the current detector 5 is sampled and held by the sample hold circuit 15. A voltage corresponding to the inductor current value sampled and held by the sample and hold circuit 15 is input to the inverting input terminal of the comparator 17 via the delay circuit 16 described in detail later.

  The comparator 17 compares the superimposed voltage from the adder 10 with a voltage corresponding to the inductor current value, and outputs the comparison result to the drive circuit 13. The drive circuit 13 outputs a drive signal (PWM signal) for driving the switching element 2 (2A, 2B) at a duty ratio such that the output voltage VOUT becomes a predetermined target voltage according to the output voltage level of the comparator 17. Each of the switching elements 2 performs a switching operation based on the drive signal, whereby the input voltage VIN from the reference power supply is stepped down. Specific examples of the switching element 2 include semiconductor elements such as IGBTs, MOSFETs, and bipolar transistors.

  Based on the PWM signal, when the high-side switching element 2A is turned on and the low-side switching element 2B is turned off, a current flows through the inductor 4 connected to the connection point between the switching elements 2A and 2B, and the output capacitor 6 It is charged. Based on the PWM signal, when the switching element 2A is turned off and the switching element 2B is turned on, the inductor 4 and the output capacitor 6 connected to the output side of the inductor 4 The current flows back through the switching element 2B. By performing such a switching operation, the smoothed output voltage VOUT is output from the output terminal 7. In addition, by providing the switching element 2B, heat generation by the diode 3 connected to the input side of the inductor 4 can be suppressed. Further, if the diode 3 is provided, the current can be recirculated, and therefore the configuration without the switching element 2B may be employed. Further, if the diode 3 is a Schottky diode, noise can be reduced because the recovery current is small, and heat generation can be suppressed because the forward voltage is small.

By the way, ideally, the characteristic of PWM control is
VOUT = IL / [R _OUT // R _LOAD // (1 / jωC _OUT )]
= {R _S / [R _OUT // R _LOAD // (1 / jωC _OUT )]} × ERROUT
... (1)
Given in. Here, VOUT is the output voltage of the switching power supply, IL is the inductor current, _{R S} conversion resistor for detecting the inductor _{current, R OUT} is the output resistance of the switching power _{supply, R LOAD} is the load connected to the output of the switching power supply load resistor, C _OUT is the capacitance of the output capacitor, ERROUT output voltage of the error amplifier for amplifying an error between VOUT and its target voltage, omega is the angular frequency of the control frequency range.

However, in ideal current control, the phase does not turn more than 90 ° even in the high frequency range, but in reality there is a control delay for each switching, so switching occurs as the control frequency range approaches the carrier frequency of PWM control. The phase delay of the power supply output becomes significant. That is, as long as the PWM control is discrete control, the calculation of the nth switching timing is reflected in the feedback calculation of at least the (n + 1) th switching timing.
VOUT (n + 1) = {R _S / [R _OUT /// R _LOAD // (1 / jωC _OUT )]}
× ERROUT (n) (2)
It becomes. Therefore, when the angular frequency ω approaches the calculation cycle, a phase delay of one cycle occurs.

  FIG. 8A is a diagram showing a gain characteristic of a power supply output with respect to an output of an error amplifier that amplifies an error between an output voltage and a target voltage in a conventional switching power supply. FIG. 8B is a diagram showing the phase characteristics of the power supply output with respect to the output of the error amplifier that amplifies the error between the output voltage and the target voltage in the conventional switching power supply. FIG. 8 shows simulation results showing changes in the gain and phase of the power supply output when an AC input is applied to the output point of the error amplifier. As shown in FIG. 8B, the phase delay of the power supply output increases as the angular frequency ω of the error amplifier output increases, and the magnitude of the phase delay increases as the carrier frequency of PWM control decreases. Become prominent.

  In this regard, even if the design is made such that the phase from the output of the error amplifier to the power supply output is delayed by 90 °, the stability of the power supply output may be lost if it is delayed more than that. In FIG. 8, for example, when the control frequency region is around 100 kHz, the phase of the power supply output is delayed by 90 ° or more unless the carrier frequency is set to 10 MHz or higher. On the other hand, for example, when the carrier frequency is set to 2 MHz, the phase of the power output is delayed by 90 ° or more unless controlled in the control frequency region of 20 kHz or less. As a countermeasure, it can be considered to raise the carrier frequency. However, raising the carrier frequency may cause problems such as switching loss and switching noise in some cases, which may be difficult.

  Therefore, the step-down switching power supply 100 is detected by the current detector 5 so as to match the phase delay of the voltage feedback circuit including the error amplifier 8 for generating the PWM signal based on the output voltage VOUT of the power supply output. A delay circuit 16 is provided to delay the phase of the current feedback circuit comprising a sample and hold circuit 15 for performing phase lead compensation based on the inductor current. A detailed configuration example and operation of the step-down switching power supply 100 shown in FIG. 1 including the delay circuit 16 will be described. FIG. 2 is a diagram illustrating a first configuration example of the step-down switching power supply 100. FIG. 3 is a timing chart showing the operation of the first configuration example of the step-down switching power supply 100.

  When the switching element 2 is turned on / off according to the PWM signal (see FIGS. 3J and 3K), an inductor current flows through the inductor 4 as shown in FIG. As a basic operation, when the switching element 2A is turned on by the H level PWM signal (j), the inductor current increases, and when the switching element 2A is turned off by the L level PWM signal (j). Inductor current decreases.

  The inductor current (a) is converted into a voltage proportional to the magnitude of the current by the conversion resistor 5 </ b> A provided in the current detection unit 5 and input to the sample and hold circuit 15. The sample hold circuit 15 samples the conversion voltage by the conversion resistor 5A at the sample period according to the control clock signal (h) from the clock signal generation circuit 13A. The control clock signal (h) output from the clock signal generation circuit 13 </ b> A is a signal for generating a carrier frequency for PWM control that determines the switching period of the switching element 2. For example, the sample hold circuit 15 samples an analog voltage corresponding to the inductor current (a) at the rising (or falling) timing of the control clock signal (h). The sampled analog voltage is converted into a digital value by the A / D converter 18 and stored in the register 16 as a sampling value.

  The sampling value by the sampling hold circuit 15 is sequentially stored in the plurality of registers 16 through the A / D converter 18 according to the sampling timing based on the control clock signal (h). In the case of FIG. 2, three registers 16A, 16B, and 16C are provided. At the (n + 1) th sampling timing, the nth sampling value stored in the register 16A moves to the register 16B, and a new n + 1th sampling value is stored in the register 16A. At the (n + 2) th sampling timing, the nth sampling value stored in the register 16B is moved to the register 16C, the n + 1th sampling value stored in the register 16A is moved to the register 16B, and a new n + 2th sampling time is obtained. The sampling value is stored in the register 16A. As a result, the result of sampling two cycles before the present is stored in the register 16C. The sampling value stored in the register 16C is input to the inverting input terminal of the comparator 17A.

  On the other hand, the error amplifier 8 amplifies and outputs an error between the output voltage VOUT and its target voltage. The amplification factor of the error amplifier 8 may be set to an appropriate value from the relationship with other circuits. The superimposed signal (e) obtained by adding the ramp signal from the ramp signal generation circuit 9 to the output voltage (f) of the error amplifier 8 by the adder 10 is input to the non-inverting input terminal of the comparator 17A.

  The comparator 17A compares the sampling value (d) stored in the register 16C with the superimposed signal (e), and outputs an H level signal when the sampling value (d) is smaller than the superimposed signal (e). When the value (d) is larger than the superimposed signal (e), an L level signal is output (FIG. 3 (g)). Based on the comparison result of the comparator 17A, drive signals for the high-side switching element 2A and the low-side switching element 2B are generated.

  The output (g) of the comparator 17A is inverted and input to the reset terminal R of the flip-flop 13B via the inverter 17B. The control clock signal (h) is input to the set terminal S of the flip-flop 13B. The flip-flop 13B synchronizes the output (g) of the comparator 17A with the control clock signal (h). When the rising edge of the control clock signal (h) is input to the set terminal S, an H level signal is output from the output terminal Q, and the output (g) of the comparator 17A is inverted via the inverter 17B, thereby rising edge. Is input to the reset terminal R, an L level signal is output from the output terminal Q (see FIG. 3I).

  The output terminal Q is connected to one input terminal of an AND circuit 13F that outputs a drive signal for the high-side switching element 2A, and is connected to the other of the AND circuit 13F via a delay circuit 13C that delays and outputs the input signal. Connected to one input terminal. The output terminal Q is connected to one input terminal of an AND circuit 13G that outputs a drive signal for the low-side switching element 2B via an inverter 13E, and a delay circuit 13D that delays and outputs the input signal. To the other input terminal of the AND circuit 13G.

  When the reset terminal R is at the Lo level, the output terminal Q becomes the H level by the rise of the control clock signal (h). When the output terminal Q is switched from the L level to the H level, the L level is input to the AND circuit 13G due to the presence of the inverter 13E, so that the switching element 2B is turned off. In addition, after a predetermined time has elapsed since the output terminal Q is switched to H level by the delay circuit 13C, both inputs of the AND circuit 13F become H level, so that the switching element 2A is turned on. Therefore, the dead time shown in FIG. 3 can be provided by the delay circuit 13C so that the switching elements 2A and 2B are turned on at the same time and no through current flows. When the switching element 2A is turned on after the switching element 2B is turned off, the inductor current increases.

  Further, when the superimposed signal (e) input to the comparator 17A becomes smaller than the sampling value (d), the output of the comparator 17A is switched from H to L level. When the output of the comparator 17A is switched from H to L level, the reset terminal R of the flip-flop 13B is switched from L to H level by the inverter 17B, so that the output terminal Q becomes L level. When the output terminal Q is switched from the H level to the L level, the L level is input to the AND circuit 13F, so that the switching element 2A is turned off. Further, when the output terminal Q is switched from the H level to the L level, the H level is input to the AND circuit 13G due to the presence of the inverter 13E, and a predetermined time elapses after the output terminal Q is switched to the L level by the delay circuit 13D. After that, both the inputs of the AND circuit 13G become H level, so that the switching element 2B is turned on. Therefore, the delay circuit 13D can provide the dead time shown in FIG. 3 so that the switching elements 2A and 2B are turned on at the same time and no through current flows. When the switching element 2A is turned off, the inductor current decreases.

  Therefore, according to the first embodiment, the sampling value (d) two cycles before the current time stored in the register 16C can be compared with the superimposed signal (e). Can be adjusted.

  FIG. 4 is a diagram illustrating a second configuration example of the step-down switching power supply 100. FIG. 5 is a timing chart showing the operation of the second configuration example of the step-down switching power supply 100. The same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified. In the second configuration example, a plurality of sampling values of the inductor current are held as analog voltages in the plurality of capacitors 16 (16D, 16E, 16F) shown in FIG.

  When the switching element 2 is turned on / off according to the PWM signal (see FIGS. 5J and 5K), an inductor current flows through the inductor 4 as shown in FIG.

  The inductor current (a) is converted into an analog voltage proportional to the magnitude of the current by the conversion resistor 5 </ b> A and the operational amplifier 5 </ b> B provided in the current detection unit 5 and input to the sample and hold circuit 15. The operational amplifier 5B level-shifts the inductor current value converted into a voltage value by the conversion resistor 5A to a predetermined reference voltage VREF standard, and amplifies it with a predetermined amplification factor.

  The sample hold circuit 15 includes a plurality of switches 15 that perform switching operations in accordance with a plurality of different timing signals φ synchronized with the control clock signal (h), and a plurality of capacitors that are supplied with amplified voltages of inductor current values amplified by the operational amplifier 5B. With. The switch 15 may be a switching element such as a transistor, for example. Each period of the timing signal φ and the number of switches 15 and capacitors 16 are determined according to how many sampling values of the inductor current should be stored at each sampling timing. In the present embodiment, six switches 15A to 15F that perform switching operations according to timing signals φ1 to φ6 and three capacitors 16D to 16F are provided so that sampling values for three samplings can be stored. Each cycle of the timing signals φ1 to φ6 is three times the switching cycle of the switching element 2. Further, the timing signals φ1 to φ3 for storing the sampling values amplified by the operational amplifier 5B in the capacitor 16 are 120 ° out of phase with each other, and the sampling values stored in the capacitor 16 are applied to the inverting input terminal of the operational amplifier 17A. Timing signals φ4 to φ6 for output are also 120 ° out of phase with each other. The rising timing and falling timing of the timing signals φ1 to φ3 are synchronized with those of the control clock signal (h). The timing signal φ4 falls at the rising timing of the timing signal φ1, and the timing signal φ5 rises at the falling timing of the timing signal φ1. The timing signal φ5 falls at the rising timing of the timing signal φ2, and the timing signal φ6 rises at the falling timing of the timing signal φ2. The timing signal φ6 falls at the rising timing of the timing signal φ3, and the timing signal φ4 rises at the falling timing of the timing signal φ3.

  The n-th sampling value amplified by the operational amplifier 5B is supplied to the capacitor 16D through the switch 15A that is turned on by the timing signal φ1 in a state in which the switch 15D is off, and the switch 15A is turned off by the timing signal φ1. The voltage value of the immediately preceding capacitor 16D is sampled and held. Subsequently, the n + 1-th sampling value amplified by the operational amplifier 5B is supplied to the capacitor 16E via the switch 15B that is turned on by the timing signal φ2 in a state where the switch 15E is off, and the switch 15B is turned off by the timing signal φ2. As a result, the voltage value of the capacitor 16E immediately before is sampled and held. Subsequently, the n + 2th sampling value amplified by the operational amplifier 5B is supplied to the capacitor 16F via the switch 15C that is turned on by the timing signal φ3 in a state where the switch 15F is off, and the switch 15C is turned off by the timing signal φ3. As a result, the voltage value of the capacitor 16F immediately before is sampled and held.

  At this time, at the (n + 2) th sampling timing, the switch 15D is turned on by the timing signal φ4, whereby the nth sampling value stored in the capacitor 16D is input to the inverting input terminal of the comparator 17A. Then, at the (n + 3) th sampling timing, the switch signal 15D is turned off according to the timing signal φ4. Similarly, at the (n + 3) th sampling timing, when the switch 15E is turned on by the timing signal φ5, the (n + 1) th sampling value stored in the capacitor 16E is input to the inverting input terminal of the comparator 17A. Then, at the (n + 4) th sampling timing, the switch signal 15E is turned off according to the timing signal φ5. Similarly, at the (n + 4) th sampling timing, when the switch 15F is turned on by the timing signal φ6, the (n + 2) th sampling value stored in the capacitor 16F is input to the inverting input terminal of the comparator 17A. Then, at the (n + 5) th sampling timing, the switch signal 15F is turned off according to the timing signal φ6. That is, the sampling value of the inductor current two cycles before the present is input to the inverting input terminal of the comparator 17A (FIG. 5 (l)). When inputting the sampling value of the inductor current n cycles before the current to the inverting input terminal of the comparator 17A, similarly to the configuration shown in FIG. 4, n + 1 capacitors 16 are provided at both ends thereof. A switch 15 may be provided.

  On the other hand, the error amplifier 8 outputs an integrated value of the output voltage VOUT (FIG. 5 (f)). The superimposed signal (e) obtained by adding the voltage value converted by the resistor 10C and the output value of the error amplifier 8 after current conversion of the ramp signal from the ramp signal generation circuit 9 by the operational amplifier 10A and the current mirror circuit 10B, The signal is input to the non-inverting input terminal of the comparator 17A. The operational amplifier 10A, the current mirror circuit 10B, and the resistor 10C correspond to the adder 10 shown in FIG.

  The comparator 17A compares the sampling value stored in the capacitor 16 (any one of (b), (c), and (d)) with the superimposed signal (e), and when the sampled value is smaller than the superimposed signal (e). Outputs an H level signal, and outputs an L level signal when the sampling value is larger than the superimposed signal (e) (FIG. 5 (g)). Based on the comparison result of the comparator 17A, drive signals for the high-side switching element 2A and the low-side switching element 2B are generated. Since the following operations are the same as those in the first embodiment, a description thereof will be omitted.

  Therefore, according to the above-described second embodiment, it is possible to compare the sampling value (any one of (b), (c), and (d)) stored two times before the current stored in the capacitor 16 with the superimposed signal (e). As a result, the phase shift between the current feedback and the voltage feedback can be matched.

  FIG. 6 is a diagram showing a step-up switching power supply 200. FIG. 7 is a timing chart showing the operation of the step-up switching power supply 200. The same components as those in the first and second embodiments are denoted by the same reference numerals, and the description thereof is omitted or simplified.

  The inductor 4 flows through the inductor 4 as shown in FIG. 7A by turning on / off the switching element 2 in accordance with the PWM signal (see FIGS. 7J and 7K). As a basic operation, when the switching element 2B is turned on by the H level PWM signal (j), the inductor current increases, and when the switching element 2B is turned off by the L level PWM signal (j). Inductor current decreases.

  The inductor current (a) is converted into a voltage proportional to the magnitude of the current by the current detection unit 5 and input to the sample and hold circuit 15. The sampling value of the inductor current value sampled and held by the sample and hold circuit 15 is input to the inverting input terminal of the comparator 17 via the delay circuit 16 similar to that in the first and second embodiments.

  On the other hand, as in the first and second embodiments, the adder 10 outputs a superimposed voltage obtained by adding the amplified voltage from the error amplifier 8 and the ramp signal from the ramp signal generating circuit 9. The superimposed voltage from the adder 10 is input to the non-inverting input terminal of the comparator 17.

  As in the first and second embodiments, the comparator 17 compares the superimposed voltage from the adder 10 with the sampling value of the inductor current value stored via the delay circuit 16 and outputs the comparison result to the drive circuit 13. To do. The comparator 17 compares the sampling value (l) delayed by the delay circuit 16 with the superimposed signal (e), and outputs an H level signal when the sampling value is smaller than the superimposed signal (e). Is greater than the superimposed signal (e), an L level signal is output (FIG. 7 (g)). The drive circuit 13 outputs a drive signal (PWM signal) for driving the switching element 2 (2A, 2B) at a duty ratio such that the output voltage VOUT becomes a predetermined target voltage according to the output voltage level of the comparator 17 (FIG. 7 (j) (k)). Since the configuration of the drive circuit 13 is the same as that of the drive circuits of the first and second embodiments, description thereof is omitted. Each of the switching elements 2 performs a switching operation based on the drive signal, whereby the input voltage VIN from the reference power supply is stepped down.

  That is, when the low-side switching element 2B is turned on and the high-side switching element 2A is turned off based on the PWM signal, a current flows through the inductor 4 connected to the connection point between the switching elements 2A and 2B. Energy is stored. When the switching element 2B is turned off and the switching element 2A is turned on based on the PWM signal, the energy accumulated in the inductor 4 is accumulated in the output capacitor 6 connected to the output side of the inductor 4 via the switching element 2A. Is done. By performing such a switching operation, the smoothed output voltage VOUT is output from the output terminal 7. By providing the switching element 2A, heat generation by the diode 3 connected in parallel to the switching element 2A can be suppressed. In addition, if the diode 3 is provided, current can be passed, and therefore the configuration without the switching element 2A may be used.

  Therefore, according to the third embodiment, the sampling value (l) delayed by the delay circuit 16 can be compared with the superimposed signal (e), so that the phase shift between the current feedback and the voltage feedback can be matched. become.

Thus, according to the above-described embodiment, the inductor current IL (n−m) detected before the m switching period from the current nth switching period is controlled by the output of the error amplifier 8. The characteristics of PWM control are
ERROUT = R _S × IL (nm) (3)
VOUT (n + 1) = {R _S / [R _OUT /// R _LOAD // (1 / jωC _OUT )]}
× ERROUT (n + m) (4)
(N and m are integers of 1 or more, and n> m). That is, since the output voltage VOUT in the (n + 1) th switching cycle is controlled using the output voltage ERROUT (n + m) of the error amplifier in the (n + m) th switching cycle, the phase of the output voltage VOUT is returned.

  FIG. 9 is a diagram illustrating a gain-phase characteristic of PWM control when the carrier frequency is 2 MHz in the switching power supply according to the present embodiment. FIG. 9A is a diagram showing the gain characteristic of the power supply output VOUT with respect to the output of the error amplifier 8 in the switching power supply according to the present embodiment. FIG. 8B is a diagram showing the phase characteristic of the power supply output VOUT with respect to the output of the error amplifier 8 in the switching power supply according to the present embodiment. “Delay” in FIG. 9 indicates a time delayed by the delay circuit 16 for delaying the phase of the current feedback circuit (that is, a delay time between input and output of the delay circuit 16). As shown in FIG. 9B, by providing a delay time in the current feedback circuit by the delay circuit 16, the phase delay can be suppressed (the phase delay in the case of delay = 1 μs is the delay = 0 μs). Smaller than the case). As a result, the stability of the power supply output VOUT can be ensured.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

  For example, the carrier signal for generating the PWM signal is not limited to the ramp signal but may be another carrier signal such as a sine wave signal.

  Further, in the above-described embodiment, the comparator 17 compares the output value of the delay circuit 16 with the added value obtained by adding the output value of the error amplifier 8 and the ramp signal. The subtracted value obtained by subtracting the ramp signal from the output value of the delay circuit 16 may be compared with the output value of the error amplifier 8.

It is the schematic which showed the circuit structure of the pressure | voltage fall type | mold switching power supply 100 which is one Embodiment of this invention. 1 is a diagram illustrating a first configuration example of a step-down switching power supply 100. FIG. 3 is a timing chart showing the operation of the first configuration example of the step-down switching power supply 100. 3 is a diagram illustrating a second configuration example of the step-down switching power supply 100. FIG. 5 is a timing chart showing an operation of a second configuration example of the step-down switching power supply 100. 2 is a diagram showing a step-up switching power supply 200. FIG. 5 is a timing chart showing the operation of the step-up switching power supply 200. It is the figure which showed the gain-phase characteristic of PWM control in the conventional switching power supply. It is the figure which showed the gain-phase characteristic of PWM control in the switching power supply which concerns on a present Example.

Explanation of symbols

2, 2A, 2B Switching element 4 Inductor 5 Current detection unit 8 Error amplifier 9 Ramp signal generation circuit 13 Drive circuit 15 Sample hold circuit 16 Delay circuit 17, 17A Comparator

Claims (5)

A switching power supply device that includes a switching element and an inductor connected to the switching element, and controls the output voltage by driving the switching element for each switching cycle,
Current detecting means for detecting an inductor current flowing through the inductor;
Storage means for storing the detection result of the current detection means;
Error amplifying means for amplifying an error between the output voltage and a predetermined reference voltage;
The carrier signal is superimposed on the superimposition result obtained by superimposing the carrier signal on either the amplification result of the error amplification means or the detection result before m (m is an integer of 1 or more) stored in the storage means. A switching power supply device comprising: drive signal generation means for generating a drive signal for the switching element based on a comparison result with the other one that is not. The drive signal generation means includes
A flip-flop having a clock signal that generates the switching period as a set input and a signal based on the comparison result as a reset input,
The switching power supply device according to claim 1, wherein the driving signal is generated based on an output of the flip-flop.   The switching power supply device according to claim 1, wherein the detection result of the current detection unit is sequentially stored in the storage unit in synchronization with the switching period. A switching power supply device that includes a switching element and an inductor connected to the switching element, and controls the output voltage by driving the switching element for each switching cycle,
Current detecting means for detecting an inductor current flowing through the inductor;
Storage means for inputting a detection result of the current detection means;
Error amplifying means for amplifying an error between the output voltage and a predetermined reference voltage;
A comparator to which the detection result before m (m is an integer of 1 or more) stored in the storage means is input;
Wherein m stored in the superimposed result as the storage means for a carrier signal is superimposed on the amplification result of the error amplifying means (m is an integer of 1 or more) based on the comparison result by the comparator and the detection result of the previous switching period, And a drive signal generating means for generating a drive signal for the switching element. A switching power supply device that includes a switching element and an inductor connected to the switching element, and controls the output voltage by driving the switching element for each switching cycle,
Current detecting means for detecting an inductor current flowing through the inductor;
A comparator,
A storage unit that is provided between the current detection unit and the comparator and stores a detection result of the current detection unit;
Error amplifying means for amplifying an error between the output voltage and a predetermined reference voltage;
The carrier signal is superimposed on the superimposition result obtained by superimposing the carrier signal on either the amplification result of the error amplification means or the detection result before m (m is an integer of 1 or more) stored in the storage means. A switching power supply device comprising: drive signal generation means for generating a drive signal for the switching element based on a comparison result by the comparator with the other one that is not.

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