JP5145665B2 - Insulated gate bipolar transistor - Google Patents

Description

  The present invention relates to a vertical insulated gate bipolar transistor having a trench structure.

  In recent years, there has been a demand for miniaturization and high performance of power supply equipment in the field of power electronics. In order to meet these demands, research is being conducted on power semiconductor devices to achieve higher breakdown voltage and higher current, as well as lower loss, higher breakdown resistance, and higher speed. In general, a vertical insulated gate bipolar transistor (hereinafter referred to as IGBT) is used as a power semiconductor device capable of realizing a high breakdown voltage, a large current, and a low loss.

  The IGBT is driven by a MOS (metal / oxide film / semiconductor) gate. Two types of IGBTs are widely known: a planar type having a planar MOS gate structure and a trench type having a MOS gate structure in a trench groove. A planar IGBT has a planar gate structure in which a large number of planar MOS cells having a semiconductor surface as a channel region are arranged on a semiconductor substrate. The trench IGBT has a trench gate structure in which a large number of trench MOS cells having a trench sidewall as a channel region are arranged on a semiconductor substrate.

  In general, the trench type MOS device is considered to be more advantageous than the planar type MOS device in that the loss can be easily reduced by reducing the channel resistance. On the other hand, the trench type MOS device has a problem that the breakdown voltage is lowered when a high-speed operation and a low on-voltage are realized. Also, planar MOS devices have a simple MOS gate manufacturing process, are easy to manufacture at low cost, and have a gate insulating film on the semiconductor surface, so they are more reliable than trench MOS devices. Is also advantageous. On the other hand, the planar MOS device has a problem that it is difficult to increase the cell density.

  A conventional trench gate type IGBT and planar gate type IGBT will be described. Note that in this specification, the regions where n or p is listed mean that electrons or holes are majority carriers, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than the region where it is not attached.

FIG. 19 is a cross-sectional view showing a configuration of a conventional trench gate type IGBT. As shown in FIG. 19, p well region 2, p floating region 3, and trench gate 4 are provided on the first main surface side of the silicon substrate to be n ⁻ base region 1. The trench gate 4 includes a trench 5, a gate insulating film 6 that covers the inner peripheral surface of the trench 5, and a gate electrode 7 that fills the trench 5 through the gate insulating film 6. The trenches 5 are formed deeper than the p-well region 2 and the p-floating region 3 from the first main surface of the substrate, and are provided at a pitch similar to that depth.

In p well region 2, n ⁺ emitter region 8 is selectively provided in contact with trench gate 4 on the first main surface side of the substrate. An interlayer insulating film 9 such as silicate glass is provided on the first main surface of the substrate so as to cover the p floating region 3, the gate insulating film 6 and the gate electrode 7. An emitter electrode 10 such as a metal film is provided on the interlayer insulating film 9 and is electrically connected to both the n ⁺ emitter region 8 and the p well region 2 through a contact hole.

A p ⁺ collector region 11 and a collector electrode 12 such as a metal film electrically connected to the p ⁺ collector region 11 are provided on the second main surface side of the substrate. In the case where the IGBT is designed as a so-called punch-through type in order to enhance its performance, an n ⁺ buffer layer is provided between the n ⁻ base region 1 and the p ⁺ collector region 11. In the configuration shown in FIG. 19, a portion (channel region) between the n ⁻ base region 1 and the n ⁺ emitter region 8 on the trench side wall contributes to the gate-emitter capacitance, and the channel region around the trench 5. The part except for contributes to the gate-collector capacitance.

FIG. 20 is a cross-sectional view showing a configuration of a conventional planar gate type IGBT. As shown in FIG. 20, a p-well region 2 is selectively provided on the first main surface side of the silicon substrate to be the n ⁻ base region 1. In p well region 2, n ⁺ emitter region 8 is selectively provided on the first main surface side of the substrate. A planar gate 16 is provided on the first main surface of the substrate. The planar gate 16 includes a gate insulating film 6 that covers a portion of the p well region 2 between the n ⁺ emitter region 8 and the n ⁻ base region 1, and a gate electrode 7 on the gate insulating film 6.

Gate electrode 7 is insulated from semiconductor region including n ⁺ emitter region 8 and emitter electrode 10 by interlayer insulating film 9. The emitter electrode 10, the p ⁺ collector region 11, the collector electrode 12, and the n ⁺ buffer layer (not shown) have the same configuration as that of the trench gate type IGBT described above.

  Next, the operation of the IGBT will be described. Since there is no difference in electrical operation between the trench gate type IGBT and the planar gate type IGBT, the trench gate type IGBT will be described here.

First, the operation in the off state will be described. A voltage sufficiently lower than the gate threshold voltage is applied between the gate electrode 7 and the emitter electrode 10, and in this state, a voltage is applied between the collector electrode 12 and the emitter electrode 10. As a result, the pn junction composed of the n ⁻ base region 1 and the p well region 2 is in a reverse bias state, so that a depletion layer spreads mainly on the n ⁻ base region 1 side.

  Since the gate potential is low, holes in the p-well region 2 are attracted and accumulated on the surface of the p-well region 2 that is in contact with the trench gate 4 (or the planar gate 16 in the planar gate type IGBT). Accordingly, the trench gate (planar gate in the planar gate type IGBT) channel is turned off.

  Next, the operation in the on state will be described. A voltage sufficiently higher than the gate threshold voltage is applied between the gate electrode 7 and the emitter electrode 10, and in this state, a voltage is applied between the collector electrode 12 and the emitter electrode 10. Since the gate potential is high, electrons in the p-well region 2 are attracted to the surface of the p-well region 2 that is in contact with the trench gate 4 (planar gate 16 in the case of a planar gate IGBT).

Then, a region of the p-well region 2 that is in contact with the trench gate 4 (planar gate 16 in the case of a planar gate IGBT) is inverted by n to form a trench gate (planar gate in the case of a planar gate IGBT) channel. As a result, electrons are supplied from the n ⁺ emitter region 8 through the channel to the n ⁻ base region 1 and flow toward the positive potential p ⁺ collector region 11.

Electrons when flowing into the p ⁺ collector region 11, holes are injected into n ⁺ buffer layer (not shown) from the p ⁺ collector region 11. This hole causes conductivity modulation in the n ⁻ base region 1. If the lifetime of the holes in the n ⁻ base region 1 is sufficiently long, the holes reach the vicinity of the trench gate channel and are sucked into the p-well region 2 having a low potential.

  However, the conventional trench gate type IGBT described above has the following problems in the off state. In the off state, only a slight leakage current generated from the inside of the depletion layer flows between the collector electrode 12 and the emitter electrode 10. Accordingly, the impedance of the collector electrode 12 and the emitter electrode 10 is increased. As the collector voltage rises, the electric field inside the IGBT increases accordingly, but the potential at the bottom of the trench gate 4 is substantially the same as that of the gate electrode 7.

On the other hand, the potential of the n ⁻ base region 1 located below the p well region 2 at the same depth position as the bottom of the trench gate 4 is caused by donor ions between the position and the p well region 2. It rises above the potential (emitter potential) of the p-well region 2. In particular, the electric field tends to be strong at the corner of the bottom of the trench gate 4. At this time, if the electric field inside the IGBT exceeds the critical electric field and the impact occurs strongly, the leakage current increases abruptly between the collector electrode 12 and the emitter electrode 10, thereby causing the IGBT to breakdown.

In order to avoid this and obtain a high breakdown voltage, it is necessary to increase the voltage drop present in the depletion layer before reaching the critical electric field. For that purpose, the n ⁻ base region 1 is thickened to reduce the impurity concentration of the n ⁻ base region 1, the bottom corner of the trench gate 4 is rounded, and the interval between the trench gates 4 is increased. It has been reported that the electric field at the bottom corner of the trench gate 4 is reduced by narrowing (see, for example, Non-Patent Document 1).

Further, the conventional trench gate type IGBT has the following problems in the on state. In the ON state, since the density of electrons and holes in the n ⁻ base region 1 is increased, the impedances of the collector electrode 12 and the emitter electrode 10 are decreased. However, since many holes are sucked into the p-well region 2, the injection of electrons from the trench gate channel into the n ⁻ base region 1 is somewhat limited. Therefore, a low on-voltage cannot be obtained.

In order to supply more electrons from the trench gate channel side, it is necessary to reduce the amount of holes flowing into the p-well region 2. As a configuration for that purpose, a configuration in which the pitch of the trench gates 4 is narrowed or the trench gates 4 are formed deeply has been reported (for example, see Non-Patent Document 2). Further, a configuration has been proposed in which a portion of the trench gate 4 without the emitter contact of the p-well region 2 or the n ⁺ emitter region 8 is inserted between the normal trench IGBT portions (for example, Patent Document 1, Non-Patent Document). 2). In addition, a configuration in which an n-type layer having a high impurity concentration is provided under the p-well region 2 has been proposed (see, for example, Patent Document 2).

Further, in the conventional planar gate type IGBT, since the p-well region 2 is also diffused in the lateral direction, there are the following problems in the on state. Since a larger number of holes are sucked into the p-well region 2 than in the above-described configuration in which the trench contact type IGBT is inserted into the portion of the trench gate 4 without the emitter contact in the p-well region 2 or the n ⁺ emitter region 8, the planar The injection of electrons from the gate channel into the n ⁻ base region 1 is somewhat limited. Therefore, a low on-voltage cannot be obtained.

  In order to supply more electrons from the planar gate channel side, it is necessary to reduce the amount of holes flowing into the p-well region 2. As a configuration for that purpose, a configuration is proposed in which the interval between the p-well regions 2 is increased. A configuration in which an n-type layer having a high impurity concentration is provided under the p-well region 2 has been proposed (see, for example, Patent Document 2). Further, by providing a trench 5 in the central portion of the p-well region 2 and being connected to the emitter electrode 10 through a dielectric film, the breakdown voltage can be increased and the concentration of the n-type substrate can be indirectly increased. It has been proposed (see, for example, Patent Document 3).

Japanese Patent Laid-Open No. 7-50405 JP-A-9-326486 JP 2001-85688 A Ken'ichi Matsushita, two others, "Blocking Voltage Design Consideration for Deep Trench MOS Gate High Power Devices), Proceedings of 1995 International Symposium on Power Semiconductor Devices & ICs, p. 256-260 Mitsuhiko Kitagawa, 6 others, “4500V IEGTs having Switching Characteristics Superior to GTO”, Proceedings of 1995. International Symposium on Power Semiconductor Devices & ICs, p. 486-491

  However, in the trench gate type IGBT in which the interval between the trench gates is narrowed, the area of the trench gate per unit area increases, so that the gate capacity increases, and the manufacturing limit in manufacturing the IGBT. The problem arises that it becomes difficult. In addition, the configuration in which the pitch of the trench gate is narrowed, the configuration in which the trench gate is formed deeply, and the configuration in which the portion of the trench gate without the emitter contact or emitter region in the p-well region is inserted causes a problem that the gate capacitance increases. Further, in the configuration in which the trench gate is formed deeply and the configuration in which the high concentration n-type layer is provided under the p-well region, there arises a problem that the breakdown voltage decreases.

  Further, in the planar gate type IGBT, the configuration in which the interval between the p-well regions is widened causes a problem that the gate capacitance increases. Further, in the configuration in which the interval between the p-well regions is widened and the configuration in which the high-concentration n-type layer is provided under the p-well region, there is a problem that the electric field in the curvature portion of the p-well region becomes strong and the breakdown voltage decreases. Further, in the configuration in which the trench is provided in the central portion of the p-well region, the amount of holes sucked into the p-well region is not changed, so that the amount of electrons supplied from the planar gate channel cannot be increased.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an IGBT having a low on-voltage and a high breakdown voltage in order to solve the above-described problems caused by the prior art. Another object of the present invention is to provide an IGBT having a low on-voltage and a small gate capacitance.

In order to solve the above-described problems and achieve the object, an IGBT according to the present invention includes a second conductivity type collector region formed on a first main surface of a semiconductor substrate serving as a first conductivity type base region, A collector electrode electrically connected to the two-conductivity type collector region, a plurality of trenches formed in a straight line on the second main surface of the semiconductor substrate, and the adjacent trenches of the semiconductor substrate. A second conductivity type well region selectively formed so as to be alternately arranged with the first conductivity type base region along the longitudinal direction of the trench in the region between the trenches, and the second conductivity type well region The first conductivity type emitter region selectively formed in the first conductivity type emitter region and the second conductivity type well region are sandwiched between the first conductivity type emitter region and the first conductivity type base region, and in the longitudinal direction of the trench. A gate insulating film in which a channel is formed on the second major surface of said semiconductor substrate region formed me, a gate electrode formed on the gate insulating film, the first conductive type emitter region and An emitter electrode electrically connected to the second conductivity type well region, and having the inter-trench region without the second conductivity type well region among the plurality of inter-trench regions, In the inter-trench region without the conductive type well region, only the first conductive type base region is exposed on the second main surface of the semiconductor substrate, and the trench is filled with a conductor via an insulating film. The conductor in the trench is electrically connected to the emitter electrode .

Further, IGBT according to this invention is the invention described above, the trench is characterized in that it is formed at regular intervals. Further, IGBT according to this invention is the invention described above, the gate insulating film, the upper part of the first conductivity type base region, thicker than the upper part of the second conductivity type well region Features.

Further, IGBT according to this invention is the invention described above, wherein the insulating film in the trench is a silicon oxide film. Further, IGBT according to this invention is the invention described above, wherein the thickness of the silicon oxide film is 150nm or more.

Further, IGBT according to this invention is the invention described above, wherein the thickness of the silicon oxide film is 200nm or more.

In the IGBT according to the present invention, the second main surface of the semiconductor substrate is covered with an interlayer insulating film in the inter- trench region without the second conductivity type well region. A conductive floating region is provided. In the IGBT according to the present invention, the inter-trench regions with the second conductivity type well region and the inter-trench regions without the second conductivity type well region are alternately arranged in the above-described invention. It is characterized by.

  According to the present invention, the on-voltage can be reduced by providing the trench structure and the gate structure separately as in the case of the conventional trench gate type IGBT. Further, the trench interval can be freely set by forming the MOS channel in the longitudinal direction of the trench. For example, a high breakdown voltage can be obtained by narrowing the trench interval. Furthermore, since the gate electrode is not formed in the trench, the conventional problems such as an increase in gate capacitance and a decrease in breakdown voltage can be easily avoided. That is, the thickness of the insulating film in the trench can be set freely. For example, the trench can be filled with only an insulating film. Further, the trench interval can be narrowed without increasing the gate capacitance. Moreover, it is not necessary to perform the treatment on the trench sidewall after the trench formation.

  Further, since the gate is similar to the conventional planar structure, high reliability can be obtained. Further, the gate capacitance is smaller than that of the conventional planar gate type IGBT. Furthermore, since the breakdown voltage is determined at the bottom of the trench, the breakdown voltage can be increased. That is, it is possible to overcome the problem that the breakdown voltage is lowered at the curvature portion of the p-well region, which was a problem in the conventional planar gate type IGBT. Therefore, since the measure for reducing the on-voltage can be applied without restriction, an IGBT having a small gate capacitance can be obtained at a low cost.

  According to the IGBT according to the present invention, there is an effect that an IGBT having a low on-voltage and a high breakdown voltage can be obtained. In addition, an IGBT having a low on-voltage and a small gate capacitance can be obtained.

  Exemplary embodiments of an IGBT according to the present invention will be described below in detail with reference to the accompanying drawings. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

Embodiment 1 FIG.
FIG. 1 is a partial cross-sectional perspective view showing the configuration of the IGBT according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view showing a cross-sectional configuration parallel to the trench longitudinal direction of the IGBT shown in FIG. 1 and passing through the inter-trench region. FIG. 3 is a cross-sectional view showing a cross-sectional configuration parallel to the trench lateral direction of the IGBT shown in FIG. 1 and passing through the p-well region and not passing through the n ⁺ emitter region. Here, the inter-trench region is a semiconductor region sandwiched between adjacent trenches.

As shown in FIGS. 1 to 3, a p-well region 22 is selectively formed on the first main surface side of the silicon substrate that becomes the n ⁻ base region 21. A plurality of trenches 25 are formed in parallel to each other on the first main surface side of the substrate. Each trench 25 has a linear planar shape and reaches the n ⁻ base region 21 deeper than the p-well region 22. In the inter-trench region, n ⁻ base regions 21 and p-well regions 22 alternately appear on the first main surface of the substrate in the longitudinal direction of the trench 25 (see FIGS. 1 and 2).

The n ⁻ base region 21 and the p well region 22 appear on the first main surface of the substrate in the same manner in adjacent inter-trench regions. That is, when looking along the longitudinal direction of the trench 25 from the left front side of FIG. 1 to the right hand back side, when the p-well region 22 appears on the first main surface of the substrate in a certain inter-trench region, back to back If the p-well region 22 appears on the first main surface of the substrate in the adjacent inter-trench region and the n ⁻ base region 21 appears in the inter-trench region, An n ⁻ base region 21 appears (see FIGS. 1 and 3). Therefore, in the cross-section in the short direction of the trench 25 passing through the p well region 22, the p well region 22 is divided into a plurality of regions by the trench 25 (see FIG. 3).

In p well region 22, n ⁺ emitter region 28 is selectively provided on the first main surface side of the substrate. The gate insulating film 26, the inter-trench regions, the p-well region 22, n ⁺ emitter region 28 and the n ^- between the base region 21, and the n ^- is provided in contact with the surface of the base region 21. The gate electrode 27 is provided on the gate insulating film 26. That is, the gate structure is a structure in which the gate electrode 27 is provided on the first main surface of the substrate via the gate insulating film 26, that is, a planar gate structure.

When in the on state, the channel is formed in the longitudinal direction of the trench 25 along the surface of the p-well region 22 between the n ⁺ emitter region 28 and the n ⁻ base region 21. In FIG. 1 and FIG. 2, a portion where the channel is formed (channel region) is indicated by a one-dot chain line and denoted by reference numeral 41. Each of the gate insulating film 26 and the gate electrode 27 extends along the trench 25 to the adjacent cell, and is connected to the gate insulating film 26 and the gate electrode 27 of the adjacent cell.

The gate electrode 27 is covered with an interlayer insulating film 29. The emitter electrode 30 (not shown in FIG. 1) is provided on the interlayer insulating film 29. Emitter electrode 30 is in contact with and electrically connected to p well region 22 and n ⁺ emitter region 28 via a contact hole. The exposed surface on the first main surface side of the substrate including the emitter electrode 30 is covered with a protective film (not shown).

The trench 25 is filled with a conductor 43 with an insulating film 42 interposed therebetween. The conductor 43 is insulated from the n ⁻ base region 21 by the insulating film 42. In the semiconductor device having such a structure, the maximum electric field strength usually appears at the bottom of the trench. The conductor 43 is electrically connected to the emitter electrode 30 in a region not shown in the figure. On the second main surface side of the substrate, a p ⁺ collector region 31 and a collector electrode 32 electrically connected to the p ⁺ collector region 31 are provided.

When the IGBT is a punch-through type, an n ⁺ layer is provided as a field stop layer between the n ⁻ base region 21 and the p ⁺ collector region 31. In the configuration of the first embodiment, the channel region 41 between the n ⁻ base region 21 and the n ⁺ emitter region 28 contributes to the gate-emitter capacitance, and between the adjacent p well regions 22 in the n ⁻ base region 21. This part contributes to the gate-collector capacitance. In FIG. 1, a part of the gate insulating film 26, the gate electrode 27, the interlayer insulating film 29, and the emitter electrode 30 are omitted.

The breakdown voltage class of the IGBT according to the first embodiment is not particularly limited, but in the first embodiment, for example, it is set to a 600V class. An example is given in that case. The semiconductor substrate is an n-type silicon substrate having a resistivity of 30 Ωcm. The trenches 25 are formed in stripes at intervals of 5 μm, and the depth is 5 μm. The insulating film 42 and the conductor 43 in the trench 25 are a silicon oxide film and highly doped polysilicon, respectively. The thicknesses of the p ⁺ collector region 31 and the field stop layer (not shown) are 0.3 μm and 3 μm, respectively. The thickness of the semiconductor substrate is 65 μm.

  Next, the results of examining the relationship between the thickness of the insulating film 42 in the trench 25 and the breakdown voltage of the IGBT according to the first embodiment will be described. The electrical characteristics of the semiconductor substrate, the dimensions of each part, the material of each part, etc. are as described above. The curvature at the bottom of the trench is 0.6 μm. FIG. 4 is a characteristic diagram showing the relationship between the thickness of the insulating film in the trench and the breakdown voltage of an IGBT having a breakdown voltage class of 600V. In FIG. 4, the ◯ and ● plots are obtained when the protruding amount of the trench 25 from the p-well region 22 is 4.0 μm and 2.0 μm, respectively.

  FIG. 5 is a characteristic diagram showing the relationship between the thickness of the insulating film in the trench and the breakdown voltage of the IGBT whose breakdown voltage class is 1200 V class. In the 1200V class IGBT, the resistivity of the n-type semiconductor substrate is 65 Ωcm, and the thickness thereof is 135 μm. Other than that, it is the same as the 600V class. In FIG. 5, the ▪ plot is when the protrusion amount of the trench 25 from the p-well region 22 is 2.0 μm. In both FIG. 4 and FIG. 5, the insulating film 42 is a silicon oxide film.

  In the present embodiment, the breakdown voltage determining factor of the IGBT may be at the bottom of the trench. Further, since the conductor 43 embedded in the trench 25 via the insulating film 42 is not a gate electrode, the thickness of the insulating film 42 is independent of the threshold value and the like. Therefore, the thickness of the insulating film 42 can be freely designed as a function of the breakdown voltage only.

Here, there is no particular determinant of how much the breakdown voltage of the IGBT should be, but in general, the higher the breakdown voltage of the IGBT, the thinner the n ⁻ base region 21 is. it can. It is desirable that the n ⁻ base region 21 is thin because the generation loss of the IGBT can be reduced. In order to obtain a structure capable of realizing a withstand voltage of 95% of the maximum withstand voltage, the thickness of the insulating film 42 inside the trench 25 is 150 nm or more, preferably 200 nm or more, more preferably 300 nm or more, as shown in FIGS. You can see that

Next, the results of examining the impact ionization rate at the time of avalanche breakdown by device simulation for the IGBT of the first embodiment will be described. 6 to 9 are characteristic diagrams showing device simulation results of IGBTs having a withstand voltage class of 600 V class, and FIGS. 6, 7, 8 and 9 respectively show the thickness of the insulating film in the trench (T _Gox ) Is 50 nm, 200 nm, 300 nm and 400 nm. 6 to 9, it can be seen that the impact ionization rate is high at the bottom of the trench regardless of whether the insulating film 42 in the trench 25 is thick or thin.

  Next, with respect to the IGBT of the first embodiment, the result of examining the relationship between the thickness of the insulating film 42 in the trench 25 and the breakdown voltage by changing the curvature of the bottom of the trench will be described. FIG. 10 is a characteristic diagram showing the relationship between the thickness of the insulating film in the trench and the breakdown voltage of the IGBT whose breakdown voltage class is 600V class. In FIG. 10, ◯, Δ, and □ plots are obtained when the curvature of the trench bottom is 0.4 μm, 0.6 μm, and 1.0 μm, respectively.

  From FIG. 10, when the curvature of the bottom of the trench is in the range of 0.4 μm to 1.0 μm, the maximum breakdown voltage can be obtained by setting the thickness of the insulating film 42 inside the trench 25 to 150 nm or more, preferably 200 nm or more. It can be seen that a withstand voltage of 95% can be realized. It can also be seen that the thickness of the insulating film 42 capable of realizing a withstand voltage of 95% of the maximum withstand voltage is reduced as the curvature of the trench bottom becomes 1.0 μm, 0.6 μm, and 0.4 μm. Therefore, in the range where the curvature at the bottom of the trench is 1.0 μm or less, if the thickness of the insulating film 42 in the trench 25 is 150 nm or more, preferably 200 nm or more, a breakdown voltage of 95% of the maximum breakdown voltage can be obtained. Can be estimated.

Embodiment 2. FIG.
FIG. 11 is a partial cross-sectional perspective view showing the configuration of the IGBT according to the second embodiment of the present invention. As shown in FIG. 11, in the IGBT of the second embodiment, the p-well region 22 appears in the adjacent inter-trench region when viewed along the longitudinal direction of the trench 25 from the front left side to the back right hand in FIG. The position is shifted. Accordingly, in the cross section in the short direction of the trench 25, the n ⁻ base region 21 and the p well region 22 appear alternately in a plurality of inter-trench regions. Other configurations are the same as those of the first embodiment. In the first embodiment described above, it is obvious that the region with the highest electric field strength is the bottom of the trench and the portion farthest from the p-well region 22 in the longitudinal direction of the trench 25. Accordingly, by shifting the arrangement of the p-well region 22 in the short direction of the trench as in the second embodiment, a higher breakdown voltage than that in the first embodiment can be obtained. In FIG. 11, a part of the gate insulating film 26 and the gate electrode 27, the interlayer insulating film and the emitter electrode are omitted.

Embodiment 3 FIG.
FIG. 12 is a cross-sectional view showing the configuration of the IGBT according to the third embodiment of the present invention, and corresponds to the cross section shown in FIG. As shown in FIG. 12, in the IGBT of the third embodiment, the portion of the gate insulating film 26 above the n ⁻ base region 21 is made thicker than the other portions. Other configurations are the same as those of the first embodiment. With this configuration, the gate capacity of the hot portion of the gate insulating film 26 is reduced. Therefore, compared with the first embodiment, the gate capacitance, particularly the feedback capacitance that strongly affects the switching time can be reduced, which is effective as a high-speed switching type IGBT.

Embodiment 4 FIG.
FIG. 13 is a partial cross-sectional perspective view showing the configuration of the IGBT according to the fourth embodiment of the present invention. As shown in FIG. 13, in the IGBT of the fourth embodiment, the p-well region 22 is not formed in a part of the inter-trench region. Although not particularly limited, the inter-trench region where the p-well region 22 is formed and the inter-trench region where the p-well region 22 is not formed are alternately arranged. Other configurations are the same as those of the first embodiment. With such a configuration, the area of the p-well region 22 in contact with the emitter electrode becomes smaller than that in the first embodiment, and the amount of holes flowing into the p-well region 22 can be reduced. Thereby, the supply of electrons from the channel side is increased to increase the injection efficiency. Further, since the gate area is reduced, the gate capacitance can be made smaller than that in the first embodiment. In FIG. 13, a part of the gate insulating film 26, the gate electrode 27, the interlayer insulating film 29, and the emitter electrode are omitted. The configuration of the inter-trench region where the p-well region 22 is not formed is not questioned.

Embodiment 5 FIG.
FIG. 14 is a partial cross-sectional perspective view showing the configuration of the IGBT according to the fifth embodiment of the present invention. As shown in FIG. 14, the IGBT of the fifth embodiment is the same as the IGBT of the fourth embodiment, except that a p floating region 44 is provided in the inter-trench region where the p well region 22 is not formed. The p floating region 44 is not electrically connected to any electrode. That is, the p floating region 44 floats in terms of potential. Other configurations are the same as those of the first embodiment. In FIG. 14, a part of the gate insulating film 26, the gate electrode 27, the interlayer insulating film 29, and the emitter electrode are omitted.

Embodiment 6 FIG.
FIG. 15 is a partial cross-sectional perspective view showing the configuration of the IGBT according to the sixth embodiment of the present invention. As shown in FIG. 15, in the IGBT of the sixth embodiment, the p well region 45 is formed in the inter-trench region where the p well region 22 is not formed in the IGBT of the fourth embodiment. The emitter electrode 30 is connected through a region having a large resistance component 46. Other configurations are the same as those of the first embodiment. In FIG. 15, a part of the gate insulating film 26, the gate electrode 27, the interlayer insulating film 29, and the emitter electrode 30 is omitted.

  Next, the results of examining the relationship between the thickness of the insulating film 42 in the trench 25 and the breakdown voltage of each IGBT according to the fourth to sixth embodiments will be described. The electrical characteristics, the dimensions of each part, the material of each part, and the like of the semiconductor substrate are as described in the first embodiment. In any case, the withstand voltage class is a 600V class. FIG. 16 is a characteristic diagram showing the relationship between the thickness of the in-trench insulating film and the breakdown voltage of each IGBT according to the fourth to sixth embodiments. In FIG. 16, the ◯, Δ, and □ plots are for the fourth embodiment, the fifth embodiment, and the sixth embodiment, respectively. From FIG. 16, it can be seen that the fourth embodiment and the fifth embodiment are substantially the same, and are close to the maximum withstand voltage in the order of the fourth embodiment, the fifth embodiment, and the sixth embodiment, and are advantageous.

Embodiment 7 FIG.
FIG. 17 is a partial cross-sectional perspective view showing the configuration of the IGBT according to the seventh embodiment of the present invention. As shown in FIG. 17, the IGBT of the seventh embodiment has a trench 25 filled with an insulating film 47. This insulating film 47 is, for example, a silicon oxide film. Other configurations are the same as those of the first embodiment. In FIG. 17, a part of the gate insulating film 26, the gate electrode 27, the interlayer insulating film 29, and the emitter electrode are omitted.

Embodiment 8 FIG.
FIG. 18 is a partial cross-sectional perspective view showing the configuration of the IGBT according to the eighth embodiment of the present invention. As shown in FIG. 18, the IGBT of the eighth embodiment has an n-type relatively low concentration so as to surround the p-well region 22 between the p-well region 22 and the n ⁻ base region 21 in the inter-trench region. A region 48 is provided. Other configurations are the same as those of the first embodiment. With this configuration, the diffusion amount in the trench longitudinal direction of the p well region 22 can be reduced, and the area of the p well region 22 contacting the emitter electrode can be made smaller than that in the first embodiment. The amount of holes flowing into the well region 22 can be reduced. Thereby, the supply of electrons from the channel side can be increased and the injection efficiency can be increased. In FIG. 18, a part of the gate insulating film 26, the gate electrode 27, the interlayer insulating film 29, and the emitter electrode are omitted.

  As described above, according to the first to eighth embodiments, since the trench structure and the gate structure are provided separately, the on-voltage can be reduced as in the case of the conventional trench gate type IGBT. . Further, since the channel region 41 can be formed in the longitudinal direction of the trench 25, the interval between the trenches 25 can be freely set. For example, a high breakdown voltage can be obtained by narrowing the trench interval. Furthermore, since the gate electrode is not formed in the trench 25, it is possible to easily avoid conventional problems such as an increase in gate capacitance and a decrease in breakdown voltage. Further, the trench interval can be narrowed without increasing the gate capacitance. Moreover, it is not necessary to perform the treatment on the trench sidewall after the trench formation.

  Further, since the gate is similar to the conventional planar structure, high reliability can be obtained. Further, the gate capacitance is smaller than that of the conventional planar gate type IGBT. Furthermore, since the breakdown voltage is determined at the bottom of the trench, the problem that the breakdown voltage decreases at the curvature portion of the p-well region 22 can be overcome and the breakdown voltage can be increased. Therefore, since the measure for reducing the on-voltage can be applied without restriction, an IGBT having a small gate capacitance can be obtained at a low cost.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the electrical characteristic values and dimensions described in the embodiments are examples, and the present invention is not limited to these values. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the IGBT according to the present invention is useful for a power semiconductor device, and is particularly suitable for a power semiconductor device used for power supply equipment and the like.

It is a fragmentary sectional perspective view which shows the structure of IGBT concerning Embodiment 1 of this invention. It is sectional drawing which shows the structure of the cross section which is parallel to the trench longitudinal direction of IGBT shown in FIG. 1, and passes through the area | region between trenches. FIG. 2 is a cross-sectional view showing a cross-sectional configuration that is parallel to the trench lateral direction of the IGBT shown in FIG. 1 and that passes through a p-well region and does not pass through an n ⁺ emitter region. It is a characteristic view which shows the relationship between the thickness of the insulating film in a trench of 600V class IGBT concerning Embodiment 1 of this invention, and a proof pressure. It is a characteristic view which shows the relationship between the thickness of the insulating film in a trench of 1200V class IGBT concerning Embodiment 1 of this invention, and a proof pressure. It is a characteristic view which shows the device simulation result which shows the impact ionization rate at the time of the avalanche breakdown of IGBT concerning Embodiment 1 of this invention. It is a characteristic view which shows the device simulation result which shows the impact ionization rate at the time of the avalanche breakdown of IGBT concerning Embodiment 1 of this invention. It is a characteristic view which shows the device simulation result which shows the impact ionization rate at the time of the avalanche breakdown of IGBT concerning Embodiment 1 of this invention. It is a characteristic view which shows the device simulation result which shows the impact ionization rate at the time of the avalanche breakdown of IGBT concerning Embodiment 1 of this invention. It is a characteristic view which shows the relationship between the curvature of the trench bottom part of 600V class IGBT concerning Embodiment 1 of this invention, the thickness of the insulating film in a trench, and a proof pressure. It is a fragmentary sectional perspective view which shows the structure of IGBT concerning Embodiment 2 of this invention. It is sectional drawing which shows the structure of IGBT concerning Embodiment 3 of this invention. It is a fragmentary sectional perspective view which shows the structure of IGBT concerning Embodiment 4 of this invention. It is a fragmentary sectional perspective view which shows the structure of IGBT concerning Embodiment 5 of this invention. It is a partial cross section perspective view which shows the structure of IGBT concerning Embodiment 6 of this invention. It is a characteristic view which shows the relationship between the thickness of the insulating film in a trench of 600V class IGBT concerning Embodiments 4-6 of this invention, and a proof pressure. It is a fragmentary sectional perspective view which shows the structure of IGBT concerning Embodiment 7 of this invention. It is a partial cross section perspective view which shows the structure of IGBT concerning Embodiment 8 of this invention. It is sectional drawing which shows the structure of the conventional trench gate type IGBT. It is sectional drawing which shows the structure of the conventional planar gate type IGBT.

Explanation of symbols

21 n ⁻ base region 22 p well region 25 trench 26 gate insulating film 27 gate electrode 28 n ⁺ emitter region 30 emitter electrode 31 p ⁺ collector region 32 collector electrodes 42 and 47 insulating film 43 conductor 44 p floating region

Claims (8)

A second conductivity type collector region formed on the first main surface of the semiconductor substrate to be the first conductivity type base region;
A collector electrode electrically connected to the second conductivity type collector region;
A plurality of trenches formed in a straight line on the second main surface of the semiconductor substrate;
A second conductivity type selectively formed so as to be alternately arranged with the first conductivity type base region along the longitudinal direction of the trench in a region between the trenches between the adjacent trenches of the semiconductor substrate. A well region;
A first conductivity type emitter region selectively formed in the second conductivity type well region;
A second region of the semiconductor substrate in a region of the second conductivity type well region sandwiched between the first conductivity type emitter region and the first conductivity type base region and having a channel formed along the longitudinal direction of the trench . A gate insulating film formed on the main surface of
A gate electrode formed on the gate insulating film;
An emitter electrode electrically connected to the first conductivity type emitter region and the second conductivity type well region;
With
Among the plurality of inter-trench regions, the inter-trench region without the second conductivity type well region,
In the region between the trenches without the second conductivity type well region, only the first conductivity type base region is exposed on the second main surface of the semiconductor substrate ,
The trench is filled with a conductor via an insulating film;
The insulated gate bipolar transistor , wherein the conductor in the trench is electrically connected to the emitter electrode .   2. The insulated gate bipolar transistor according to claim 1, wherein the trenches are formed at equal intervals.   3. The insulated gate bipolar according to claim 1, wherein a portion of the gate insulating film above the first conductivity type base region is thicker than a portion above the second conductivity type well region. Transistor. The insulated gate bipolar transistor according to claim 1, wherein the insulating film in the trench is a silicon oxide film. 5. The insulated gate bipolar transistor according to claim 4, wherein the thickness of the silicon oxide film is 150 nm or more. 5. The insulated gate bipolar transistor according to claim 4, wherein the thickness of the silicon oxide film is 200 nm or more. A second conductivity type floating region formed by covering the second main surface of the semiconductor substrate with an interlayer insulating film is provided in the inter-trench region without the second conductivity type well region. The insulated gate bipolar transistor as described in any one of Claims 1-6. The inter-trench region with the second conductivity type well region and the inter-trench region without the second conductivity type well region are alternately arranged. An insulated gate bipolar transistor as described in 1.

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