JP5149115B2 - Semiconductor test equipment - Google Patents

Description

  The present invention relates to a semiconductor test apparatus, and more particularly to sequence control of pattern generation instructions.

  FIG. 5 is a block diagram showing a configuration example of a conventional semiconductor test apparatus. In FIG. 5, a sequence control circuit 100 for controlling a sequence of pattern generation instructions described in a program, an instruction memory 200 for storing pattern generation instructions, a pattern generation circuit 300 capable of operations such as addition and subtraction, and an IC under test 500 Comparator 400 for judging whether the quality is good or bad.

  The program of the semiconductor test apparatus is converted into machine language by a computer such as a workstation. The converted machine language is transferred to a hardware instruction memory and various registers before executing the test.

  The sequence control circuit 100 outputs a program counter signal a according to an instruction described in the program. The instruction memory 200 is accessed by a program counter signal a serving as a memory address, and outputs a pattern generation instruction b. The pattern generation circuit 300 generates a test pattern c and an expected pattern d to be supplied to the IC under test 500 in accordance with the pattern generation instruction b. The comparator 400 compares the expected pattern d from the pattern generation circuit with the output signal e from the IC under test 500 to determine pass / fail of the IC under test 500.

  FIG. 6 shows an example of a program in the semiconductor test apparatus of FIG. 5, which is composed of a sequence control instruction and a pattern generation instruction. The sequence control instruction “NOOP” is an instruction that executes the line described as “NOOP” and increments the program counter. “LOOP” is an instruction for jumping a program counter until an instruction from a designated line to a line described as “LOOP” is executed a designated number of times. In this example, “6” is the specified number of times, and “AA” is the row specification. Since the line designated by “AA” is the same as the line described as “LOOP”, this line is executed six times.

  FIG. 7 is a timing chart for explaining the operation when the program of FIG. 6 is executed by the semiconductor test apparatus of FIG. In the instruction memory 200, an instruction “X = 0” at address 0, “X = X + 1” at address 1, “X = 0” at address 2, is set by the computer.

  When the test of the IC under test 500 starts, the sequence control circuit 100 generates the program counter signal a as “0, 1, 1, 1, 1, 1, 1, 2” according to the program. The instruction memory 200 receives the program counter signal a and sets the pattern generation instruction b to “X = 0”, “X = X + 1”, “X = X + 1”, “X = X + 1”, “X = X + 1”, “X = X + 1”. , “X = X + 1”, and “X = 0”. The pattern generation circuit 300 receives the pattern generation instruction b, performs an operation, and generates a pattern output c as “0, 1, 2, 3, 4, 5, 6, 0”.

  The pattern generated by the pattern generation circuit 300 in this way is supplied to the IC under test 500. Similarly, the comparator 400 compares the expected pattern generated by the pattern generation circuit 300 with the output of the IC under test 500 to determine whether the IC under test 500 is good or bad.

  FIG. 8 is a block diagram showing an example of a conventional sequence control circuit 100, which includes a flip-flop 1, an instruction memory 2 for storing a sequence control instruction, and a program counter control unit 3.

  The flip-flop 1 outputs the program counter signal a to the outside and inputs it to the instruction memory 2 and the program counter control unit 3. The instruction memory 2 is accessed by the program counter signal a input from the flip-flop 1 and outputs a sequence control instruction f to the program counter control unit 3. The program counter control unit 3 decodes the sequence control instruction f, determines the next program counter signal g, and outputs it to the flip-flop 1. In the next cycle, the flip-flop 1 outputs the next program counter signal g. Thereafter, the same processing is performed.

  The sequence control circuit 100 outputs a continuous program counter signal a by repeating such a series of operations.

  FIG. 9 is a timing chart for explaining the operation when the sequence control circuit of FIG. 8 executes the program of FIG. In the instruction memory 2, an instruction “NOOP” at address 0, “LOOP” at address 1, “NOOP” at address 2 is set by the computer, and an initial value “0” is set in flip-flop 1. .

  When the test of the IC under test 500 is started, the address 0 of the instruction memory 2 is accessed by the value “0” of the program counter signal a, and the “NOOP” instruction is output as the sequence control instruction f. The program counter control unit 3 decodes the sequence control instruction “NOOP” and outputs a value “1” obtained by incrementing the program counter as the next program counter signal g. The flip-flop 1 outputs “1” in the next cycle, and the same processing is performed.

  The sequence control circuit 100 generates the program counter signal a as “0, 1, 1, 1, 1, 1, 1, 2” by repeating such a series of operations.

  FIG. 10 shows another example of a program related to the sequence control instruction. The sequence control instruction “JUMP” is an instruction for executing a line described as “JUMP” and jumping the program counter to a designated line. In this example, “AA” is a row designation, and since the row designated by “AA” is address 10, “10” is output to the next program counter signal g.

  “JPFLG1” is an instruction for executing the line described as “JPFLG1” and determining the next program counter from the value of the PFLG1 register provided in the sequence control circuit. This is an instruction to increment the program counter when the value of the PFLG1 register is “0” and to jump the program counter to the designated line when it is “1”. In this example, when “BB” is a row designation and the value of the PFLG1 register is “0”, the value “13” obtained by incrementing the program counter is output to the next program counter signal g. When “1”, since the row designated by “BB” is address 20, “20” is output to the next program counter signal g.

  In this example, “JPFLG1” has been described, but actually, a plurality of “JPFLGn” instructions for a plurality of PFLGn registers are possible (n: 1, 2,...).

  FIG. 11 is a block diagram illustrating a configuration example of the program counter control unit 3 in the sequence control circuit 100 of FIG. 8. The jump control circuit 11, the loop counter 12, the PFLGn register 13, the adder 14, and the selector 15 are illustrated. It consists of and.

  The jump control circuit 11 controls the jump of the program counter, decodes the sequence control instruction f, and outputs a selection signal q to the selector 15. The jump control circuit 11 is connected to a loop counter 12 for counting the number of loops and a PFLGn register 13.

  The output of the adder 14 that increments the program counter signal a by +1 is input to one input terminal of the selector 15, and the jump address included in the sequence control instruction f is input to the other input terminal. 1 is output as the next program counter signal g, based on the selection signal q input from.

  The selector 15 selectively outputs the output of the adder 14 when the sequence control instruction is “NOOP”, and selectively outputs the jump address included in the sequence control instruction f when the sequence control instruction is “JUMP”.

  When the sequence control instruction is “LOOP”, the jump address included in the sequence control instruction f is selected if the loop counter 12 is in a loop, and the output of the adder 14 is selected if the loop is completed.

  Further, when the sequence control instruction is “JPFLGn”, the jump address included in the sequence control instruction f is selected if the value of the PFLGn register 13 is “1”, and the output of the adder 14 if it is “0”. Select.

  Patent Document 1 discloses a configuration of a conventional sequence control circuit in a semiconductor test apparatus.

JP 2001-282324 A

  By the way, it is necessary to increase the speed of the sequence control circuit 100 in order to perform the test efficiently with the increase in the speed of the memory which is the IC under test 500 of the semiconductor test apparatus.

  However, since the conventional sequence control circuit accesses the instruction memory during one cycle to control the program counter, the maximum operation speed is determined by the sum of the access time of the instruction memory and the operation speed of the program counter control unit. In other words, in order to increase the operation speed, there is a problem that these operation speeds must be improved.

  The present invention has been made in view of such problems, and an object of the present invention is to realize a semiconductor test apparatus using a sequence control circuit capable of increasing the operation speed.

In order to solve such a problem, the invention of claim 1
In a semiconductor test apparatus having a sequence control circuit for controlling a sequence of pattern generation instructions described in a program,
The sequence control circuit includes:
An instruction memory for storing sequence control instructions;
A program counter control unit that decodes a sequence control instruction input from the instruction memory and determines a next program counter signal;
A flip-flop that outputs the program counter signal of the program counter control unit to the outside and inputs to the instruction memory;
An instruction conversion unit that decodes a part of the sequence control instruction immediately before test execution and inputs the conversion output to the instruction memory;
And the sequence control circuit decodes a part of the sequence control instruction including the conditional branch instruction immediately before the test execution.

  As a result, the number of instructions that need to be decoded by the sequence control circuit during test execution is reduced, and the speed can be increased accordingly.

  In the present invention, in order to reduce the instruction to be decoded by the program counter control unit, a conditional branch instruction that selects an operation according to the value of the PFLGn register whose value is determined immediately before the test execution and is not changed during the test execution. Focus on a certain “JPFLGn” instruction. This “JPFLGn” instruction checks the value of the PFLGn register immediately before the test execution. If the PFLGn register is “0”, it can be converted to a “NOOP” instruction. If it is “1”, it is converted to a “JUMP” instruction. It is a possible instruction.

  The present invention is characterized in that the conversion of the “JPFLGn” instruction is performed by the JPFLG instruction conversion unit before the test is executed. By converting the “JPFLGn” instruction into a “NOOP” or “JUMP” instruction, The counter control unit does not need to decode the “JPFLGn” instruction.

  The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a sequence control circuit according to the present invention. In FIG. 1, the sequence control circuit includes an instruction memory 22 that stores a sequence control instruction, a program counter control unit 23, a flip-flop 21, and a JPFLG instruction conversion unit 24.

  The flip-flop 21 outputs the program counter signal a to the outside and inputs it to the instruction memory 22.

  The JPFLG instruction conversion unit 24 is a circuit that converts the “JPFLGn” instruction into a “NOOP” or “JUMP” instruction immediately before the test execution, and its conversion output is input to the instruction memory 22.

  The instruction memory 22 is accessed by the program counter signal a input from the flip-flop 1 and outputs a sequence control instruction f to the program counter control unit 23.

  The program counter control unit 23 decodes the sequence control instruction f, determines the next program counter signal g, and outputs it to the flip-flop 21. At the next cycle, the flip-flop 21 outputs the next program counter signal g. Thereafter, the same processing is performed. Note that the program counter control unit 23 is obtained by deleting the decoding of the “JPFLGn” instruction from the program counter control unit 3 of the conventional sequence control unit 100 shown in FIG.

  FIG. 2 is a block diagram illustrating a specific example of the JPFLG instruction conversion unit 24. The JPFLG instruction conversion unit 24 includes a JPFLG instruction identification unit 31, a JPFLG counter 32, a JPFLG data memory 33, a JPFLG address memory 34, a read counter 35, a PFLGn register 36, and an instruction conversion unit 37.

  The JPFLG instruction identification unit 31 receives data h and write enable signal i to be written to the instruction memory 22, and uses the JPFLG memory write enable signal k as the JPFLG counter 32, the WE terminal of the JPFLG data memory 33, and the WE terminal of the JPFLG address memory 34. Output to.

  The JPFLG counter 32 inputs the count value 1 to the Wadd terminal of the JPFLG data memory 33, the Wadd terminal of the JPFLG address memory 34, and the read counter 35.

  The data h written in the instruction memory 22 is input to the Wdata terminal of the JPFLG data memory 33, the count value q of the read counter 35 is input to the Radd terminal, and the write of the instruction memory 22 is input to the Wdata terminal of the JPFLG address memory 34. The address j is input, and the count value q of the read counter 35 is input to the Radd terminal.

  The instruction conversion unit 37 receives the value m of the PFLGn register 36 and the data n from the Rdata terminal of the JPFLG data memory 33, and outputs the instruction memory conversion write data p.

  The JPFLG address memory 34 outputs the write address o for instruction memory conversion from the Rdata terminal.

The operation of the JPFLG instruction conversion unit 24 configured as described above will be described.
An example in which the sequence control command is transferred from the computer to the instruction memory 22 and the “JPFLGn” command is converted to the “NOOP” or “JUMP” command immediately before the test execution will be described.

  The JPFLG instruction identifying unit 31 identifies whether the sequence control instruction transferred from the computer to the instruction memory 22 is a “JPFLGn” instruction. If it is a “JPFLGn” instruction, the JPFLG memory write enable signal k is asserted, and if it is not a “JPFLGn” instruction, the JPFLG memory write enable signal k is negated.

  The JPFLG counter 32 sets the initial value to 0, and increments the counter by asserting the JPFLG memory write enable signal k.

  The JPFLG data memory 33 writes the data h to be written to the instruction memory 22 by asserting the JPFLG memory write enable signal k using the count value 1 of the JPFLG counter 32 as an address.

  The JPFLG address memory 34 writes the write address j of the instruction memory 22 by asserting the JPFLG memory write enable signal k using the count value 1 of the JPFLG counter 32 as an address.

FIG. 3 is a timing chart showing an operation example when a sequence control command is transferred from the computer to the instruction memory 22.
Since the sequence control instruction transferred from the computer is “NOOP” at period t1, the JPFLG instruction identifying unit 31 negates the JPFLG memory write enable signal k. The JPFLG data memory 33 and the JPFLG address memory 34 are not written, and the JPFLG counter 32 is not incremented.

  Since the sequence control instruction transferred from the computer is “JPFLG1” in the period t2, the JPFLG instruction identifying unit 31 asserts the JPFLG memory write enable signal k. The JPFLG data memory 33 writes the data “JPFLG1” using the count value 1 “0” of the JPFLG counter 32 as an address, and the JPFLG address memory 34 uses the count value 1 “0” of the JPFLG counter 32 as an address. Write “1”. The JPFLG counter 32 is incremented and the count value l becomes “1”.

  In cycles t3 and 4, since the sequence control instruction transferred from the computer is “NOOP”, the JPFLG instruction identifying unit 31 negates the JPFLG memory write enable signal k. The JPFLG data memory 33 and the JPFLG address memory 34 are not written, and the JPFLG counter 32 is not incremented.

  In the period t5, the sequence control instruction transferred from the computer is “JPFLG2”, so the JPFLG instruction identifying unit 31 asserts the JPFLG memory write enable signal k. The JPFLG data memory 33 writes the data “JPFLG2” using the count value 1 “1” of the JPFLG counter 32 as an address, and the JPFLG address memory 34 uses the count value 1 “1” of the JPFLG counter 32 as an address. 4 "is written. The JPFLG counter 32 is incremented and the count value l becomes “2”.

  In the period t6, since the sequence control instruction transferred from the computer is “NOOP”, the JPFLG instruction identifying unit 31 negates the JPFLG memory write enable signal k. The JPFLG data memory 33 and the JPFLG address memory 34 are not written, and the JPFLG counter 32 is not incremented.

  In the cycle t7, the sequence control instruction transferred from the computer is “JPFLG3”, so the JPFLG instruction identifying unit 31 asserts the JPFLG memory write enable signal k. The JPFLG data memory 33 writes the data “JPFLG3” using the count value 1 “2” of the JPFLG counter 32 as an address, and the JPFLG address memory 34 uses the count value 1 “2” of the JPFLG counter 32 as an address. ". The JPFLG counter 32 is incremented and the count value l becomes “3”.

  Thus, when the sequence control instruction is transferred from the computer to the instruction memory 22, the JPFLG instruction conversion unit 24 identifies whether it is a “JPFLGn” instruction, and if it is a “JPFLGn” instruction, the instruction memory 22 Are stored in the JPFLG address memory 34, and the “JPFLGn” instruction is stored in the JPFLG data memory 33.

  Next, an operation for converting the “JPFLGn” instruction into a “NOOP” or “JUMP” instruction immediately before the test execution will be described.

  The read counter 35 receives the conversion start command (not shown) of the JPFLG command from the computer and starts its operation. The read counter 35 counts down using a value obtained by subtracting 1 from the count value 1 of the JPFLG counter 32 as an initial value.

  The JPFLG data memory 33 outputs data n using the count value q of the read counter 35 as an address. This data n is a “JPFLGn” instruction stored.

  The JPFLG address memory 34 outputs data o using the count value q of the read counter 35 as an address. This data o becomes the write address for instruction memory conversion.

  The instruction conversion unit 37 receives data n of the JPFLG data memory 33 that is a “JPFLGn” instruction. The “JPFLGn” instruction is decoded and converted into a “NOOP” instruction or a “JUMP” instruction based on the value m of the corresponding PFLGn register 36. When the PFLGn register 36 is “0”, it is converted into a “NOOP” instruction, and when it is “1”, it is converted into a “JUMP” instruction. The converted output data p becomes write data for instruction memory conversion.

  FIG. 4 is a timing chart showing an operation example when the address of the instruction memory 22 and the “JPFLGn” instruction stored in FIG. 3 are converted into a “NOOP” or “JUMP” instruction immediately before the test execution.

  In the period t1, the read counter 35 outputs a value “2” obtained by subtracting 1 from the count value l “3” of the JPFLG counter 32 as the count value q. The JPFLG data memory 33 outputs “JPFLG3” as data n with the count value q “2” of the read counter 35 as an address. The instruction conversion unit 37 receives the “JPFLG3” instruction of the data n and converts it to a “JUMP” instruction because the value of the PFLG3 register 36 is “1”.

  The JPFLG address memory 34 outputs “6” as data o using the count value q “2” of the read counter 35 as an address. The instruction memory 22 writes the output data p “JUMP” of the instruction conversion unit 37 using the data o “6” of the JPFLG address memory 34 as an address.

  In the period t2, the read counter 35 outputs the down-counted value “1” as the count value q. The JPFLG data memory 33 outputs “JPFLG2” as data n with the count value q “1” of the read counter 35 as an address. The instruction conversion unit 37 receives the “JPFLG2” instruction of the data n and converts it to a “NOOP” instruction because the value of the PFLG2 register 36 is “0”.

  The JPFLG address memory 34 outputs “4” as data o using the count value q “1” of the read counter 35 as an address. The instruction memory 22 writes “NOOP” of the output data p of the instruction conversion unit 37 using the data o “4” of the JPFLG address memory 34 as an address.

  In the period t3, the read counter 35 outputs the down-counted value “0” as the count value q. The JPFLG data memory 33 outputs “JPFLG1” as data n with the count value q “0” of the read counter 35 as an address. The instruction conversion unit 37 receives the “JPFLG1” instruction of the data n and converts it to a “JUMP” instruction because the value of the PFLG1 register 36 is “1”.

  The JPFLG address memory 34 outputs “1” as data o using the count value q “0” of the read counter 35 as an address. The instruction memory 22 writes “JUMP” of the output data p of the instruction conversion unit 37 using the data o “1” of the JPFLG address memory 34 as an address.

  In the above-described embodiment, the “JPFLGn” instruction and the instruction memory address are stored by hardware and converted into a “NOOP” instruction or a “JUMP” instruction according to the value of the PFLGn register. An instruction and an instruction memory address may be stored and converted into a “NOOP” instruction or a “JUMP” instruction depending on the value of the PFLGn register.

  As described above, according to the present invention, the number of instructions to be decoded by the sequence control circuit during test execution is reduced, and the decoding circuit can be reduced, so that the operation speed is improved and the semiconductor test apparatus can be speeded up.

It is a block diagram which shows the structural example of the sequence control circuit based on this invention. It is a block diagram which shows the specific example of the JPFLG instruction | command conversion part 24 of FIG. It is a timing chart which shows the operation example of FIG. It is a timing chart which shows the operation example of FIG. It is a block diagram which shows the structural example of the conventional semiconductor test apparatus. 6 is a program example in the semiconductor test apparatus of FIG. 6 is a timing chart showing an example of the operation of FIG. FIG. 10 is a block diagram showing an example of a conventional sequence control circuit 100. It is a timing chart which shows the operation example of FIG. It is another example of a program regarding a sequence control command. FIG. 9 is a block diagram illustrating a configuration example of a program counter control unit 3 in the sequence control circuit 100 of FIG. 8.

Explanation of symbols

21 Flip-flop 22 Instruction memory 23 Program counter control unit 24 JPFLG instruction conversion unit

Claims (1)

In a semiconductor test apparatus having a sequence control circuit for controlling a sequence of pattern generation instructions described in a program,
The sequence control circuit includes:
An instruction memory for storing sequence control instructions;
A program counter control unit that decodes a sequence control instruction input from the instruction memory and determines a next program counter signal;
A flip-flop that outputs the program counter signal of the program counter control unit to the outside and inputs to the instruction memory;
An instruction conversion unit that decodes a part of the sequence control instruction immediately before test execution and inputs the conversion output to the instruction memory;
And the sequence control circuit decodes a part of the sequence control instruction including the conditional branch instruction immediately before the test execution.

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