JP5155602B2 - Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program - Google Patents

Description

  The present invention relates to a semiconductor failure analysis apparatus, a failure analysis method, and a failure analysis program for analyzing a failure of a semiconductor device.

An emission microscope, an OBIRCH (Optical Beam Induced Resistance Change) apparatus, a time-resolved emission microscope, and the like are used as a semiconductor inspection apparatus that acquires an observation image for analyzing a defect of a semiconductor device. In these inspection apparatuses, it is possible to analyze a defect such as a failure portion of a semiconductor device using a light emission image or an OBIRCH image acquired as a defect observation image (see, for example, Patent Documents 1 to 4).
JP 2003-86689 A JP 2003-303746 A Japanese Patent Laid-Open No. 2007-3306 JP 2007-5497 A

  In recent years, in semiconductor failure analysis, semiconductor devices to be analyzed have been miniaturized and highly integrated, and it has become difficult to analyze a defective portion using the above-described inspection apparatus. Therefore, in order to analyze a defective portion of such a semiconductor device, it is indispensable to improve the reliability and efficiency of the analysis processing for estimating the defective portion of the semiconductor device from the defect observation image. .

  The present invention has been made to solve the above problems, a semiconductor failure analysis apparatus, a failure analysis method capable of reliably and efficiently analyzing a failure of a semiconductor device using a failure observation image, An object is to provide a failure analysis program.

In order to achieve such an object, a semiconductor defect analysis apparatus according to the present invention is a semiconductor defect analysis apparatus that analyzes a defect of a semiconductor device, and (1) performs an inspection for defects as an observation image of a semiconductor device. Inspection information acquisition means for acquiring defect observation images including reaction information resulting from defects, (2) layout information acquisition means for acquiring layout information of semiconductor devices, and (3) defect observation images and layouts. And (4) a defect analysis unit that refers to the defect observation image and sets an analysis region corresponding to the reaction information. And a wiring information analyzing means for performing failure analysis with reference to the analysis region for a plurality of wirings included in the layout of the semiconductor device, (5) wiring The information analysis means extracts a wiring that passes through the analysis region among the plurality of wirings as a defective candidate wiring, and refers to the distance between the other wiring and the candidate wiring in the plurality of wirings, Proximity wiring information is acquired, and the wiring information analysis unit sets a distance threshold for acquiring the proximity wiring information, and the distance between the other wiring and the candidate wiring in the plurality of wirings is equal to or less than the distance threshold. case, as well as it determined that the adjacent wire and another wire for the candidate interconnection for a plurality of layers in the laminated structure of a semiconductor device, characterized that you have been capable of setting the distance threshold for each layer.

The semiconductor failure analysis method according to the present invention is a semiconductor failure analysis method for analyzing a failure of a semiconductor device. (1) As an observation image of a semiconductor device, it is caused by a failure obtained by inspecting a failure. An inspection information acquisition step of acquiring a defect observation image including reaction information to be performed; (2) a layout information acquisition step of acquiring layout information of the semiconductor device; and (3) a semiconductor device by referring to the defect observation image and the layout information. A defect analysis step for analyzing a defect, and (4) the defect analysis step is included in a semiconductor device layout and a region setting step for setting an analysis region corresponding to reaction information with reference to a defect observation image A wiring information analysis step of performing failure analysis with reference to the analysis region for a plurality of wirings to be (5) wiring information In the analysis step, the wiring that passes through the analysis region among the plurality of wirings is extracted as a defective candidate wiring, and the distance between the other wirings in the plurality of wirings and the candidate wiring is referred to, and When proximity wiring information is acquired , the wiring information analysis step sets a distance threshold for acquiring proximity wiring information, and the distance between other wirings and candidate wirings in a plurality of wirings is equal to or less than the distance threshold to, as well as determined that the adjacent wire and another wire for the candidate interconnection for a plurality of layers in the laminated structure of a semiconductor device, characterized that you have been capable of setting the distance threshold for each layer.

A semiconductor failure analysis program according to the present invention is a program for causing a computer to execute a semiconductor failure analysis for analyzing a failure of a semiconductor device, and (1) performing an inspection on the failure as an observation image of the semiconductor device. Inspection information acquisition processing for acquiring a defect observation image including reaction information resulting from defects, (2) layout information acquisition processing for acquiring semiconductor device layout information, and (3) failure observation image and layout information And (4) the defect analysis process refers to a defect observation image, and sets an analysis area corresponding to reaction information. Perform failure analysis with reference to the analysis area for multiple wirings included in the setting process and semiconductor device layout (5) The wiring information analysis process extracts a wiring that passes through the analysis region among a plurality of wirings as a defective candidate wiring, and other wirings and candidate wirings among the plurality of wirings. The adjacent wiring information for the candidate wiring is acquired with reference to the distance between the wiring and the wiring information analysis processing sets a distance threshold for acquiring the adjacent wiring information, and candidates with other wirings in a plurality of wirings When the distance to the wiring is less than or equal to the distance threshold, it is determined that other wirings are adjacent to the candidate wiring, and the distance threshold can be set for each layer of multiple layers in the stacked structure of semiconductor devices It has been characterized by Rukoto.

  In the semiconductor defect analysis apparatus, the defect analysis method, and the defect analysis program described above, information necessary for the defect observation image such as the light emission image and the OBIRCH image obtained by inspecting the semiconductor device to be analyzed, and the layout of the semiconductor device And get. Then, by setting an analysis region corresponding to reaction information (for example, information on a reaction site) in the defect observation image, by extracting a wiring that passes through the analysis region from each wiring (net) constituting the semiconductor device , Semiconductor device failure analysis. According to such a configuration, a candidate wiring for a defect in a semiconductor device can be estimated by a wiring that passes through an analysis region set based on the defect observation image.

  Further, in the above configuration, the information about the proximity wiring with respect to the candidate wiring with reference to the distance between the defective candidate wiring extracted as the wiring passing through the analysis region and other wiring included in the layout of the semiconductor device. Is getting. As described above, according to the configuration in which the adjacent wiring information is extracted from the candidate wiring, it is possible to efficiently acquire information on a defect that occurs between adjacent wirings in the semiconductor device, for example, a short defect between the wirings. it can. Therefore, it is possible to reliably and efficiently perform the failure analysis of the semiconductor device using the failure observation image.

  Here, regarding the content of the specific proximity wiring information acquired in the above configuration, it is preferable to acquire information on the proximity wiring with respect to the candidate wiring and the proximity location between the candidate wiring and the proximity wiring as the proximity wiring information. As described above, it is possible to estimate a candidate portion of a defect such as a short-circuit defect by specifying a neighboring wire with respect to the defective candidate wire and acquiring information on a neighboring portion between these wires.

  As for a specific method of acquiring adjacent wiring information, the failure analysis apparatus sets a distance threshold for acquiring the adjacent wiring information by the wiring information analyzing means, and sets the distance threshold for other wirings and candidate wirings in a plurality of wirings. When the distance between the two is less than or equal to the distance threshold, it is preferable to determine the other wiring as a proximity wiring to the candidate wiring. Similarly, in the failure analysis method, the wiring information analysis step sets a distance threshold for acquiring adjacent wiring information, and the distance between the other wirings in the plurality of wirings and the candidate wiring is equal to or smaller than the distance threshold. In this case, it is preferable to determine the other wiring as a proximity wiring to the candidate wiring. Similarly, the defect analysis program sets a distance threshold for the wiring information analysis processing to acquire the adjacent wiring information, and the distance between the other wirings in the plurality of wirings and the candidate wiring is equal to or smaller than the distance threshold. In this case, it is preferable to determine the other wiring as a proximity wiring to the candidate wiring.

  As described above, by setting the distance threshold for the distance between the wirings and acquiring the adjacent wiring information, it is possible to reliably extract the adjacent wirings with respect to the candidate wiring. As a method for determining the adjacent wiring in this case, specifically, for example, there is a method in which the width of the candidate wiring is increased by a distance threshold value and a wiring having an overlapping portion with respect to the expanded candidate wiring is used as the adjacent wiring. is there. In such a configuration, the distance threshold is preferably configured so that the distance threshold can be set for each layer of a plurality of layers in the stacked structure of the semiconductor devices.

  In addition, the failure analysis apparatus obtains adjacent wiring information for the candidate wiring by referring to the distance between the other wiring and the candidate wiring in the plurality of wirings and the proximity length thereof. Also good. Similarly, in the failure analysis method, the wiring information analysis step refers to the distance between the other wiring and the candidate wiring in the plurality of wirings, and the proximity length thereof, and acquires the adjacent wiring information for the candidate wiring. May be. Similarly, the failure analysis program obtains the adjacent wiring information for the candidate wiring by referring to the distance between the other wiring and the candidate wiring in the plurality of wirings and the proximity length thereof. May be.

  As described above, in addition to the distance between the defective candidate wiring extracted as the wiring passing through the analysis region and the other wiring included in the layout of the semiconductor device, the proximity length between the wirings is referred to. Also according to the method, it is possible to suitably acquire information on the proximity wiring with respect to the candidate wiring.

  In addition, the defect analysis apparatus selects a suspected defective wiring that is a candidate wiring from which adjacent wiring information is to be acquired from among a plurality of candidate wirings when a plurality of candidate wirings are extracted as candidate wirings. Thus, it is preferable to acquire adjacent wiring information for the suspected defective wiring. Similarly, in the failure analysis method, when a plurality of candidate wirings are extracted as candidate wirings in the wiring information analysis step, suspected defective wirings that are candidate wirings for which proximity wiring information is to be acquired among the plurality of candidate wirings. It is preferable to select and acquire adjacent wiring information for the suspected defective wiring. Similarly, when the wiring information analysis process extracts a plurality of candidate wirings as candidate wirings, the failure analysis program determines a suspected defective wiring that is a candidate wiring for which proximity wiring information is to be acquired from among the plurality of candidate wirings. It is preferable to select and acquire adjacent wiring information for the suspected defective wiring.

  As described above, the defect analysis for the plurality of wirings can be suitably performed by selecting the suspected defective wiring as the acquisition target of the adjacent wiring information and performing the failure analysis for the extracted candidate wirings. As a method for selecting the suspected defective wiring in this case, a method of selecting the suspected defective wiring from a plurality of candidate wirings in consideration of the number of times of passage through the analysis region can be used. Two or more candidate wirings may be selected as the suspected defective wirings.

  In addition, when a plurality of candidate wirings are extracted as described above, for a failure analysis of a plurality of wirings performed with reference to the candidate wirings and the adjacent wirings, the failure analysis apparatus includes a wiring information analysis unit that includes a plurality of wirings. When other wirings in (1) are determined as neighboring wirings for suspected defective wirings, considering whether neighboring wirings are other candidate wirings included in multiple candidate wirings, failure analysis for multiple wirings It is preferable to carry out.

  Similarly, in the failure analysis method, when the wiring information analysis step determines that another wiring in the plurality of wirings is a neighboring wiring with respect to the suspected defective wiring, other candidate wirings in which the neighboring wiring is included in the plurality of candidate wirings. In consideration of whether or not, it is preferable to perform failure analysis on a plurality of wirings.

  Similarly, when the wiring information analysis process determines that another wiring in a plurality of wirings is a neighboring wiring with respect to the suspected defective wiring, the failure analysis program determines that the other wiring is included in the plurality of candidate wirings. In consideration of whether or not, it is preferable to perform failure analysis on a plurality of wirings.

  In this way, in the failure analysis of a plurality of wirings, whether the adjacent wiring extracted for the specific candidate wiring is another candidate wiring, that is, whether the adjacent wiring passes through the analysis region. By referring to whether or not, it is possible to reliably extract information such as a wiring that is highly likely to cause a short-circuit failure between wirings in the semiconductor device.

  According to the semiconductor failure analysis device, the failure analysis method, and the failure analysis program of the present invention, the wiring passing through the analysis region set in the failure observation image is extracted as a defective candidate wiring, and the extracted candidate wiring is By referring to the distance to other wirings included in the layout of the semiconductor device and acquiring adjacent wiring information for the candidate wiring, it is possible to efficiently acquire information about defects that occur between the wirings, and the semiconductor Device failure analysis can be performed reliably and efficiently.

  Hereinafter, preferred embodiments of a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. Further, the dimensional ratios in the drawings do not necessarily match those described.

  FIG. 1 is a block diagram schematically showing a configuration of an embodiment of a failure analysis system including a semiconductor failure analysis apparatus according to the present invention. This defect analysis system 1 is for analyzing a semiconductor device as an analysis target and using the observed image, and includes a semiconductor defect analysis device 10, an inspection information supply device 20, a layout information supply device 30, and the like. The display device 40 and the input device 45 are provided. Hereinafter, configurations of the semiconductor failure analysis apparatus 10 and the failure analysis system 1 will be described together with a semiconductor failure analysis method.

  The semiconductor failure analysis apparatus 10 is an analysis apparatus for inputting data necessary for failure analysis of a semiconductor device and executing the failure analysis processing. The defect analysis apparatus 10 according to the present embodiment includes an inspection information acquisition unit 11, a layout information acquisition unit 12, a defect analysis unit 13, an analysis screen display control unit 14, and a layout image display control unit 15. . Further, the defect analysis apparatus 10 is connected to a display apparatus 40 for displaying information relating to defect analysis and an input apparatus 45 used for inputting instructions and information necessary for defect analysis.

  Data used for defect analysis executed in the defect analysis apparatus 10 is acquired by the inspection information acquisition unit 11 and the layout information acquisition unit 12. The inspection information acquisition unit 11 includes, as an observation image of a semiconductor device, a pattern image P1 that is a normal observation image, and a defect observation image P2 that includes reaction information that is obtained by performing a defect inspection. And get. The layout information acquisition unit 12 acquires layout information indicating the configuration of a plurality of wirings in the semiconductor device.

  In FIG. 1, an inspection information supply device 20 is connected to the inspection information acquisition unit 11, and the pattern image P <b> 1 and the defect observation image P <b> 2 are supplied from the supply device 20 to the acquisition unit 11. As the inspection information supply device 20, for example, an emission microscope device can be used. In this case, the defect observation image P2 is a light emission image. Further, an OBIRCH device can be used as the inspection information supply device 20. In this case, the defect observation image P2 is an OBIRCH image. Alternatively, other types of semiconductor inspection devices may be used as the supply device 20.

  When the pattern image P1 and the defect observation image P2 are acquired in advance by the semiconductor inspection apparatus, the inspection information supply apparatus 20 is a data storage device that stores those image data. The data storage device in this case may be provided inside the failure analysis device 10 or may be an external device. Such a configuration is useful when an observation image is first collected by the semiconductor inspection apparatus, and the software of the defect analysis apparatus 10 is executed on another computer to share the defect analysis work. is there.

  For the pattern image P1 and the defect observation image P2 acquired by a semiconductor inspection apparatus such as an emission microscope apparatus or an OBIRCH apparatus, the images P1 and P2 are acquired in a state where the semiconductor device is placed on the stage. For this reason, both are acquired as images that are aligned with each other. Further, the coordinate system on the images P1 and P2 is set corresponding to, for example, a stage coordinate system in the semiconductor inspection apparatus.

  On the other hand, a layout information supply device 30 is connected to the layout information acquisition unit 12 via a network, and layout information such as a layout image P3 is supplied from the supply device 30 to the acquisition unit 12. As this layout information supply device 30, for example, a supply device that holds necessary design information such as arrangement of elements and nets (wirings) constituting a semiconductor device, or a layout viewer that generates a layout image P3 from the design information. A workstation running CAD software can be used.

  Here, for example, information regarding layout information other than the layout image P3, such as individual information of a plurality of nets included in the semiconductor device, is communicated with the layout information supply device 30 as necessary in the defect analysis device 10. It is preferable to use the structure to acquire. Alternatively, the information may be read from the layout information acquisition unit 12 together with the layout image P3.

  Further, in the layout information supply apparatus 30, information on the wiring configuration of the semiconductor device included in the layout information is prepared as data in the GDSII format, for example. The GDSII data is wiring information in which a configuration of a plurality of wirings of a semiconductor device is described by a pattern data group of wiring patterns in each of a plurality of layers in the stacked structure of the semiconductor device, and is widely used in the semiconductor field. In the GDSII data, specifically, the above-described wiring pattern is expressed by a rectangular pattern specified by a combination of start point, end point, and width data.

  Alternatively, the layout information supply device 30 may be configured such that the wiring configuration information included in the layout information is prepared as data in another format such as the LEF / DEF format.

  In the present embodiment, the failure analysis apparatus 10 is provided with a layout image display control unit 15. The layout image display control unit 15 is composed of screen transfer software, for example, an X terminal, and has a function of displaying a layout image P3 drawn by the layout information supply device 30 on a predetermined display window of the display device 40. . However, such a layout image display control unit 15 may be omitted if unnecessary.

  Image information acquired by the inspection information acquisition unit 11 and the layout information acquisition unit 12 and layout information about a plurality of wirings are input to the defect analysis unit 13. The defect analysis unit 13 is an analysis unit that analyzes the defect of the semiconductor device with reference to the defect observation image P2 and the layout information. The analysis screen display control unit 14 is information display control means for causing the display device 40 to display information about the analysis result of the semiconductor device failure by the failure analysis unit 13. Further, the analysis screen display control unit 14 displays information on the failure analysis of the semiconductor device on a predetermined analysis screen other than the analysis result as necessary.

  FIG. 2 is a block diagram showing a specific configuration of the failure analysis unit 13 in the semiconductor failure analysis apparatus 10 shown in FIG. The defect analysis unit 13 according to the present embodiment includes an area setting unit 131 and a wiring information analysis unit 132. FIG. 3 is a diagram schematically illustrating a failure analysis method executed by the region setting unit 131 and the wiring information analysis unit 132.

  The region setting unit 131 is a setting unit that sets an analysis region corresponding to reaction information in the image P2 with reference to the defect observation image P2 for the semiconductor device to be analyzed. Here, a light emission image acquired by the emission microscope apparatus is considered as an example of the defect observation image P2. For example, in the example shown in FIG. 3A, there are six light emitting areas (reaction areas) A1 to A6 in the light emission image as the reaction information referred to in the failure analysis. On the other hand, the area setting unit 131 sets six analysis areas B1 to B6 corresponding to the light emitting areas as shown in FIG.

  In the present embodiment, the region setting unit 131 includes an analysis region setting unit 136 and a mask region setting unit 137. The analysis region setting unit 136 sets the analysis region by a method such as applying a predetermined luminance threshold to the defect observation image P2. The setting of the analysis area in the setting unit 136 is performed automatically or manually by an operator. Further, the shape of the analysis region to be set is not particularly limited, but it is preferable to set it to a rectangular region (reaction box) as shown in FIG.

  In addition, the mask area setting unit 137 sets a mask area used as a mask when performing defect analysis using the defect observation image P2. The analysis region setting unit 136 extracts a reaction region and sets an analysis region with reference to the defect observation image masked using the mask region set by the mask region setting unit 137. Note that such mask area setting and mask processing may not be performed if unnecessary.

  The wiring information analysis unit 132 is an analysis unit that analyzes a plurality of wirings (a plurality of nets) included in the layout of the semiconductor device with reference to the analysis region set by the region setting unit 131. Specifically, the analysis unit 132 analyzes a plurality of wirings, and extracts wirings that pass through the analysis region as defective candidate wirings (candidate nets). When a plurality of analysis regions are set by the region setting unit 131, the analysis unit 132 extracts candidate wirings that pass through at least one of the plurality of analysis regions for the plurality of wirings. The number of times the candidate wiring passes through the analysis area (the number of analysis areas through which the wiring passes) is extracted.

  In the above example, as shown in FIG. 3C, four wirings C1 to C4 as candidate wirings that pass through the analysis region with respect to the six analysis regions B1 to B6 set by the analysis region setting unit 136. Has been extracted. Among these candidate wirings C1 to C4, the wiring C1 has the largest number of times of passage through the analysis region, the wiring C2 has the number of times of passage twice, and the wirings C3 and C4 have the number of times of passage once. Yes.

  In the analysis of such wiring information, the analysis may be performed by communicating with the layout information supply device 30 via the layout information acquisition unit 12 as necessary. As such a configuration, for example, there is a configuration in which the analysis unit 132 instructs the layout information supply device 30 to extract candidate wirings and acquire the number of passes through the analysis region, and receive the result as layout information.

  In the present embodiment, the wiring information analysis unit 132 extracts defective candidate wirings from a plurality of wirings as described above, and further extracts other candidate wirings and candidate wirings from among the plurality of wirings. The proximity wiring information for the candidate wiring is acquired with reference to the distance between the two. Such adjacent wiring information is useful information for analyzing a defect such as a short defect occurring between adjacent wirings in a semiconductor device.

  Specifically, the analysis unit 132 sets a distance threshold for acquiring adjacent wiring information with respect to the distance between the wirings. Then, when the distance between the other wiring included in the plurality of wirings and the candidate wiring is equal to or less than the distance threshold value, the wiring is determined as the proximity wiring to the candidate wiring. Further, as the proximity wiring information extracted by the analysis unit 132, specifically, for example, it is preferable to acquire information on the proximity wiring with respect to the candidate wiring and the proximity location between the candidate wiring and the proximity wiring.

  In addition, when the wiring information used for failure analysis of a plurality of wirings is wiring data in the GDSII format or the like in which the wiring configuration is described by the pattern data group of the wiring pattern, the analysis unit 132 performs extraction of defective candidate wirings. The candidate wiring is extracted by performing equipotential tracking of the wiring pattern using the pattern data group. That is, in the wiring information described above, the wiring structure in the semiconductor device is described as an aggregate of a plurality of wiring patterns. Therefore, by performing equipotential tracking over a plurality of layers on such a wiring pattern, it is possible to extract a wiring that is an analysis target.

  In addition, the wiring information analysis unit 132 performs a process of selecting a suspected defective wiring that is likely to be actually defective from a plurality of candidate wirings extracted as described above, as necessary. May be. Such selection of the suspected defective wiring is automatically performed by a method such as selecting a candidate wiring having the largest number of passes through the analysis region or manually by the operator. In addition, when a suspected defective wiring is selected from a plurality of candidate wirings as described above, the analysis unit 132 targets the selected suspected defective wiring, and between the other wirings of the plurality of wirings and the suspected defective wiring. The adjacent wiring information for the suspected defective wiring is acquired with reference to the distance.

  In the present embodiment, an analysis target selection unit 135 is further provided for the wiring information analysis unit 132. The analysis target selection unit 135 is a selection unit that selects a layer to be subjected to failure analysis in the wiring information analysis unit 132 as necessary for the stacked structure of the semiconductor device to be subjected to failure analysis. The selection of a layer by the analysis target selection unit 135 can be performed with reference to a defect observation image acquisition condition or the like.

  For example, when an OBIRCH image is used as the defect observation image, the range in which the laser beam for measurement can reach is limited in the stacked structure of the semiconductor device. Specifically, when laser light is incident from the back side of the semiconductor device, for example, the laser light reaches only about four layers from the bottom layer. Therefore, when the defect observation image is an OBIRCH image, it is preferable that the analysis target selection unit 135 restricts the layer in the range where the laser beam can reach to be the analysis target.

  Information such as an image necessary for defect analysis or information obtained as an analysis result is displayed on the display device 40 as an analysis screen by the analysis screen display control unit 14 as necessary. For example, the display control unit 14 includes information indicating an analysis result by the failure analysis unit 13, specifically, information on an analysis region set by the setting unit 136, or candidate wiring and candidate wiring extracted by the analysis unit 132 And the like are displayed on the display device 40.

  Such an analysis result may be displayed, for example, as an image including an analysis area and wiring as shown in FIG. 3C, or may be displayed according to the name of the candidate wiring and the number of passes. May be. Specifically, it is preferable that the analysis screen display control unit 14 causes the display device 40 to display a wiring list in which the wiring extracted by the wiring information analysis unit 132 is displayed as a result of the analysis.

  When a plurality of analysis areas are set, candidate wirings extracted by the wiring information analysis unit 132 (for example, names of wirings set arbitrarily) and the number of times the wiring passes through the analysis area are analyzed as analysis results. It is preferable to display on the display device 40 a wiring list in which a list (for example, a count number indicating the number of passages) is displayed. In addition, regarding the display of the number of times of passage through the wiring analysis region, the number of times of passage may be displayed in a graph to further improve the visibility.

  When the analysis result is displayed as an image including the analysis region and the candidate wiring, the candidate wiring (candidate net) may be highlighted on the layout image as shown in FIG. In addition, when the extracted candidate wiring is selected by a mouse operation or the like, specifically, various display methods such as changing the color of the analysis region through which the wiring passes may be used.

  In the defect analysis unit 13 of the present embodiment, a position adjustment unit 133 is further provided. The position adjustment unit 133 refers to the pattern image P1 and the layout image P3, and positions the observation image from the supply device 20 including the pattern image P1 and the defect observation image P2 and the layout image P3 from the supply device 30. Align. For this alignment, for example, a method can be used in which appropriate three points are designated in the pattern image P1, and corresponding three points are designated in the layout image P3, and the alignment is performed from these coordinates.

  The defect analysis unit 13 is provided with an additional analysis information acquisition unit 134. The additional analysis information acquisition unit 134 acquires, from an external device or the like, additional analysis information about a semiconductor device failure obtained by an analysis method different from the analysis method described above by the region setting unit 131 and the wiring information analysis unit 132. To do. The acquired additional analysis information is referred to together with the analysis result obtained by the wiring information analysis unit 132.

  The effects of the semiconductor failure analysis apparatus and the semiconductor failure analysis method according to the above embodiment will be described.

  In the semiconductor defect analysis apparatus 10 and the defect analysis method shown in FIG. 1, a defect observation image P2 obtained by inspecting a semiconductor device to be analyzed via the inspection information acquisition unit 11 and the layout information acquisition unit 12, Information necessary for the layout of the semiconductor device is acquired. Then, in the region setting unit 131, an analysis region is set corresponding to reaction information (for example, information on a reaction location, specifically information on a light emission location in a light emission image) caused by a failure in the failure observation image P2. In the wiring information analysis unit 132, the failure analysis of the semiconductor device is performed by extracting the wiring that passes through the analysis region among the wirings constituting the semiconductor device.

  According to such a configuration, it is possible to estimate a candidate wiring that is highly likely to be defective from among an enormous number of wirings in the semiconductor device by wiring that passes through the analysis region. For example, the reaction information caused by the defect in the defect observation image P2 is not only when the reaction part itself is a defective part, but also other defective parts such as a wiring open defect or a short defect between adjacent wirings. The reaction site resulting from is included. According to the above configuration, it is possible to appropriately narrow down and estimate such a defective portion using the analysis region.

  Further, in the above configuration, the wiring information analysis unit 132 refers to the distance between the defective candidate wiring extracted as the wiring passing through the analysis region and the other wiring included in the layout of the semiconductor device. Information about proximity wiring to wiring is acquired. As described above, according to the configuration in which the adjacent wiring information is extracted from the candidate wiring, it is possible to efficiently acquire information on a defect that occurs between adjacent wirings in the semiconductor device, for example, a short defect between the wirings. it can. Therefore, it is possible to reliably and efficiently perform the failure analysis of the semiconductor device using the failure observation image.

  Further, according to the defect analysis system 1 constituted by the semiconductor defect analysis apparatus 10, the inspection information supply apparatus 20, the layout information supply apparatus 30, and the display apparatus 40, the semiconductor device using the defect observation image P2 is used. A semiconductor failure analysis system capable of reliably and efficiently performing the failure analysis is realized.

  Here, with regard to the details of the specific proximity wiring information acquired in the above configuration, the analysis unit 132 acquires, as the proximity wiring information, information on the proximity wiring with respect to the candidate wiring and the proximity location between the candidate wiring and the proximity wiring. It is preferable to do. As described above, not only the information on the proximity wiring but also the information on the proximity location indicating the position on the layout where the candidate wiring and the proximity wiring are close to each other is obtained as the proximity wiring information. Can be suitably estimated. The method for acquiring the adjacent wiring information will be specifically described later.

  In addition, when a plurality of candidate wirings are extracted as candidate wirings, the wiring information analysis unit 132 selects a suspected defective wiring that is a candidate wiring from which the adjacent wiring information is to be acquired from among the plurality of candidate wirings. It is preferable to obtain the proximity wiring information for the suspected defective wiring with reference to the distance between the other wiring in the wiring and the suspected defective wiring.

  As described above, the defect analysis for the plurality of wirings can be suitably performed by selecting the suspected defective wiring as the acquisition target of the adjacent wiring information and performing the failure analysis for the extracted candidate wirings. Further, as a method for selecting the suspected defective wiring in this case, it is preferable to use a method of selecting the suspected defective wiring from a plurality of candidate wirings in consideration of the number of passes through the analysis region. As an example of such a method, there is a method of selecting a candidate wiring having the largest number of passes through the analysis region as a suspected defective wiring. Moreover, it is good also as a structure which can select 2 or more candidate wiring as suspected defective wiring.

  In addition, when a plurality of candidate wirings are extracted as described above, for the failure analysis of the plurality of wirings performed with reference to the candidate wirings and the adjacent wirings, the analysis unit 132 determines that other wirings among the plurality of wirings When it is determined that the adjacent wiring is a neighboring wiring for the suspected defective wiring (candidate wiring for which the neighboring wiring information is to be acquired), a plurality of wirings are considered in consideration of whether the neighboring wiring is another candidate wiring included in the plurality of candidate wirings. It is preferable to perform defect analysis on the wiring.

  In such a configuration, it is defective by referring to whether the adjacent wiring extracted for a specific candidate wiring is another candidate wiring, that is, whether the adjacent wiring is a wiring that passes through the analysis region. Analysis is performed. In this case, for example, when both the suspected defective wiring and the adjacent wiring are extracted as candidate wirings that pass through the analysis region, it is determined that there is a high possibility that a short defect has occurred between the wirings. It is possible to reliably detect the occurrence of defects between the wirings.

  Further, in the above configuration, when wiring information based on a pattern data group that is an assembly of wiring patterns is used as wiring information in a semiconductor device, the equipotential tracking of the wiring pattern in the pattern data group is performed when extracting defective candidate wirings. As a result, candidate wirings are extracted. According to such a configuration, for example, defective candidate wirings can be efficiently extracted using wiring information obtained from GDSII data that is easily available compared to LEF / DEF data and the like. However, in failure analysis such as extraction of candidate wirings, for example, data in other formats such as LEF / DEF data may be used. Further, such wiring extraction by equipotential tracking is also performed as necessary in the extraction of adjacent wiring.

  Regarding a specific candidate wiring extraction method by equipotential tracking, for a plurality of layers of a semiconductor device, an extraction layer used for extracting candidate wiring passing through an analysis region, a tracking layer used for equipotential tracking of a wiring pattern, It is preferable to execute extraction of candidate wirings. As described above, in the plurality of layers of the semiconductor device, the extraction layer and the tracking layer are set according to the specific device structure, the type of the defect observation image P2, and the like, so that the candidate by the equipotential tracking of the wiring pattern is possible. Wiring extraction can be suitably executed.

  In the above-described method for extracting candidate wirings, a termination layer at which the equipotential tracking of the wiring pattern ends may be set for a plurality of layers of the semiconductor device. This makes it possible to perform various failure analysis, for example, by designating the layer to which the gate of the transistor is connected as the termination layer and separating and detecting the light emitting transistor. In this case, as a tracking mode in equipotential tracking, a configuration in which only a wiring that terminates in the termination layer is extracted and a tracking mode that does not refer to the termination layer may be used.

  Furthermore, the wiring information analysis unit 132 may be configured to be able to set the maximum number of extracted patterns for limiting the number of wiring patterns (graphics) to be extracted for tracing the equipotential of the wiring patterns. Thereby, it is possible to suitably execute extraction of candidate wirings by equipotential tracking of wiring patterns using wiring information obtained from GDSII data or the like.

  Regarding the setting of the analysis region in the region setting unit 131 of the defect analysis unit 13, for example, a reaction region is extracted by applying a luminance threshold to the luminance distribution in the defect observation image, and the analysis region is determined based on this reaction region. A setting method can be used. Thereby, the analysis area used for defect analysis can be set suitably. Further, in this case, the reaction region used for setting the analysis region may be selected by comparing the area of the reaction region with a predetermined area threshold. As a result, it is possible to set the analysis region after excluding unnecessary regions due to noise, dust, and the like from the extracted reaction regions.

  Regarding the setting of the analysis region in the analysis region setting unit 136, it is preferable to set the analysis region in a layout coordinate system corresponding to the layout of the semiconductor device. Thus, by setting the analysis region extracted from the defect observation image P2 in the layout coordinate system on the layout information side instead of the coordinate system on the image on the inspection information side, a plurality of areas included in the layout of the semiconductor device are included. It is possible to efficiently execute the defect analysis for the wiring with reference to the analysis region set in the layout coordinate system.

  In addition, by expressing the analysis area in the layout coordinate system in this way, the range of use of the analysis area in defect analysis can be expanded. Thereby, the freedom degree of the specific analysis method in the failure analysis of the semiconductor device using an analysis area | region is improved. Alternatively, the analysis area may be set in a coordinate system on the image. For example, as described above, the coordinate system on the image in the defect observation image P2 or the like is set corresponding to the stage coordinate system in the semiconductor inspection apparatus.

  Further, when the layout coordinate system is applied in setting the analysis region as described above, the observation images of the semiconductor devices such as the pattern image P1 and the defect observation image P2 may be converted into the layout coordinate system and stored. . In addition, regarding the mutual relationship among the pattern image P1, the defect observation image P2, and the layout image P3, it is preferable to perform alignment between the observation images P1 and P2 and the layout image P3.

  4 is a diagram schematically showing the correspondence between the observation image and the layout image of the semiconductor device. FIG. 4A shows the correspondence between the pattern image P1, the defect observation image P2, and the layout image P3. (B) shows a superimposed image P6 in which these images are superimposed in the order of images P1, P3, and P2. Thus, the pattern image P1 and the layout image P3 have a certain correspondence. Therefore, the position adjustment unit 133 can perform image alignment by referring to the correspondence between the pattern image P1 and the layout image P3. Thereby, the precision of the defect analysis about the wiring of a semiconductor device can be improved.

  The processing corresponding to the failure analysis method executed in the semiconductor failure analysis apparatus 10 shown in FIG. 1 can be realized by a semiconductor failure analysis program for causing a computer to execute semiconductor failure analysis. For example, the failure analysis apparatus 10 includes a CPU that operates each software program necessary for semiconductor failure analysis processing, a ROM that stores the software program, and a RAM that temporarily stores data during program execution. Can be configured. In such a configuration, the above-described failure analysis apparatus 10 can be realized by executing a predetermined failure analysis program by the CPU.

  Further, the above-described program for causing the CPU to execute each process for semiconductor defect analysis can be recorded on a computer-readable recording medium and distributed. In such a recording medium, for example, a magnetic medium such as a hard disk and a flexible disk, an optical medium such as a CD-ROM and a DVD-ROM, a magneto-optical medium such as a floppy disk, or a program instruction is executed or stored. For example, hardware devices such as RAM, ROM, and semiconductor non-volatile memory are included.

  FIG. 5 is a flowchart showing an example of a semiconductor failure analysis method executed in the semiconductor failure analysis apparatus 10 shown in FIG. In this embodiment, first, an observation image including a defect observation image P2 necessary for defect analysis and layout information including wiring information of a plurality of wirings are acquired via the inspection information acquisition unit 11 and the layout information acquisition unit 12. (Step S101, inspection information acquisition step, layout information acquisition step). Then, after the position adjustment unit 133 performs alignment between the observation image including the pattern image P1 and the defect observation image P2 and the layout image P3 (S102, position adjustment step), the image P2 and the layout information are obtained. The failure analysis of the semiconductor device that is performed with reference is started (failure analysis step).

  First, the region setting unit 131 refers to the defect observation image P2, and sets an analysis region corresponding to the reaction information in the image P2 (S103, region setting step). Subsequently, the wiring information analysis unit 132 performs defect analysis on the plurality of wirings included in the layout of the semiconductor device with reference to the analysis region (wiring information analysis step). Specifically, a wiring that passes through the analysis region among the plurality of wirings is extracted as a defective candidate wiring (S104). In the extraction of candidate wiring, when GDSII data or the like is used as wiring information, wiring extraction by equipotential tracking is performed.

  Information on the extracted candidate wiring is displayed on the analysis screen of the display device 40 by the display control unit 14 (S105). At this time, if necessary, additional analysis information such as a failure diagnosis result is acquired by the additional analysis information acquisition unit 134 and is also referred to (additional analysis information acquisition step). In addition, when a plurality of candidate wirings are extracted as candidate wirings, one of the plurality of candidate wirings, or two or more suspected defects, if necessary, as wirings for which proximity wiring information is to be acquired A wiring is selected (S106). Note that when only one candidate wiring is extracted, the wiring becomes a suspected defective wiring as it is.

  Subsequently, the wiring information analysis unit 132 refers to the distance between the suspicious defective wiring that is the candidate wiring for which the proximity wiring information is acquired and the other wiring among the plurality of wirings included in the layout, and the suspicious defective Proximity wiring information for the wiring is acquired (S107). The acquired proximity wiring information is displayed on the analysis screen of the display device 40 by the display control unit 14 (S108). Further, referring to the adjacent wiring information, further necessary defect analysis is performed for the semiconductor device (S109). In this failure analysis, other information, for example, information on whether the extracted adjacent wiring is another candidate wiring, additional analysis information, or the like is referred to as necessary. Further, as an example of specific contents of the failure analysis here, there is an analysis as to whether or not a short failure has occurred between the suspected defective wiring and the adjacent wiring.

  Next, an example of a semiconductor inspection apparatus used for acquiring the defect observation image P2 will be described. FIG. 6 is a configuration diagram showing an example of a semiconductor inspection apparatus applicable as the inspection information supply apparatus 20 shown in FIG. 1 (see, for example, Patent Documents 3 and 4).

  A semiconductor inspection apparatus 20 </ b> A according to this configuration example includes an observation unit 21 and a control unit 22. The semiconductor device S to be inspected (analysis target by the defect analysis apparatus 10) is placed on a stage 218 provided in the observation unit 21. Furthermore, in this configuration example, a test fixture 219 for applying an electrical signal or the like necessary for failure analysis to the semiconductor device S is installed. For example, the semiconductor device S is disposed so that the back surface thereof faces the objective lens 220.

  The observation unit 21 includes a high sensitivity camera 210 installed in a dark box, a laser scanning optical system (LSM) unit 212, optical systems 222 and 224, and an XYZ stage 215. Among these, the camera 210 and the LSM unit 212 are image acquisition means for acquiring an observation image (pattern image P1, defect observation image P2) of the semiconductor device S.

  The optical system 222, 224 and the objective lens 220 provided on the semiconductor device S side of the optical system 222, 224 are light guide optics for guiding an image (light image) from the semiconductor device S to an image acquisition unit. The system is configured. The test fixture 219 is an inspection unit that performs an inspection for analyzing a failure of the semiconductor device S. The LSM unit 212 also has a function as an inspection unit in addition to the above function as an image acquisition unit.

  The optical system 222 is a camera optical system that guides light from the semiconductor device S incident through the objective lens 220 to the camera 210. The optical system 222 has an imaging lens 222 a for forming an image enlarged by the objective lens 220 at a predetermined magnification on a light receiving surface inside the camera 210. A beam splitter 224a of the optical system 224 is interposed between the objective lens 220 and the optical system 222. As the high sensitivity camera 210, for example, a cooled CCD camera or the like is used.

  In such a configuration, light from the semiconductor device S is guided to the camera 210 via an optical system including the objective lens 220 and the camera optical system 222, and the camera 210 observes the pattern image P1 and the like of the device S. An image is acquired. It is also possible to acquire a light emission image that is the defect observation image P2 of the device S. In this case, light generated from the device S in a state where a voltage is applied by the test fixture 219 is guided to the camera 210 via the optical system, and a light emission image is acquired by the camera 210.

  The LSM unit 212 includes a laser light introducing optical fiber 212a for irradiating infrared laser light, a collimator lens 212b that converts the laser light into parallel light, a beam splitter 212e that reflects the laser light converted into parallel light, An XY scanner 212f that scans laser light in the XY direction and emits the laser light toward the semiconductor device S is provided. In addition, the LSM unit 212 includes a condenser lens 212d that collects light incident from the semiconductor device S side through the XY scanner 212f and transmitted through the beam splitter 212e, and detection light for detecting the collected light. Fiber 212c.

  The optical system 224 is an optical system for an LSM unit that guides light between the semiconductor device S and the objective lens 220 and the LSM unit 212. The optical system 224 includes a beam splitter 224a that reflects part of light incident from the semiconductor device S via the objective lens 220, an optical path conversion mirror 224b, and a condensing lens 224c. .

  In such a configuration, the infrared laser light emitted from the laser light source via the optical fiber 212a passes through the lens 212b, the beam splitter 212e, the XY scanner 212f, the optical system 224, and the objective lens 220, and the semiconductor device S. Irradiated to. The reflected scattered light from the device S with respect to this incident light reflects the circuit pattern in the device S. The reflected light from the semiconductor device S enters the optical fiber 212c through an optical path opposite to the incident light, and is detected by a photodetector connected to the optical fiber 212c.

  The intensity of light detected by the photodetector via the detection optical fiber 212c is an intensity reflecting the circuit pattern provided in the semiconductor device S as described above. Accordingly, the infrared laser beam is scanned on the device S by the XY scanner 212f, so that the pattern image P1 of the device S can be clearly obtained.

  The control unit 22 includes a camera control unit 251a, an LSM control unit 251b, an OBIRCH control unit 251c, and a stage control unit 252. Among these, the camera control unit 251a, the LSM control unit 251b, and the OBIRCH control unit 251c constitute an observation control unit that controls acquisition of an observation image of the semiconductor device S, setting of observation conditions, and the like executed by the observation unit 21. doing.

  Specifically, the camera control unit 251a and the LSM control unit 251b control the acquisition of the observation image of the device S by controlling the operations of the camera 210 and the LSM unit 212, respectively. The OBIRCH control unit 251c is for acquiring an OBIRCH image as a defective observation image, and extracts a current change or the like in the device S that occurs when scanning with laser light. In addition, the stage control unit 252 controls the operation of the XYZ stage 215 in the observation unit 21, thereby setting the observation location of the semiconductor device S to be an inspection location in the inspection apparatus 20A, or its alignment, focusing, etc. To control.

  In addition, an inspection information processing unit 23 is provided for the observation unit 21 and the control unit 22. The inspection information processing unit 23 collects observation image data of the semiconductor device S acquired by the observation unit 21, supplies inspection information including the pattern image P1 and the defect observation image P2 to the defect analysis apparatus 10 (see FIG. 1), and the like. Perform the process. In addition, if necessary, the display device 24 may be connected to the inspection information processing unit 23.

  The semiconductor failure analysis apparatus, failure analysis method, and failure analysis program according to the present invention will be described more specifically.

  First, a method for extracting adjacent wirings from candidate wirings will be described. In the failure analysis apparatus 10 shown in FIGS. 1 and 2, the analysis unit 132 acquires adjacent wiring information for a candidate wiring with reference to the distance between the defective candidate wiring and another wiring. For a specific method for acquiring such adjacent wiring information, as described above, when the distance threshold is set in the analysis unit 132 and the distance between the other wiring and the candidate wiring is equal to or smaller than the distance threshold, A method of determining the wiring as a proximity wiring with respect to the candidate wiring can be used. As described above, according to the configuration using the distance threshold, it is possible to reliably extract the adjacent wiring with respect to the candidate wiring.

  In such a configuration, it is preferable that a distance threshold can be set for each layer of a plurality of layers in the stacked structure of semiconductor devices. Here, in a laminated structure of semiconductor devices, design conditions such as wiring are usually different for each layer. On the other hand, according to the configuration in which the distance threshold is set for each layer as described above, it is possible to suitably set the method for acquiring the proximity wiring information according to the configuration of each layer and the wiring design conditions.

  FIG. 7 is a diagram illustrating an example of a method for determining a proximity wiring with respect to a candidate wiring. Here, as shown in FIG. 7A, it is assumed that the wirings C1 to C4 are considered as a plurality of wirings in the semiconductor device, and the wiring C1 (shown by a solid line) is extracted as a defective candidate wiring. Next, a method for acquiring the adjacent wiring information will be described. Here, it is assumed that the threshold value Dth is set as the distance threshold value for acquiring the adjacent wiring information with respect to the distance D between the wirings.

  In the proximity wiring determination method shown in FIG. 7, as shown in FIG. 7B, the width of the candidate wiring C <b> 1 is increased by the distance threshold value Dth, and the candidate wiring C <b> 10 is expanded. At this time, if the original wiring width of the candidate wiring C1 is W, the width of the expanded candidate wiring C10 is W + 2 × Dth. Then, among the other wirings C2 to C4, a wiring that overlaps the expansion candidate wiring C10 is determined as a proximity wiring. In the example shown in FIG. 7B, the wirings C2 and C3 having the neighboring locations R2 and R3 that overlap with the enlarged candidate wiring C10 among the wirings C2 to C4 are determined as the neighboring wirings for the wiring C1.

  In addition, for the acquisition of the proximity wiring information, the analysis unit 132 uses a method of acquiring the proximity wiring information by referring to the distance between the other wiring and the candidate wiring in the plurality of wirings and the proximity length thereof. May be. In this way, with respect to the defective candidate wiring extracted as the wiring passing through the analysis region, in addition to the distance to other wiring, the method of referring to the proximity length between these wirings can also be used for the candidate wiring. Information about the adjacent wiring can be preferably acquired.

  FIG. 8 is a diagram illustrating another example of a method for determining a proximity wiring with respect to a candidate wiring. In the proximity wiring determination method illustrated in FIG. 8, proximity locations (proximity regions) R2 to R4 are extracted for the wirings C2 to C4 with respect to the candidate wiring C1. Then, for each of the extracted proximity points R2 to R4, the capacitance between the wirings determined by the ratio L / D of the distance D and the proximity length L is obtained, and the obtained capacitance value is compared with a capacitance threshold value. Determine if it is a close wiring.

  Next, a method for extracting a proximity portion between the candidate wiring and the proximity wiring will be described. Here, the extraction of adjacent portions between wirings will be described by taking as an example a case where wiring information of a semiconductor device is supplied as data in the GDSII format. Even when the wiring information is supplied as data in the LEF / DEF format or the like, it is possible to extract the adjacent portion by the same method.

  FIG. 9 is a diagram illustrating an example of a method for extracting a proximity portion between a candidate wiring and a proximity wiring. In this example, as shown in FIG. 9A, a wiring including a wiring C1 composed of four wiring patterns of patterns C11 to C14 and a wiring C2 composed of three wiring patterns of patterns C21 to C23. Consider the configuration. In this configuration, the wirings C1 and C2 are both configured by a wiring pattern parallel to the X axis or the Y axis.

  In this embodiment, as shown in FIG. 9B, four adjacent locations R1 to R4 are extracted between the wiring C1 and the wiring C2 for such a wiring configuration. Specifically, a proximity point R1 having a distance D1 and a length L1 is extracted between the wiring pattern C11 and the wiring patterns C21 and C22. Further, a proximity point R2 having a distance D2 and a length L2 is extracted between the wiring patterns C12 and C13 and the wiring pattern C22. Further, a proximity portion R3 having a distance D3 and a length L3 is extracted between the wiring pattern C13 and the wiring pattern C23. Further, a proximity portion R4 having a distance D4 and a length L4 is extracted between the wiring pattern C14 and the wiring pattern C23.

  In the embodiment of FIG. 9, the proximity location is extracted between the straight line portions of the adjacent wirings C <b> 1 and C <b> 2, and the proximity location is not extracted for the corner portion of the wiring. In such a configuration, when the combination of the proximity points R1 to R4 in FIG. 9B is regarded as a proximity point as a whole, the length L1 to the parallel running section of the straight line portion is determined as the proximity length. The length obtained by adding L4 is preferably the proximity length.

  In addition, regarding the extraction of the proximity location, for example, not only the straight line portion of the adjacent wiring but also the corner portion may be extracted as the proximity location. In this case, in FIG. 9B, the whole including the adjacent locations R1 to R4 may be extracted as an integrated adjacent location. Further, the proximity locations R3 and R4 that are proximity locations to the wiring pattern C23 may be extracted as an integral proximity location. However, in these adjacent locations R3 and R4, the defect generation conditions differ depending on the distances D3 and D4 between the wirings. Therefore, it is preferable to extract them as separate proximity points R3 and R4 as described above in order to perform a detailed failure analysis between wirings.

  FIG. 10 is a diagram illustrating another example of a method for extracting a proximity portion between a candidate wiring and a proximity wiring. In this example, as shown in FIG. 10A, a wiring including a wiring C1 composed of three wiring patterns of patterns C11 to C13 and a wiring C2 composed of three wiring patterns of patterns C21 to C23. Consider the configuration. In this configuration, the wirings C1 and C2 are each configured to include a wiring pattern that is not parallel to the X axis or the Y axis but forms a predetermined angle.

  In the present embodiment, for such a wiring configuration, as shown in FIG. 10A, three adjacent locations R1 to R3 are extracted between the wiring C1 and the wiring C2. Specifically, an adjacent portion R1 having a distance D1 and a length L1 is extracted between the wiring pattern C11 and the wiring pattern C21. Further, a proximity point R2 having a distance D2 and a length L2 is extracted between the wiring pattern C12 and the wiring pattern C22. Further, a proximity portion R3 having a distance D3 and a length L3 is extracted between the wiring pattern C13 and the wiring pattern C23.

  Further, in this embodiment, the distance D and the length L at each adjacent location are determined by the method shown in FIG. FIG. 10B shows a method for determining the distance D2 and the length L2 of the proximity location R2 among the proximity locations R1 to R3 described above. In this method, with respect to the distance D2 between the wirings in the proximity R2, the shorter distance D21 of the distances D21 and D22 at both ends thereof is set as the distance D2 between the wirings. Further, regarding the proximity length L2 of the wiring at the proximity location R2, the longer length L22 of the length L21 on the wiring C1 side and the length L22 on the wiring C2 side is set as the wiring proximity length L2. .

  Next, a specific example of the semiconductor failure analysis method executed in the semiconductor failure analysis apparatus 10 shown in FIG. 1 will be described together with examples of analysis screens shown in FIGS. In addition, the analysis screen shown below is displayed on the display apparatus 40 in the structure of FIG. 1, for example.

  The analysis screen illustrated in FIG. 11A illustrates an example of a wiring list display screen that displays a list of candidate wirings (candidate nets) extracted from a plurality of wirings. The analysis screen 510 has a wiring list display area 511 located on the left side of the screen and a graph display area 512 located on the right side of the screen and displayed as a histogram of the wiring list. In the example of this screen 510, in the wiring list display area 511, the names (nets) NET1 to NET8 of wirings extracted as defective candidate wirings and the number of passes (counts) of their respective analysis areas are displayed. In the graph display area 512, the number of passes through the analysis area for each of the wirings NET1 to NET8 is displayed as a histogram.

  In the present embodiment, since a plurality of candidate wirings NET1 to NET8 are extracted, the suspected defective wiring is selected as the acquisition target of the proximity wiring information. For example, when the wiring NET1 with the largest count is selected as the suspected defective wiring, the histogram of the selected suspected defective wiring NET1 is highlighted in the graph display area 512 as shown in the analysis screen 520 in FIG. Is done. Such selection of the suspected defective wiring is performed automatically or manually by an operation of an operator clicking a histogram of the wiring NET1 on the screen.

  The analysis screen shown in FIG. 12 shows an example of a proximity location extraction screen used for acquiring proximity wiring information for the selected suspected defective wiring NET1. The analysis screen 530 includes an extraction condition setting area 531, an extraction result display area 532, and an operation display area 533.

  In the extraction condition setting area 531, the suspected defective wiring NET <b> 1 selected on the analysis screen 520 is displayed as a target net for proximity location extraction. Further, in this extraction condition setting area 531, a distance threshold value for acquiring adjacent wiring information can be set for each layer. In the example shown in FIG. 12, distance thresholds of 0.8 μm, 1.0 μm for layer 2 and 1.2 μm for layer 1 are set, respectively. Thereby, the analysis of the proximity wiring with respect to the suspected defective wiring can be executed in detail. In such a configuration, if the distance threshold is set to 0.0 μm for a specific layer, the adjacent wiring extraction process is not performed for that layer.

  In the extraction result display area 532, with respect to the proximity location extracted under the conditions displayed in the setting area 531, the distance between the wirings at the proximity location, the proximity length between the wirings, the layer name from which the proximity location was extracted, and Information including the net name of the proximity wiring is displayed.

  In the example shown in FIG. 12, a proximity location with a distance of 0.6 μm and a length of 2.0 μm is extracted in the layer 1 for the proximity wiring NET4 as the proximity location 1 for the suspicious defective wiring NET1. . Further, as the proximity location 2, a proximity location having a distance of 0.6 μm and a length of 3.0 μm is extracted in the layer 2 for the proximity wiring NET9. Further, as the proximity location 3, a proximity location having a distance of 0.7 μm and a length of 0.7 μm is extracted in the layer 1 for the proximity wiring NET4. In FIG. 12, the proximity location 1 and the proximity location 3 are proximity locations for the same proximity wiring NET4.

  Further, below the extraction condition setting area 531 and the extraction result display area 532, an operation display area 533 for performing a necessary operation related to the proximity location extraction is provided. In the example shown in FIG. 12, in the operation display area 533, the sort operation instruction area 534 for sorting the proximity places extracted by the distance between wires, the proximity length, the layer name, or the net name, the extracted proximity places Is a proximity display display area 535 for highlighting on the wiring display screen (see FIG. 3C), and a proximity for highlighting the proximity net (proximity wiring) on the wiring display screen or wiring list display screen. A net display instruction area 536 and an end button 537 for instructing the end of proximity part extraction are provided.

  In the display of the extraction result in the display area 532, when the extracted adjacent wiring is, for example, a wiring pattern in GDSII data and the corresponding net name is unknown, the net name is not displayed for the wiring. For such wiring, it is possible to obtain information such as a net name by performing equipotential tracking or the like as necessary. Further, the display items in the display area 532 are not limited to the above-described distance between wirings, proximity length, layer name, and net name, and other items may be displayed. As a display example of such an item, there is a configuration that displays a score value representing a defect probability (failure probability) at a nearby location, which is obtained based on one or both of the distance between wires and the proximity length. In this case, the sorting operation instruction area 534 may be configured to be able to sort adjacent locations based on score values.

  In the analysis screen 530 illustrated in FIG. 12, the proximity location 1 by the wiring NET4 is selected automatically or manually by the operator among the proximity locations 1 to 3. At this time, as shown in the analysis screen 540 of FIG. 13A, the selected adjacent wiring NET4 is highlighted in the wiring list display area 511 and the graph display area 512 of the wiring list display screen.

  By referring to such analysis screens 530 and 540, considering whether or not the adjacent wiring extracted for the suspected defective wiring is another candidate wiring included in the plurality of candidate wirings, a plurality of wirings It is possible to perform a failure analysis on. For example, for the proximity location 2 among the proximity locations 1 to 3, the proximity wiring NET9 is not included in the candidate wirings NET1 to NET8. Therefore, when the proximity location 2 is selected on the analysis screen 530, no wiring is highlighted on the analysis screen 540.

  Also, the analysis screen 550 of FIG. 13B shows additional analysis information obtained by another method acquired by the additional analysis information acquisition unit 134 (for example, a result of failure diagnosis for narrowing down a failure location based on a semiconductor test result. 3 shows a display example of a wiring list display screen when performing failure analysis in consideration of (information). Here, in the graph display area 512, the histograms of the wirings NET1, NET3, and NET4 that are determined to be defective by the additional analysis information are displayed in different display colors (shown with hatching in the figure). The wiring list is sorted so that these wirings are higher.

  Further, on such an analysis screen 550, by performing an operation such as clicking a highlight button, the matching wiring between the result of the failure analysis and the additional analysis information is displayed on the image as shown in FIG. It is good also as a structure which carries out a highlight display. In the above configuration, the wiring information determined to be defective by the additional analysis information is displayed at the same time, but various other methods can be used for using the additional analysis information. Is possible. For example, a wiring list based on a distance between wirings obtained by the defect analysis apparatus 10, a proximity length, or a score value of a defect probability obtained therefrom, and a wiring based on a score value of the defect probability in additional analysis information Two different diagnosis results from the list may be displayed at the same time, and the wiring defect may be determined from the information.

  The semiconductor failure analysis apparatus, failure analysis method, and failure analysis program according to the present invention are not limited to the above-described embodiments and configuration examples, and various modifications are possible. For example, as the proximity wiring information for the candidate wiring, in the above configuration example, the information on the proximity wiring and the information on the proximity portion between the candidate wiring and the proximity wiring are acquired. Depending on the situation, only the information on the proximity wiring or only the information on the proximity location may be acquired.

  Moreover, about the specific extraction method of the proximity wiring and proximity location with respect to a candidate wiring, FIGS. 7-10 shows the example, and may use various methods besides that. In general, any candidate wiring extracted from a plurality of wirings of a semiconductor device may be configured so as to obtain adjacent wiring information by referring to the distances between the other wirings and the candidate wiring in the plurality of wirings.

  INDUSTRIAL APPLICABILITY The present invention can be used as a semiconductor failure analysis apparatus, a failure analysis method, and a failure analysis program that can reliably and efficiently analyze a failure of a semiconductor device using a failure observation image.

It is a block diagram which shows the structure of one Embodiment of the failure analysis system containing a semiconductor failure analysis apparatus. It is a block diagram which shows the specific structure of a defect analysis part. It is a figure showing typically about a semiconductor failure analysis method. It is a figure which shows typically about a response | compatibility of an observation image and a layout image. It is a flowchart which shows an example of a semiconductor failure analysis method. It is a block diagram which shows an example of a semiconductor inspection apparatus. It is a figure which shows an example of the determination method of the adjacent wiring with respect to a candidate wiring. It is a figure which shows the other example of the determination method of the adjacent wiring with respect to a candidate wiring. It is a figure which shows an example of the extraction method of the proximity location of a candidate wiring and a proximity wiring. It is a figure which shows the other example of the extraction method of the proximity location of a candidate wiring and a proximity wiring. It is a figure which shows the example of a display of a wiring list display screen. It is a figure which shows the example of a display of a proximity location extraction screen. It is a figure which shows the example of a display of a wiring list display screen.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor failure analysis system, 10 ... Semiconductor failure analysis apparatus, 11 ... Inspection information acquisition part, 12 ... Layout information acquisition part, 13 ... Defect analysis part, 131 ... Area setting part, 136 ... Analysis area setting part, 137 ... Mask Area setting unit 132 ... Wiring information analysis unit 133 ... Position adjustment unit 134 ... Additional analysis information acquisition unit 135 ... Analysis target selection unit 14 ... Analysis screen display control unit 15 ... Layout image display control unit 20 Inspection information supply device, 20A ... Semiconductor inspection device, 21 ... Observation unit, 22 ... Control unit, 23 ... Inspection information processing unit, 24 ... Display device, 30 ... Layout information supply device, 40 ... Display device, 45 ... Input device.

Claims (12)

A semiconductor failure analysis apparatus for analyzing a failure of a semiconductor device,
As an observation image of a semiconductor device, an inspection information acquisition means for acquiring a defect observation image including reaction information caused by a defect obtained by performing an inspection for a defect;
Layout information acquisition means for acquiring layout information of the semiconductor device;
A defect analysis means for analyzing the defect of the semiconductor device with reference to the defect observation image and the layout information,
The defect analysis means refers to the defect observation image, refers to the area setting means for setting an analysis area corresponding to the reaction information, and refers to the analysis area for a plurality of wirings included in the layout of the semiconductor device. Wiring information analysis means for performing defect analysis,
The wiring information analyzing unit extracts a wiring that passes through the analysis area among the plurality of wirings as a defective candidate wiring, and calculates a distance between the other wirings in the plurality of wirings and the candidate wiring. Referring to and obtaining proximity wiring information for the candidate wiring ,
The wiring information analysis means sets a distance threshold for acquiring the proximity wiring information, and when the distance between the other wirings in the plurality of wirings and the candidate wiring is equal to or less than the distance threshold, together with the other wires to determine that adjacent wire for the candidate interconnection, the plurality of layers in the laminated structure of a semiconductor device, a semiconductor failure analysis, characterized that you have been capable of setting the distance threshold for each layer apparatus. The wiring information analyzing means refers to a distance between another wiring and the candidate wiring in the plurality of wirings and a proximity length thereof, and acquires the neighboring wiring information for the candidate wiring. failure analysis apparatus of claim 1 Stories mounting to. When a plurality of candidate wirings are extracted as the candidate wirings, the wiring information analyzing unit selects a suspected defective wiring that is a candidate wiring from which the proximity wiring information is to be acquired, among the plurality of candidate wirings, failure analysis apparatus according to claim 1, wherein the obtaining the adjacent wire information for the suspected faulty wiring. The wiring information analyzing means may determine that the adjacent wiring is another candidate wiring included in the plurality of candidate wirings when another wiring of the plurality of wirings is determined to be a neighboring wiring with respect to the suspected defective wiring. The failure analysis apparatus according to claim 3 , wherein failure analysis is performed on the plurality of wirings in consideration of whether or not the plurality of wirings are present. A semiconductor failure analysis method for analyzing a failure of a semiconductor device,
As an observation image of the semiconductor device, an inspection information acquisition step for acquiring a defect observation image including reaction information resulting from the defect, obtained by performing an inspection for the defect,
A layout information acquisition step of acquiring layout information of the semiconductor device;
A failure analysis step of analyzing the defect of the semiconductor device with reference to the defect observation image and the layout information,
The defect analysis step refers to the defect observation image, refers to the region setting step for setting an analysis region corresponding to the reaction information, and refers to the analysis region for a plurality of wirings included in the layout of the semiconductor device. Wiring information analysis step for performing defect analysis,
In the wiring information analyzing step, a wiring that passes through the analysis area among the plurality of wirings is extracted as a defective candidate wiring, and a distance between the other wirings in the plurality of wirings and the candidate wiring is determined. Referring to and obtaining proximity wiring information for the candidate wiring ,
The wiring information analysis step sets a distance threshold for acquiring the proximity wiring information, and when the distance between the other wiring and the candidate wiring in the plurality of wirings is equal to or less than the distance threshold, together with the other wires to determine that adjacent wire for the candidate interconnection, the plurality of layers in the laminated structure of a semiconductor device, a semiconductor failure analysis, characterized that you have been capable of setting the distance threshold for each layer Method. The wiring information analysis step refers to a distance between another wiring in the plurality of wirings and the candidate wiring, and a proximity length thereof, and acquires the neighboring wiring information for the candidate wiring. The failure analysis method according to claim 5 . In the wiring information analyzing step, when a plurality of candidate wirings are extracted as the candidate wirings, a suspected defective wiring that is a candidate wiring to be acquired from the proximity wiring information is selected from the plurality of candidate wirings, The failure analysis method according to claim 5, wherein the proximity wiring information for the suspected defective wiring is acquired. In the wiring information analyzing step, when another wiring of the plurality of wirings is determined to be a proximity wiring with respect to the suspected defective wiring, the proximity wiring becomes another candidate wiring included in the plurality of candidate wirings. The failure analysis method according to claim 7 , wherein failure analysis is performed for the plurality of wirings in consideration of whether or not there is any. A program for causing a computer to execute a semiconductor failure analysis for analyzing a failure of a semiconductor device,
As an observation image of a semiconductor device, an inspection information acquisition process for acquiring a defect observation image including reaction information caused by a defect obtained by performing an inspection for a defect;
Layout information acquisition processing for acquiring layout information of the semiconductor device;
Causing the computer to execute a defect analysis process for analyzing the defect of the semiconductor device with reference to the defect observation image and the layout information;
The defect analysis process refers to the defect observation image, an area setting process for setting an analysis area corresponding to the reaction information, and a reference to the analysis area for a plurality of wirings included in the layout of the semiconductor device. Wiring information analysis processing that performs defect analysis,
The wiring information analysis process extracts a wiring that passes through the analysis region among the plurality of wirings as a defective candidate wiring, and determines a distance between the other wirings in the plurality of wirings and the candidate wiring. Referring to and obtaining proximity wiring information for the candidate wiring ,
The wiring information analysis process sets a distance threshold for acquiring the adjacent wiring information, and when the distance between the other wirings in the plurality of wirings and the candidate wiring is equal to or less than the distance threshold, together with the other wires to determine that adjacent wire for the candidate interconnection, the plurality of layers in the laminated structure of a semiconductor device, a semiconductor failure analysis, characterized that you have been capable of setting the distance threshold for each layer program. The wiring information analysis process refers to a distance between another wiring of the plurality of wirings and the candidate wiring and a proximity length thereof, and acquires the neighboring wiring information with respect to the candidate wiring. The failure analysis program according to claim 9 . In the wiring information analysis process, when a plurality of candidate wirings are extracted as the candidate wirings, a suspected defective wiring that is a candidate wiring to be acquired from the neighboring wiring information is selected from the plurality of candidate wirings, The defect analysis program according to claim 9 or 10, wherein the proximity wiring information for the suspected defective wiring is acquired. In the wiring information analysis process, when another wiring of the plurality of wirings is determined to be a neighboring wiring with respect to the suspected defective wiring, the neighboring wiring becomes another candidate wiring included in the plurality of candidate wirings. The defect analysis program according to claim 11 , wherein the defect analysis is performed on the plurality of wirings in consideration of whether or not the plurality of wirings are present.

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