JP5155644B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor device assembled using a lead frame.

  A ground connection portion is disposed between the semiconductor chip and the inner lead and electrically connected to the ground pad of the semiconductor chip by wire bonding, and the ground connection portion is electrically connected to the tab suspension lead. As a result, there is a technique for stabilizing the ground potential (see, for example, Patent Document 1).

In addition, there is a technique in which a lead frame having a die pad size smaller than the size of a semiconductor chip is used, and a suspension lead and an inner lead portion of the lead frame are connected to each other with an insulating tape (see, for example, Patent Document 2).
JP-A-11-168169 Japanese Patent Laid-Open No. 11-224929

  In recent years, with an increase in performance of semiconductor devices, for example, the number of external terminals (number of pins) for exchanging data signals between the semiconductor device and external electronic devices tends to increase. As a configuration for realizing such a multi-pin semiconductor device, for example, a BGA (Ball Grid Array) is known. BGA has a structure in which a semiconductor chip is mounted on the main surface of a wiring board and a ball electrode which is an external terminal is provided on the back surface, and is suitable for increasing the number of pins. However, since the wiring board has a structure having wiring layers and insulating layers formed in multiple layers, the material cost is higher than that of the lead frame, and the manufacturing cost of the BGA is relatively high. Therefore, in recent years, as a means for reducing the manufacturing cost of the BGA, a region constituting a plurality of semiconductor devices is provided on one wiring board, and a plurality of regions are formed after mounting a semiconductor chip in each of the plurality of regions. A so-called MAP (Multi Array Package) method in which resin sealing is performed collectively is effective.

  However, if the product size of BGA per pin becomes large due to the increase in the number of pins, only 4 to 5 products can be obtained from one wiring board, and the batch mold type multi-chip substrate (MAP substrate) ), The manufacturing cost increases. Therefore, it is effective to adopt a lead frame type such as QFP (Quad Flat Package) in order to realize cost reduction.

  If a lead frame is used, the manufacturing cost can be reduced because wiring layers and insulating layers are not routed in multiple layers like a wiring board used in a BGA.

  However, the QFP has a configuration in which a semiconductor chip can be mounted and a plurality of leads are arranged around the tab. In other words, since leads serving as external terminals are arranged at the peripheral edge of the semiconductor device, the outer dimensions of the semiconductor device increase as the number of pins increases.

  Therefore, as one means for achieving a large number of pins in a lead frame type semiconductor device while realizing a reduction in the size of the semiconductor device, a power supply or a GND as disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 11-168169). It is effective to reduce the number of terminals (external terminals) to be drawn out by sharing (ground). In other words, a common lead called a bus bar lead or bar lead is provided, and a wire such as a power supply or a GND is connected to the bus bar lead so that the lead is shared and the number of terminals to be pulled out is reduced to increase the number of pins. Is intended.

  However, since the lead frame is made of metal, the lead frame expands and contracts due to the influence of heat in the die bonding process for mounting the semiconductor chip and the wire bonding process for electrically connecting the semiconductor chip and the lead with a wire ( Thermal distortion) is likely to occur. This expansion / contraction action is particularly likely to occur when the lead frame is made of a metal such as a copper alloy. In the wire bonding process, wire bonding can be performed with a part of the lead (region outside the part where the wire is connected) fixed with a holding jig (clamper), but the wire that connects the semiconductor chip and the lead is formed. The bus bar lead that overlaps with the area to be pressed cannot be pressed by the pressing jig. Therefore, when the expansion action is applied to the lead frame, both ends of the bus bar lead are fixed to the suspension leads that support the tabs, so that they cannot expand in the horizontal direction and the bus bar lead is bent. In such a state, when the bus bar lead and the wire are connected, the 2nd side that is not pressed by the pressing jig jumps up and the wire is not crimped. Moreover, there is a possibility that the wire may be peeled (disconnected) due to the non-bonding of the wire.

  Also, as a method of fixing the bus bar lead, it is conceivable to fix it by vacuum suction, but even if vacuum suction is performed, it is difficult to sufficiently suppress the bending of the lead frame. The temperature of the heat stage used in the process varies due to evacuation, and wire connection defects are likely to occur as well.

  In addition, the wire connected to the lead needs to be bonded across the bus bar lead, and if the bus bar lead is bent due to thermal strain, a problem arises that a wire short occurs.

  Furthermore, as shown in Patent Document 1, if the bus bar leads are simply arranged in a ring shape, a problem arises that tab fluctuations occur in synchronization with thermal fluctuations of the bus bar leads.

  Further, since the number of inner leads increases due to the increase in the number of pins, there is a problem that the shape of the tip of the inner lead is tapered and the rigidity of the inner lead is lowered.

  Further, when the number of inner leads increases due to the increase in the number of pins, the pitch between the leads also decreases, which causes a problem that the fluidity of the mold resin at the time of resin molding is lowered.

  Patent Document 1 describes a structure having a small tab structure and a ground connection portion provided between a tab and an inner lead. Also, Patent Document 2 (Japanese Patent Laid-Open No. 11-224929) is disclosed. ) Describes a small tab structure and a structure in which the suspension lead is bent.

  However, Patent Documents 1 and 2 do not describe any countermeasures against bus bar leads that are bent due to expansion / contraction due to the influence of heat of the lead frame.

  An object of the present invention is to provide a technique capable of realizing the manufacture of a multi-pin semiconductor device with a lead frame.

  Another object of the present invention is to provide a technique capable of reducing the cost of a semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the quality of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention is mounted on the chip support surface of the chip mounting portion, the chip mounting portion whose outer size of the chip support surface is smaller than the back surface of the semiconductor chip, the plurality of leads arranged around the chip mounting portion, and A semiconductor chip; a plurality of suspension leads that support the chip mounting portion; and a bar-shaped common lead that is disposed outside the chip mounting portion so as to surround the chip mounting portion and is connected to the suspension lead. The 1st slit is formed in this.

  The present invention also provides a chip mounting portion, a plurality of suspension leads formed integrally with the chip mounting portion, each provided with a slit, a plurality of leads provided around the chip mounting portion, and the chip A step of preparing a lead frame having a plurality of common leads that are respectively positioned between the mounting portion and the plurality of leads and integrally formed with the plurality of suspension leads, and a main surface on which the plurality of electrodes are formed. A step of mounting the semiconductor chip on the chip mounting portion; a step of electrically connecting the plurality of electrodes of the semiconductor chip and the plurality of common leads through a plurality of common lead wires; Electrically connecting the plurality of electrodes and the plurality of leads through a plurality of lead wires, respectively, the semiconductor chip, -Up mounting portion, said plurality of common lead wire and said plurality of lead wires is intended to include the step of sealing with resin.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  A bar-shaped common lead connected to the suspension lead is arranged outside the chip mounting part so as to surround the chip mounting part, and a slit is formed in the common lead, so that the expansion and contraction action due to the influence of heat is common. Even if it acts on the lead, the expansion / contraction action can be relaxed by the slit, and the bending (deformation) due to the expansion / contraction of the common lead can be reduced.

  As a result, occurrence of wire peeling can be prevented, and wire bonding to the common lead is also possible. As a result, a multi-pin semiconductor device can be manufactured with a lead frame.

  Further, the manufacturing cost of the semiconductor device can be reduced by using the lead frame.

  Moreover, since the bending due to the expansion / contraction of the common lead can be reduced, the occurrence of wire shorts can be reduced. As a result, the reliability and quality of the semiconductor device can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated, and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently indispensable in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape and positional relationship of components and the like, the shape is substantially the same unless otherwise specified and the case where it is not clearly apparent in principle. And the like are included. The same applies to the numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

(Embodiment)
1 is a plan view showing an example of the structure of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing an example of a structure cut along the line AA in FIG. 1, and FIG. FIG. 4 is a cross-sectional view showing an example of the structure cut along the line BB, FIG. 4 is a cross-sectional view showing an example of the manufacturing process until the completion of wire bonding in the assembly of the semiconductor device shown in FIG. 1, and FIG. It is sectional drawing which shows an example of the manufacturing process after the wire bonding in the assembly of a semiconductor device. 6A is a partial plan view showing an example of the structure of the lead frame used for assembling the semiconductor device shown in FIG. 1, and FIG. 6B is a part showing a part of the lead frame used for assembling the semiconductor device shown in FIG. 6A. FIG. 7 is an enlarged plan view, FIG. 7 is a partial plan view showing an example of the structure of the second offset portion of the lead frame used for assembling the semiconductor device shown in FIG. 1, and FIG. 8 is cut along the line AA in FIG. It is sectional drawing which shows an example of a structure. 9 is a plan view showing an example of a clamp region during wire bonding in the assembly of the semiconductor device shown in FIG. 1, and FIG. 10 is a cross section showing an example of a clamp structure during wire bonding in the assembly of the semiconductor device shown in FIG. 11 and 11 are partial plan views showing an example of the structure after resin molding in the assembly of the semiconductor device shown in FIG.

  12 is a cross-sectional view showing the structure of a lead frame used for assembling a semiconductor device according to a modification of the embodiment of the present invention. FIG. 13 shows a resin used in assembling the semiconductor device according to the modification of the embodiment of the present invention. FIG. 14 is a cross-sectional view showing the structure of a semiconductor device according to a modification of the embodiment of the present invention. FIG. 14 is a partial plan view showing the structure after molding through the sealing body.

  The semiconductor device according to the present embodiment is a surface-mount type assembled using a lead frame, is multi-pin, and has a common lead to which a power supply, GND, and the like are connected. The QFP 6 will be described as follows.

  The configuration of the semiconductor device (QFP 6) will be described with reference to FIGS. 1 to 3. The semiconductor device (QFP 6) has a chip support surface 1 d that can support the semiconductor chip 2, and the outer size of the chip support surface 1 d is the back surface of the semiconductor chip 2. A tab (chip mounting portion) 1c smaller than 2b, a plurality of leads arranged around the tab 1c, a semiconductor chip 2 mounted on the chip support surface 1d of the tab 1c, and a plurality of suspensions supporting the tab 1c. It consists of lead 1e. Further, the QFP 6 is disposed so as to surround the tab 1c outside the tab 1c and electrically connects the bar-shaped common lead connected to the suspension lead 1e, the pad (electrode) 2c of the semiconductor chip 2 and the lead. The first wire 4a to be connected, the second wire 4b to electrically connect the pad 2c of the semiconductor chip 2 and the common lead, and the semiconductor chip 2, the first wire 4a and the second wire 4b are made of resin. It has the sealing body 3 to seal.

  6A and 6B, the structure of the semiconductor device (QFP 6) will be described in another expression. The semiconductor device 2 has a chip support surface 1d that can support the semiconductor chip 2, and the outer size of the chip support surface 1d. Includes a chip mounting portion (tab, die pad) 1 c smaller than the back surface 2 b of the semiconductor chip 2. The chip mounting portion 1c includes a plurality of suspension leads 1e that are formed integrally with each of the chip mounting portions 1c and each provided with a slit (first slit 1g). Further, the semiconductor chip 2 includes a main surface 2a on which a plurality of pads (electrodes) 2c are formed, and is mounted on the chip mounting portion 1c. Further, the semiconductor chip 2 includes a plurality of leads (inner leads 1 a) provided around the semiconductor chip 2. Further, a plurality of bar-shaped common leads (bus bar leads, bars) which are respectively positioned between the chip mounting portion 1c and the plurality of leads (inner leads 1a) and integrally formed with the plurality of suspension leads 1e. Lead) including 1f. In addition, the semiconductor chip 2 includes a plurality of wires (first wire 4a, lead wire) 4 for electrically connecting the plurality of electrodes 2c and the plurality of leads (inner leads 1a). Also included are wires (second wire 4b, common lead wire) 4 for electrically connecting the plurality of electrodes 2a of the semiconductor chip 2 and the plurality of bar-shaped common leads 1f, respectively. In addition, the semiconductor chip 2, the chip mounting portion 1 c, and the sealing body 3 that seals the plurality of wires (first wire 4 a and second wire 4 b) 4 are included. Furthermore, it includes a plurality of outer leads 1 b that are integrally formed with each of the plurality of leads (inner leads 1 a) and exposed from the sealing body 3.

  Each of the plurality of leads is a plurality of inner leads 1a embedded in the sealing body 3 and external terminals exposed to the outside of the sealing body 3, and a plurality of bending leads formed in a gull wing shape. The outer lead 1b is provided, and the inner lead 1a and the outer lead 1b are integrally connected.

  Further, in the QFP 6, as shown in FIGS. 6A and 6B, a bar lead 1f, which is a bar-shaped elongated common lead, is provided in a region between the tab 1c and the tips of the plurality of inner leads 1a.

  In addition, the slit (through hole, hole) in the present embodiment refers to a configuration in which a part of the lead frame (suspended lead 1e) 1 is excluded, and this has the effect of relieving the stress applied to the lead frame 1. is there.

  Further, in the present embodiment, the width of the bar-shaped common lead (bar lead) 1f is narrower than the width of the suspension lead 1e (the total width including the first slit 1g and the second slit 1n). Therefore, the length of the first wire 4a that electrically connects the pad (electrode) 2c of the semiconductor chip 2 and the corresponding inner lead 1a is set so that the width of the common lead 1f is larger than the width of the suspension lead 1e. Compared to the thick case, it can be shortened. As a result, the signal propagation speed can be increased. Moreover, the short circuit defect of the wire which arises when the wire 4 is poured with resin in the resin sealing process can be suppressed.

  The bar lead 1f is a lead capable of connecting a plurality of wires 4 of the pad 2c that can be shared by a power source, a GND, and the like. Further, both end portions of the bar lead (common lead, bus bar lead) 1f are formed integrally with the adjacent suspension lead 1e. Therefore, in the semiconductor chip 2 that requires a large number of pads for power supply and GND for the purpose of improving electrical characteristics, the number of pads can be increased by sharing the signals from the increased power supply and pads such as GND in the package. Since the number of leads (inner leads and outer leads) can be reduced as compared with the above, it is very effective as a means for suppressing an increase in package size.

  In the QFP 6, four bar leads 1f are provided corresponding to each of the four sides of the semiconductor chip 2, and each side extends along the arrangement direction of the tips of the plurality of inner leads 1a. Both ends of each bar lead 1f are connected to suspension leads 1e provided along the diagonal direction of the main surface 2a of the semiconductor chip 2. Therefore, the bar lead 1f is formed in a rectangular frame shape around the tab 1c.

  Since the bar lead 1f is formed in a rectangular frame shape, the power source or the GND wire 4 can be connected in four directions. Furthermore, the flow balance of the mold resin in the four directions can be made substantially uniform.

  In the QFP 6, as shown in FIGS. 6A and 6B, a first slit 1g is formed in each bar lead 1f. That is, the 1st slit 1g is formed in the 1st connection part 1j with the suspension lead 1e of the bar lead 1f.

  The suspension lead 1e has a plurality of slits (first slit 1g, second slit 1n) as means for relieving stress. The first slit 1g will be described in detail as follows. That is, as shown in FIG. 6B, the first slit 1g is provided so as to extend to the portion where the end of the common lead (bar lead, bus bar lead) 1f is connected in the suspension lead 1e. In other words, the slit (first slit 1g) which is a means for relieving stress is formed on the extended line of the common lead 1f indicated by a two-dot chain line L (virtual line) in FIG. 6B in the suspension lead 1e.

  Further, the slit (through hole, hole) in the present embodiment has a configuration in which the suspension lead 1e is partially cut off. More specifically, as shown in FIG. 3, from the main surface of the suspension lead 1e (surface on the same side as the main surface 2a of the semiconductor chip 2) to the back surface (surface on the same side as the back surface 2b of the semiconductor chip 2). It is a through hole (hole) that penetrates.

  As described above, the bar lead 1f connected to the suspension lead 1e is disposed outside the tab 1c so as to surround the tab 1c, and the first slit 1g is formed in the first connection portion 1j of the bar lead 1f with the suspension lead 1e. As a result, even if the expansion / contraction (thermal strain) effect due to the effect of heat acts on the bar lead 1f, the expansion / contraction effect can be mitigated by the provision of the first slit 1g.

  In short, it is as follows. That is, even if the common lead 1f expands due to the heat of the heated bonding stage 10 in the wire bonding process, the end of the common lead (bar lead, bus bar lead) 1f is connected to the suspension lead 1e. Since the slit (the first slit 1g) is formed in the portion to be suspended, the suspension lead 1e is deformed and does not hinder the expansion of the suspension lead 1e.

  Thereby, it can reduce that the bar lead 1f deform | transforms, and the fluctuation | variation of the tab 1c connected via the suspension lead 1e can also be reduced.

  Also, a ring-shaped thin film tape material 1q for preventing flapping and deformation of the inner lead 1a is attached to the outer portion of the wire bonding region at the tip of the inner lead 1a.

  The QFP 6 of the present embodiment has a small tab structure (a tab 1c smaller than the outer dimensions of the semiconductor chip 2), and therefore, the size of the mounted semiconductor chip 2 can be made versatile. The reflow resistance can be improved.

  Further, when the QFP 6 is assembled, for example, it is assembled using a lead frame (see FIGS. 6A and 6B) 1 made of a copper alloy. Therefore, the tab 1c, the plurality of inner leads 1a and the outer leads 1b, the four suspension leads 1e and the bar leads 1f are made of a copper alloy. Further, in each of the plurality of inner leads 1a and the four bar leads 1f, silver plating is applied to a region where the wire 4 is connected to form a plating film (plating layer) 1f '.

  By forming the plating film (plating layer) 1f ', the connectivity between the wire 4 made of gold and the inner lead 1a made of copper can be improved. Further, although not shown, silver plating is similarly applied to a portion to which the tip portion (wire 4) of the inner lead 1a is connected to form a plating film (plating layer) 1f '.

  Further, the semiconductor chip 2 is made of, for example, silicon, and a plurality of pads 2c serving as electrodes are formed on the main surface 2a. The back surface 2b is bonded to the tab 1c via a die bond material, and the semiconductor chip 2 is supported by the tab 1c.

  The wire 4 including the first wire 4a and the second wire 4b is, for example, a gold wire. Further, the sealing resin forming the sealing body 3 is, for example, a thermosetting epoxy resin. Next, other characteristic parts of the QFP 6 will be described.

  As shown in FIGS. 3, 6A, and 6B, in the QFP 6, a first offset portion 1m is formed by bending at a location inside the first connecting portion 1j of each of the four suspension leads 1e with the bar lead 1f. Has been.

  By forming the first offset portion 1m, it is possible to prevent the location (position) of the tab 1c from fluctuating due to thermal distortion or thermal deformation of the bar lead 1f. That is, even if thermal distortion or thermal deformation occurs in the bar lead 1f, the influence is mitigated and absorbed by the first offset portion 1m, and thus is not transmitted to the tab 1c. As a result, the location (position) of the tab 1c varies. Can be prevented.

  Furthermore, since the first offset portion 1m is formed, versatility can be given to products having different chip thicknesses in which the thickness of the semiconductor chip 2 is different. That is, by adjusting the offset amount of the first offset portion 1m, the amount of resin on the upper side and the lower side of the semiconductor chip 2 can be adjusted, and the resin balance can be adjusted.

  Here, the details of the positional relationship between the first offset portion 1m and the common lead (bar lead, bus bar lead) 1f will be described below. FIG. 15 is a partial cross-sectional view showing an example of a structure at the time of mold clamping by a mold when using a lead frame without offset in the embodiment of the present invention.

  First, when the lead frame 1 on which the first offset portion 1m is not formed is used for the suspension lead 1e, as shown in FIG. 15, from the cavity surface 14b of the upper mold 14a in the mold 14 (resin molding mold). The interval X to the main surface 2a of the semiconductor chip 2 is narrower than the interval Y from the cavity surface 14d of the lower mold 14c to the back surface of the tab 1c in the mold 14 (resin mold).

  Therefore, in the resin sealing step, the amount of resin that wraps around the back surface side of the tab 1c is larger than the amount of resin that wraps around the main surface 2a of the semiconductor chip 2, and the resin balance varies. Due to the dispersion of the resin balance, the tab 1c on which the semiconductor chip 2 is mounted is pushed upward, and a problem that a part of the wire 4 is exposed from the upper surface of the sealing body 3 or a problem that the wire 4 is disconnected occurs. .

  Therefore, in the present embodiment, as shown in FIGS. 3, 6A, and 6B, the first offset portion 1m is formed on the suspension lead 1e. If it simplifies, it will be bent toward the back surface from the main surface of the suspension lead 1e. Thereby, the resin balance can be made substantially uniform.

  Here, in the present embodiment, the first offset portion 1m is formed closer to the tab 1c than the portion of the suspension lead to which the end of the common lead 1f is connected. This is because the first offset portion 1m is formed between the tab 1c and the common lead 1f, so even if thermal distortion or thermal deformation occurs in the common lead 1f, the influence is mitigated by the first offset portion 1m. -Since it is absorbed, it is difficult to be transmitted to the tab 1c. As a result, fluctuations in the location (position) of the tab 1c can be suppressed.

  Note that the offset amount of the first offset portion 1m is, for example, 0.24 mm.

  In addition, as shown in FIGS. 6A and 6B, the QFP 6 has a plurality of inner leads 1a connected to the bar leads 1f among the plurality of inner leads 1a. The plurality of inner leads 1a connected to the bar lead 1f includes a first inner lead 1h, a second inner lead 1i adjacent to the first inner lead 1h, and the first inner lead 1h and the first inner lead 1h at the end on the bar lead 1f side. 2nd connection part 1r which connects 2 inner leads 1i.

  That is, the inner lead 1a connected to the bar lead 1f includes a first inner lead 1h, a second inner lead 1i, and a second connecting portion 1r. The second connecting portion 1r includes the first inner lead 1h and the second inner lead. 1i is arranged between the bar lead 1f and the tip of each bar lead 1f side.

  As described above, the second connecting portion 1r that connects the first inner lead 1h and the second inner lead 1i is disposed between the tip of the inner lead 1a on the bar lead 1f side and the bar lead 1f. Here, since the tip of the inner lead 1a is tapered, the rigidity of the tip side of the first inner lead 1h and the second inner lead 1i can be ensured by providing the second connecting portion 1r.

  Further, as shown in FIGS. 6A and 6B, the outer (outer lead side) ends of the first inner lead 1h and the second inner lead 1i are branched from each other, and are connected like the bar lead 1f side. Not.

Thereby, in the resin sealing step, the fluidity (flow velocity) of the mold resin passing through the region where the first inner lead 1h and the second inner lead 1i are formed and the region where the other inner lead 1a is formed is almost the same. Can be even. That is, the mold resin flows almost uniformly from the branched first inner lead 1h and second inner lead 1i with the resin flowing between the other inner leads 1a, so that the mold resin has almost uniform fluidity. can do. Thereby, wire flow, deformation of the tab 1c, generation of voids, and the like can be prevented.

  As shown in FIGS. 3, 6A, and 6B, each of the four suspension leads 1e is formed with a second slit 1n outside the first coupling portion 1j with the bar lead 1f. Thereby, the flow rate of the mold resin flowing at the time of resin injection can be made uniform to prevent the wire flow, the deformation of the tab 1c, the generation of voids, and the like.

  More specifically, the four suspension leads 1e are provided to support the tab 1c. However, when the outer dimension (size) of the tab 1c is smaller than the outer dimension (size) of the semiconductor chip 2 (small tab structure) as in the present embodiment, the length of each suspension lead 1e is also the same as that of the tab 1c. The outer dimension is longer than that when the outer dimension of the semiconductor chip 2 is larger (large tab structure). When the shape of the suspension lead 1e is simply elongated, the suspension lead 1e is bent by the resin injection pressure in the resin sealing process, and the location (position) of the tab varies.

  Therefore, as shown in FIGS. 6A and 6B, the rigidity of the suspension lead 1e is improved by forming the suspension lead 1e wider. Further, as shown in FIGS. 3, 6A, and 6B, the suspension lead 1e is formed with a second slit (through hole, hole) 1n. The reason for this is as follows.

  The lead frame 1 of the present embodiment is a thin plate member made of, for example, a copper alloy, and the adhesion between the lead frame 1 and the mold resin (sealing body 3, resin) is, for example, a semiconductor chip 2 made of silicon and a mold. Low compared to adhesion to resin. Therefore, if the width of the suspension lead 1e is simply increased, peeling occurs at the interface between the sealing body 3 formed by the resin sealing process and the lead frame (particularly, the suspension lead 1e), and the reliability of the semiconductor device is increased. descend. Therefore, by forming a slit (second slit 1n) in the suspension lead 1e, the resin formed in the slit becomes an anchor effect, and the sealing body 3 and the lead frame (suspension lead 1e) 1 are connected. Adhesion can be improved. Also, by providing slits in the suspension leads 1e, the density of leads near each side of the semiconductor chip 2 having a square planar shape and the density of leads near the corners of the semiconductor chip 2 can be made substantially uniform. . As a result, the flow rate of the resin when flowing in the vicinity of the suspension lead 1e and the flow rate of the resin when flowing in the vicinity of the plurality of leads (inner leads 1a) can be made substantially uniform. It does not occur, and a decrease in resin balance can be suppressed.

  Here, focusing only on suppressing the decrease in the resin balance described above, only one slit larger than the respective slits (the first slit 1g and the second slit 1n) shown in FIG. 6A is provided on the suspension lead 1e. It may be formed. However, when the outer dimension (size) of the tab 1c is smaller than the outer dimension (size) of the semiconductor chip 2 as in the present embodiment, the length of each suspension lead 1e is longer than that of the large tab structure. . Therefore, in the lead frame 1 having such a small tab structure, when one large slit is formed in the suspension lead 1e, the rigidity of the suspension lead 1e may be reduced. Therefore, as shown in FIG. 6A, the rigidity of the suspension lead 1e can be suppressed from being lowered by dividing the slit into a plurality of slits and forming the slit in the suspension lead 1e.

  The slits (the first slit 1g and the second slit 1n) have a width wider than the width of each of the suspension leads 1e divided by the slit. Thereby, each shape of the divided | segmented suspension lead 1e can be match | combined with the shape of the adjacent inner lead 1a. Therefore, the flow rate of the resin flowing from the inner lead 1a toward the suspension lead 1e (or from the suspension lead 1e to the inner lead 1a) can be suppressed from greatly fluctuating.

  In addition, a plating film (plating layer) 1f ′ is formed on the surface of the bar lead 1f by silver plating for pressure bonding of the wire 4, but it is not applied to the entire surface of the bar lead 1f. (For example, the outer portion of the bar lead 1f in FIGS. 6A and 6B). The silver plating has low adhesion to the mold resin, but as shown in FIGS. 6A and 6B, the plating film 1f ′ is formed only in the region where the wire 4 is connected to the bar lead 1f instead of the entire surface. Thus, the adhesion between the mold resin and the bar lead 1f can be improved, and the reliability and quality of the semiconductor device can be improved.

  That is, the adhesion between the silver plating and the mold resin is lower than the adhesion between the lead frame 1 made of a copper alloy and the mold resin, but the mold resin and the lead frame are formed only in the region where the wire 4 is connected. (Common lead 1 f) A decrease in adhesion with 1 can be suppressed.

  As shown in FIG. 7, among the four bar leads 1f arranged in a rectangular frame shape, the bar leads 1f that are not connected to the tip of the inner lead 1a at portions other than both ends are shown in FIG. A second offset portion 1p is formed.

  The second offset portion 1p is a strain relief when the inner lead 1a is clamped by the clamper 11 (see FIGS. 4 and 10) during wire bonding. That is, as shown in FIG. 9, at the time of wire bonding, the bar lead 1f is not clamped by the clamper 11, but only the inner lead 1a is clamped. At that time, when the inner lead 1a is clamped, of the four bar leads 1f, the bar lead 1f connected to the inner lead 1a is fixed, so that the inner lead 1a is hardly affected by the distortion. Distortion concentrates on the bar lead 1 f not connected to the bar lead 1 f and the bar lead 1 f is deformed, and the bar lead 1 f floats from the bonding stage 10 shown in FIG. 10.

  Therefore, as a countermeasure against the floating of the bar lead 1f, the bar lead 1f that is not connected to the inner lead 1a at portions other than both ends is subjected to offset processing as shown in FIG. It can be brought into close contact with the stage 10. That is, the adhesion between the bar lead 1f and the bonding stage 10 can be secured.

  As an example of the location where the offset processing is performed, it is preferable to form the second offset portion 1p in a region not connected to the inner lead 1a of the bar lead 1f. In the example shown in FIG. 7, in the vicinity of both ends of the bar lead 1f. It is formed slightly inward.

  In the QFP 6 of the present embodiment, the bar lead 1f that is not connected to the tip of the inner lead 1a at a portion other than both ends is one of the four bar leads 1f.

  The offset amount (T) of the second offset portion 1p of the bar lead 1f shown in FIG. 8 is, for example, about 0.05 mm that can be formed by coining. Therefore, the offset amount (0.05 mm) of the second offset portion 1p of the bar lead 1f is much smaller than the offset amount (0.24 mm) of the first offset portion 1m of the suspension lead 1e.

  In the QFP 6, the inner lead 1a in the region not connected to the inner lead 1a of the bar lead 1f is a signal lead group, and a lead group connected to the outside is arranged in this region. Therefore, in this region, it is difficult to connect the bar lead 1f and the inner lead 1a.

  As shown in FIG. 2, in the QFP 6, the adjacent inner leads 1a or the adjacent wires 4 connected to the bar leads 1f and the inner leads 1a have different loop heights. That is, in the QFP 6, since the wire 4 (first wire 4a) is connected to the inner lead 1a beyond the bar lead 1f, the wire length becomes long and wire touch failure is likely to occur.

  Therefore, occurrence of wire touch can be prevented by changing the loop height between adjacent wires.

  Next, assembly of the QFP 6 according to the present embodiment will be described with reference to the process flow diagrams shown in FIGS.

  First, lead frame preparation shown in step S1 of FIG. 4 is performed. As shown in FIGS. 6A and 6B, the lead frame 1 is provided with four bar leads (common leads) 1f around a tab 1c, which is a small tab, and is connected to the suspension leads 1e at both ends. In addition, a first slit 1g is formed in the first connecting portion 1j with the suspension lead 1e.

  More specifically, as shown in FIGS. 6A and 6B, a chip mounting portion (tab, die pad) 1c and the chip mounting portion 1c are formed integrally with each other, and a slit (first slit 1g) is provided respectively. A plurality of suspension leads 1e, a plurality of leads (inner leads 1a) provided around the chip mounting portion 1c, and a position between the chip mounting portion 1c and the plurality of leads (inner leads 1a), respectively. Then, a lead frame 1 including a plurality of common leads (bar leads, bus bar leads) 1f integrally formed with the plurality of suspension leads 1e is prepared.

  Further, in the lead frame 1, a slit (first slit 1g) which is a means for relieving stress is provided in a portion where the end of the common lead 1f is connected to the suspension lead 1e. In other words, the slit (first slit 1g), which is a means for relieving stress, is formed on the extended line of the common lead 1f indicated by a broken line (virtual line) in FIG. 6B in the suspension lead 1e.

  Further, on each inner lead 1a, a ring-shaped tape material 1q is affixed to a region outside each wire joint portion.

  Of the four bar leads 1f, the three bar leads 1f are connected to the plurality of inner leads 1a via the second connecting portions 1r in the vicinity of the center instead of the respective ends. The other one bar lead 1f is not connected to the inner lead 1a in the vicinity of the center thereof. A second offset portion 1p as shown in FIG. 8 is formed in the bar lead 1f that is not connected to the inner lead 1a near the center.

  The tip of the bar lead 1f side is connected by the second connecting portion 1r, and the plurality of inner leads 1a connected to the bar lead 1f via the second connecting portion 1r are the tips on the side opposite to the bar lead 1f. Each is branched.

  Each suspension lead 1e is formed with a first offset portion 1m inside the first connecting portion 1j with the bar lead 1f.

  The lead frame 1 is a thin plate member made of, for example, a copper alloy.

  Thereafter, die bonding shown in step S2 of FIG. 4 is performed. First, the silver paste 5 is apply | coated from the potting nozzle 7 on the tab 1c. After the application, the main surface 2a of the semiconductor chip 2 is conveyed while being adsorbed and held by the adsorbing collet 8 and is arranged on the tab 1c. As shown in FIGS. 6A and 6B, each suspension lead 1e is formed with a first offset portion 1m on the inner side (the tab 1c side) than the first connection portion 1j with the bar lead 1f. When a semiconductor chip 2 having a large size is mounted on the tab 1c, if a collet having a pyramid shape that holds the outer edge of the semiconductor chip 2 is used, a part of the collet may come into contact with the first offset portion 1m. There is. However, if the suction type collet 8 is used as in the present embodiment, it can be transported by holding only the main surface 2a of the semiconductor chip 2, and therefore the collet for mounting the semiconductor chip 2 on the tab 1c. Even if 8 is lowered, a part of the collet 8 does not come into contact with the first offset portion 1m.

  Thereafter, wire bonding shown in step S3 is performed. First, as shown in FIG. 10, the lead frame 1 is placed on the bonding stage 10. Subsequently, the back surface 2 b of the semiconductor chip 2 is evacuated through the suction holes 10 a, and the semiconductor chip 2 is placed on the bonding stage 10. At the same time, the lead frame 1 is fixed by pressing the tape material 1q of the inner lead 1a from above the lead frame 1 by the clamp portion 11a of the clamper 11. The clamp part 11a of the clamper 11 presses the ring-shaped tape material 1q from above over the entire circumference.

  In brief, in this wire bonding process, the lead frame 1 on which the semiconductor chip 2 is mounted is disposed on the heated bonding stage 10, and each of the plurality of leads (inner leads 1 a) is held by the clamper 11. Is called.

  Here, the reason why the common lead 1f is not pressed by the clamper 11 is that, as shown in FIGS. 9 and 10, the shape of the clamper 11 is formed in a ring shape where the lead is pressed. If the common lead 1f is pressed by the clamper 11 having such a shape, the tip end portion (wire connection region) of the inner lead 1a is covered with the clamper 11, and a plurality of pads (electrodes) 2c of the semiconductor chip 2 are covered. It is difficult to connect the plurality of inner leads 1a with the wires (first wire 4a, lead wire) 4.

  As a result, all inner leads 1a are clamped by the clamp portion 11a during wire bonding. At that time, as shown in FIGS. 9 and 10, none of the four bar leads 1f are clamped.

  In this state, wire bonding is performed using the capillary 9 as shown in FIG. Here, for example, as shown in FIG. 10, the signal pad 2c of the semiconductor chip 2 and the signal inner lead 1a are electrically connected by the first wire 4a, while the power supply for the semiconductor chip 2 ( Alternatively, the pad 2c (for GND) and the bar lead 1f are electrically connected by the second wire 4b.

  At that time, in the adjacent inner leads 1a or the adjacent wires 4 connected to the bar leads 1f and the inner leads 1a, wire bonding is performed by changing their loop heights. In this way, the occurrence of wire touch can be prevented by changing the loop height between adjacent wires.

  In the present embodiment, in consideration of the occurrence of the above-described wire touch, the power supply (or GND) pad 2c and the bar lead 1f of the semiconductor chip 2 are connected to a wire having a low loop height (second wire 4b, After being electrically connected by a common lead wire), the signal pad 2c of the semiconductor chip 2 and the signal inner lead 1a are electrically connected by a wire having a high loop height (first wire 4a, lead wire). Connected.

  In the QFP 6, three of the four bar leads 1f are connected to the inner lead 1a near the center thereof. Therefore, in the wire bonding process, these three bar leads 1f are hardly deformed by thermal strain, but the bar lead 1f not connected to the inner lead 1a near the center is likely to be concentrated and deformed easily. . However, since a second offset portion 1p as shown in FIG. 8 is formed in the bar lead 1f not connected to the inner lead 1a near the center, the bar lead 1f is brought into close contact with the bonding stage 10 during wire bonding. be able to.

  In the assembly of the semiconductor device (QFP6) of the present embodiment, the first slit 1g is formed in the first connecting portion 1j of the bar lead 1f and the suspension lead 1e, so that the expansion / Even if the contraction (thermal strain) action acts on the bar lead 1f, the first slit 1g can mitigate the expansion / contraction action.

  As a result, bending (deformation) due to expansion / contraction of the bar lead 1f can be reduced, and occurrence of wire peeling can be prevented.

  Thereafter, resin molding and baking shown in step S4 of FIG. 5 are performed. Here, the semiconductor chip 2, the bar leads 1f, the plurality of inner leads 1a, and the plurality of wires 4 are sealed with a sealing resin by molding or the like to form a sealing body 3 as shown in FIG.

  Then, exterior plating formation shown in step S5 is performed. Here, the exterior plating 12 is formed on the outer lead 1 b exposed from the sealing body 3.

  Thereafter, the cutting and forming shown in Step S6 is performed. Here, the outer lead 1b is cut and bent to complete the assembly of the QFP 6.

  Here, the importance of the first slit 1g formed in the first connecting portion 1j of the bar lead 1f and the suspension lead 1e in the QFP 6 of the present embodiment will be described.

  When the bar lead 1f is applied to the QFP 6, if the slit is not formed in the connecting portion between the bar lead 1f and the suspension lead 1e, it is difficult to manufacture the semiconductor device (QFP 6) in the following points. Found. That is, by adopting the small tab structure, the length of the suspension lead 1e is increased, and as a result, the suspension lead 1e is easily bent. As one of the countermeasures, the suspension lead 1e is widened to be rigid. It is possible to increase the value.

  On the other hand, in a semiconductor chip that requires a large number of power supply and GND pads for the purpose of improving electrical characteristics, the number of external terminals increases and the package size also increases. Therefore, the bar lead 1f is required to suppress an increase in package size. At this time, since the bar lead 1f is not pressed by the jig (clamper 11) during wire bonding, both ends thereof are fixed to the suspension lead 1e, thereby ensuring the stability of the bar lead 1f. .

  However, the lead frame 1 made of a metal such as a copper alloy is likely to expand due to the influence of heat. Therefore, both ends of the bar lead itself are expanded by an expansion action. At this time, the suspension lead 1e is used to improve rigidity. It is formed thick and obstructs the bar lead 1f from expanding due to expansion.

  As a result, the bar lead 1f is bent.

  Therefore, by forming the first slit 1g in the first connecting portion 1j of the bar lead 1f and the suspension lead 1e, the expanded bar lead 1f can be opened, and the bar lead 1f bends ( Deformation). That is, in manufacturing a multi-pin semiconductor device (QFP6) using the lead frame 1, it is important to form the first slit 1g in the first connecting portion 1j of the bar lead 1f and the suspension lead 1e.

  As described above, in the QFP 6 of the present embodiment, the bar lead 1f connected to the suspension lead 1e is arranged outside the tab 1c so as to surround the tab 1c, and the first connection portion 1j of the bar lead 1f to the suspension lead 1e. Since the first slit 1g is formed in the first slit 1g, the first slit 1g can mitigate the expansion / contraction action even if the expansion / contraction (thermal distortion) action due to the influence of heat acts on the bar lead 1f.

  Thereby, the bending (deformation) due to the expansion / contraction of the bar lead 1f can be reduced, and the occurrence of wire peeling can be prevented.

  Furthermore, if the suspension leads 1e are formed thick, not only the bar leads 1f are prevented from expanding due to expansion, but also the fluidity (flow velocity) of the resin flowing in the vicinity of the suspension leads 1e is reduced by the plurality of inner leads 1a. Since it is different from the area | region arrange | positioned, a void becomes easy to be formed in the inside of the sealing body 3 formed.

  However, by forming the first slit 1g as in the present embodiment, the thickness of the suspension lead 1e can be formed to be approximately the same as the thickness of the inner lead 1a. In addition, the fluidity (flow velocity) of the resin flowing in the suspension lead 1e can be made substantially uniform, and the generation of voids can be suppressed.

  Therefore, wire bonding to the bar lead 1f is also possible.

  As a result, a multi-pin QFP 6 using the lead frame 1 can be manufactured.

  Further, by manufacturing using the lead frame 1, the cost of the QFP 6 can be reduced.

  Further, since the bending due to the expansion / contraction of the bar lead 1f can be reduced, the occurrence of a wire short can be reduced. As a result, the reliability and quality of the QFP 6 can be improved.

  Next, a modification of the present embodiment shown in FIGS. 12 to 14 will be described.

  FIG. 14 shows a semiconductor device according to a modification of the present embodiment. As shown in FIG. 12, a QFP 13 having a large tab 1u structure in which the size of the chip mounting portion is larger than that of the semiconductor chip 2 is shown.

  In this QFP 13, the protruding portion 1w protruding from the semiconductor chip 2 of the large tab 1u is used as a common lead, and a wire 4 such as a power supply or GND is connected to the protruding portion 1w of the large tab 1u. Is common.

  That is, the QFP 13 of the modified example is obtained by removing the bar lead 1f in the QFP 6 shown in FIGS. 1 to 3 in order to completely suppress deformation due to thermal distortion of the bar lead 1f. A large tab (tab larger than the outer dimensions of the semiconductor chip 2) 1u is adopted, and the protruding portion 1w is used as a common lead, and a wire 4 such as a power source or GND is connected to the protruding portion 1w.

At that time, the adhesion between the lead frame 1 made of copper alloy and the sealing resin is lower than the adhesion between the semiconductor chip 2 made of silicon and the sealing resin, and the large tab 1u and the sealing resin Peeling easily occurs at the interface. Therefore, in the case of the large tab 1u, the contact area between the large tab 1u and the sealing resin becomes large, and the contact area between the semiconductor chip 2 and the sealing resin becomes lower than that of the small tab structure. Becomes more prominent. Therefore, as shown in FIGS. 12 and 13, a plurality of through holes 1v are formed in the large tab 1u, and the sealing resin is passed through the through holes 1v, so that the semiconductor chip 2 and the sealing resin are in contact with each other. By improving the region, even if the large tab 1u is employed, the problem of peeling that occurs at the interface between the sealing resin and the large tab 1u is suppressed.

  Moreover, although not shown in figure, in the large tab 1u, the area | region where the wire 4 is connected is given silver plating, and the plating film (plating layer) is formed. Since silver plating has relatively low adhesion to the mold resin, by not applying to the entire surface of the tab, the adhesion between the mold resin and the large tab 1u can be improved, and the reliability of the semiconductor device can be improved. The quality can be improved.

  In the modified QFP 13, since the bar lead 1f is not provided, it is possible to prevent the connecting portion (protruding portion 1w) of the second wire 4b for power supply or GND from being bent.

  Furthermore, as shown in FIG. 13, by connecting the tips of some inner leads 1a to the large tab 1u, the large tab 1u is fixed, and therefore it is possible to prevent the large tab 1u from rotating in the horizontal direction.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the above embodiment, the case where the number of the bar leads 1f connected to the inner leads 1a near the center of each of the four bar leads 1f is three is taken as an example. The number of bar leads 1f connected to the leads 1a is not limited to three, and may be other than three.

  In the above-described embodiment, the semiconductor chip 2 is sucked and held by the sucking collet 8. However, the present invention is not limited to this, and the outer dimensions of the semiconductor chip 2 are relative to the bar lead 1f. When the size is small, a collet in which the portion holding the semiconductor chip 2 has a pyramid shape may be used.

  In the above embodiment, the semiconductor device having the small tab structure has been described. However, the present invention is not limited to this. For example, if attention is paid only to suppressing the bending of the common lead (bar lead, bus bar lead) 1 f, the outer dimension (size) of the chip support surface 1 d of the semiconductor chip 2 as shown in FIG. A lead frame 1 including a chip mounting portion (tab, die pad) 1c larger than the back surface 2b may be used, and a semiconductor device as shown in FIGS. 17 and 18 may be used.

Further, in the above-described embodiment, in the suspension lead 1e, the slit (first slit 1g) is provided in a portion where the end of the common lead 1f is connected, so that the common lead 1f is bent due to the heat of the bonding stage 10. Although it has been described that suppression is not limited, it is not limited to this. For example, as shown in FIGS. 19, 20, and 21, a slit (through hole, hole) 1 s that is a means for relieving stress is formed in a part (central portion) of the common lead (bar lead, bus bar lead) 1 f. The provided lead frame 1 may be used. In this case, a region where the wire (second wire 4b) 4 can be connected in the common lead 1f is smaller than that in the above embodiment. However, when the number of pads (electrodes) 2a of the semiconductor chip 2 is smaller than that of the above-described embodiment, the wires 4 beside the slit (third slit 1s) as shown in FIGS. It can respond by connecting. In FIG. 24, the number of wires 4 connected to the pads 2a of the semiconductor chip 2 and the inner leads 1a is shown so that it can be easily confirmed that the wires 4 are connected to the side of the slit (third slit 1s). Omitted.

  In the embodiment, as indicated by a two-dot chain line L (imaginary line) in FIG. 6B, the slit (first slit 1g) is formed on the extended line of the common lead 1f in the suspension lead 1e. Although described, the present invention is not limited to this. When the heat of the bonding stage 10 in the wire bonding process is lower than the temperature used in the embodiment, the expansion of the common lead 1f is less likely to occur than in the embodiment. Therefore, for example, as shown in FIG. 25, the slit (first slit 1g) may be formed at a position farther from the tab 1c than the extension line L of the common lead 1f in the suspension lead 1e.

  In the embodiment and the modification, the slits are formed in the suspension leads 1e or the common leads 1f as means for relieving stress. However, the present invention is not limited to this. For example, as shown in FIG. 26, a part of the common lead 1f or both ends of the common lead may have a meandering shape as shown in FIG. Even in such a configuration, even if the common lead 1f expands due to the influence of heat, the meandering portion 1t contracts, so that the bending of the common lead 1f can be suppressed.

  Moreover, although the said embodiment demonstrated the case where the structure of this invention was applied to the QFP type | mold semiconductor device from which the some outer lead 1b protrudes from the side surface of the sealing body 3, and its manufacturing method, it is limited to this. For example, as shown in FIG. 28A, FIG. 28B, and FIG. 28C, the tab 1c and the common lead 1f are positioned inside the sealing body 3, and a plurality of leads ( Only the outer lead 1b) may be applied to a QFN (Quad Flat Non-leaded Package) 15 type semiconductor device exposed from the lower surface (mounting surface, back surface) of the sealing body 3.

  Further, although the case where the configuration of the present invention is applied to the QFP type semiconductor device in which a plurality of leads are arranged along the four sides of the sealing body 3 having a quadrangular planar shape and the manufacturing method thereof has been described, the present invention is not limited thereto. For example, as shown in FIGS. 29 (a), 29 (b), and 29 (c), the tab 1c and the common lead 1f are positioned inside the sealing body 3 and sealed. SOP (Small Outline Package) type 16 in which a plurality of leads are arranged along two sides of the body 3, or as shown in FIGS. 30 (a), 30 (b), and 30 (c) (Outline Non-leaded Package) It may be applied to a 17-type semiconductor device.

  Further, the present invention is not limited to this. As shown in FIGS. 31 (a), 31 (b), and 31 (c), the tab 1c, the common lead 1f, and a plurality of leads (outer lead 1b) are sealed. You may apply to the QFN (Quad Flat Non-leaded Package) 18 type semiconductor device exposed from the lower surface (mounting surface, back surface) of the stop body 3. FIG. Further, as shown in FIGS. 32 (a), 32 (b), and 32 (c), the tab 1c, the common lead 1f, and a plurality of leads (outer leads 1b) are connected to the lower surface (mounting surface, The present invention may be applied to a SON (Small Outline Non-leaded Package) 19 type semiconductor device exposed from the back surface.

  The present invention is suitable for an electronic device assembled by using a lead frame and its assembly.

It is a top view which shows an example of the structure of the semiconductor device of embodiment of this invention. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. It is sectional drawing which shows an example of the structure cut | disconnected along the BB line of FIG. FIG. 2 is a cross-sectional view showing an example of a manufacturing process until wire bonding is completed in the assembly of the semiconductor device shown in FIG. 1. FIG. 2 is a cross-sectional view showing an example of a manufacturing process after wire bonding in the assembly of the semiconductor device shown in FIG. 1. FIG. 2 is a partial plan view showing an example of the structure of a lead frame used for assembling the semiconductor device shown in FIG. 1. FIG. 6B is a partially enlarged plan view showing a part of a lead frame used for assembling the semiconductor device shown in FIG. 6A. FIG. 4 is a partial plan view showing an example of a structure of a second offset portion of a lead frame used for assembling the semiconductor device shown in FIG. 1. It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. FIG. 2 is a plan view showing an example of a clamp region at the time of wire bonding in the assembly of the semiconductor device shown in FIG. 1. It is sectional drawing which shows an example of the clamp structure at the time of wire bonding in the assembly of the semiconductor device shown in FIG. It is a partial top view which permeate | transmits and shows an example of the structure after the resin molding in the assembly of the semiconductor device shown in FIG. It is sectional drawing which shows the structure of the lead frame used for the assembly of the semiconductor device of the modification of embodiment of this invention. It is a fragmentary top view which permeate | transmits a sealing body and shows the structure after the resin molding in the assembly of the semiconductor device of the modification of embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device of the modification of embodiment of this invention. It is a fragmentary sectional view which shows an example of the structure at the time of the metal mold | die clamp by a metal mold | die at the time of using the lead frame without offset in embodiment of this invention. It is a fragmentary top view which shows an example of the structure of the lead frame used for the assembly of the semiconductor device which employ | adopted the large tab in embodiment of this invention. FIG. 17 is a partial plan view showing an example of a structure after resin molding in assembling a semiconductor device using the lead frame shown in FIG. 16 through a sealing body. FIG. 18 is a cross-sectional view illustrating an example of the structure of the semiconductor device illustrated in FIG. 17. It is a fragmentary top view which shows an example of the structure of the lead frame in which the slit was provided in the common lead in embodiment of this invention. It is sectional drawing which shows an example of the structure cut | disconnected along the AA of FIG. FIG. 20 is an enlarged partial plan view showing an example of a structure of a slit forming portion in the lead frame shown in FIG. 19. FIG. 20 is a partial plan view illustrating an example of a structure after resin molding in the assembly of the semiconductor device using the lead frame illustrated in FIG. 19 through the sealing body. It is sectional drawing which shows an example of the structure cut | disconnected along the AA of FIG. FIG. 23 is an enlarged partial plan view showing an example of a structure of a slit forming portion in the structure shown in FIG. 22. It is an enlarged partial top view which shows the structure of the modification of the means to relieve | moderate the stress to the common lead in embodiment of this invention. It is a fragmentary top view which shows the structure of the modification of the means to relieve | moderate the stress to the common lead in the lead frame of embodiment of this invention. It is a fragmentary top view which shows the structure of the modification of the means to relieve | moderate the stress to the common lead in the lead frame of embodiment of this invention. It is a figure which shows the structure of the semiconductor device (QFN) of the modification of embodiment of this invention, (a) is a top view, (b) is sectional drawing, (c) is a back view. It is a figure which shows the structure of the semiconductor device (SOP) of the modification of embodiment of this invention, (a) is a top view, (b) is sectional drawing, (c) is a back view. It is a figure which shows the structure of the semiconductor device (SON) of the modification of embodiment of this invention, (a) is a top view, (b) is sectional drawing, (c) is a back view. It is a figure which shows the structure of the semiconductor device (QFN) of the modification of embodiment of this invention, (a) is a top view, (b) is sectional drawing, (c) is a back view. It is a figure which shows the structure of the semiconductor device (SON) of the modification of embodiment of this invention, (a) is a top view, (b) is sectional drawing, (c) is a back view.

Explanation of symbols

1 Lead frame 1a Inner lead (lead)
1b Outer lead (lead)
1c Tab (chip mounting part)
1d Chip support surface 1e Suspended lead 1f Bar lead (common lead)
1f 'plating film (plating layer)
1g 1st slit 1h 1st inner lead 1i 2nd inner lead 1j 1st connection part 1m 1st offset part 1n 2nd slit 1p 2nd offset part 1q Tape material 1r 2nd connection part 1s 3rd slit 1t Serpentine part 1u Large Tab (chip mounting part)
1v Through hole 1w Protruding part (common lead)
2 Semiconductor chip 2a Main surface 2b Back surface 2c Pad (electrode)
DESCRIPTION OF SYMBOLS 3 Sealing body 4 Wire 4a 1st wire 4b 2nd wire 5 Silver paste 6 QFP (semiconductor device)
7 Potting Nozzle 8 Adsorption Collet 9 Capillary 10 Bonding Stage 10a Adsorption Hole 11 Clamper 11a Clamp Part 12 Exterior Plating 13 QFP (Semiconductor Device)
14 Mold Die 14a Upper Die 14b Cavity Surface 14c Lower Die 14d Cavity Surface 15 QFN (Semiconductor Device)
16 SOP (semiconductor device)
17 SON (semiconductor device)
18 QFN (semiconductor device)
19 SON (semiconductor device)

Claims (5)

A chip mounting portion;
A semiconductor chip mounted on the chip mounting portion, having a main surface, a first electrode formed on the main surface, a second electrode formed on the main surface, and a back surface opposite to the main surface; ,
A plurality of suspension leads for supporting the chip mounting portion;
In plan view, a plurality of common leads arranged around the chip mounting portion,
In a plan view, a plurality of leads arranged around the chip mounting portion;
A plurality of first wires that electrically connect the plurality of first electrodes and the plurality of common leads, respectively;
A plurality of second wires that respectively electrically connect the plurality of second electrodes and the plurality of leads;
A sealing member for sealing the semiconductor chip, before Symbol plurality of first wires and the plurality of second wires,
Including
The chip mounting portion, the plurality of suspension leads, the plurality of common leads, and the plurality of leads are made of a metal whose main component is copper,
Each of the plurality of common leads is disposed between adjacent suspension leads of the plurality of suspension leads in plan view,
Each of the plurality of common leads is disposed between the chip mounting portion and the plurality of leads in a plan view.
Each of the plurality of common leads is coupled to a first portion of each of the plurality of suspension leads,
A slit is formed in the first portion of each of the plurality of suspension leads ,
Each of the plurality of common leads is formed in a straight line,
The slit formed in the first portion of each of the plurality of suspension leads and not formed in each of the plurality of common leads is located on an extension line of each of the plurality of common leads. A semiconductor device. In claim 1 ,
The semiconductor device according to claim 1, wherein an outer dimension of the chip mounting portion in plan view is smaller than an outer dimension of the semiconductor chip in plan view. In claim 2 ,
Each of the plurality of suspension leads has a first offset portion formed in a second portion closer to the chip mounting portion than the first portion. In claim 2 ,
The first common lead of the plurality of common leads is connected to the first lead of the plurality of leads. In claim 4 ,
A second common lead of the plurality of common leads is not connected to the plurality of leads,
The semiconductor device, wherein the second common lead has a second offset portion.

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