JP5157587B2 - Manufacturing method of multilayer wiring board - Google Patents
Manufacturing method of multilayer wiring board Download PDFInfo
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- JP5157587B2 JP5157587B2 JP2008090233A JP2008090233A JP5157587B2 JP 5157587 B2 JP5157587 B2 JP 5157587B2 JP 2008090233 A JP2008090233 A JP 2008090233A JP 2008090233 A JP2008090233 A JP 2008090233A JP 5157587 B2 JP5157587 B2 JP 5157587B2
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- layer
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- wiring board
- multilayer wiring
- plating
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本発明は、特に基板厚が薄い多層配線基板として好適であり、熱履歴による残留応力が少なく、優れた低反り性を有し、優れた層間接続信頼性および生産性、コスト性に優れた多層配線基板の製造方法に関する。
The present invention is particularly suitable as a multilayer wiring board having a thin substrate thickness, has little residual stress due to thermal history, has excellent low warpage, and has excellent interlayer connection reliability, productivity, and cost. The present invention relates to a method for manufacturing a wiring board.
電子技術の進歩に伴い、電子情報端末の小型化、軽量化、高機能化がますます求められてきており、このため、多層配線基板においても、基板厚が薄い多層配線基板が望まれている。 As electronic technology advances, electronic information terminals are increasingly required to be smaller, lighter, and more functional. For this reason, a multilayer wiring board with a thin board thickness is also desired for multilayer wiring boards. .
従来、基板厚を薄くすると、剛性が低いため、熱履歴による残留応力により、反りの問題が発生し、実装不具合や信頼性の低下を引き起こす。 Conventionally, when the thickness of the substrate is reduced, the rigidity is low. Therefore, the problem of warpage occurs due to the residual stress due to the thermal history, causing a mounting failure and a decrease in reliability.
それを改善するために、スティフナーなどの補強板で矯正するなどの取り組みがなされてきたが、コスト高になるなどの問題があった。 In order to improve it, efforts such as correction with stiffeners or other reinforcing plates have been made, but there were problems such as high costs.
以下に参考文献を掲げる。
本発明は、このような点を鑑みて、特に多層配線基板の高密度化に対応した薄型の基板の際に、スティフナーを用いない場合において優れた低反り性を有し、さらには優れた層間接続信頼性および生産性、コスト性を有する多層配線基板を提供するものである。 In view of such a point, the present invention has excellent low warpage in the case where a stiffener is not used, particularly in the case of a thin substrate corresponding to high density of a multilayer wiring substrate, and further, an excellent interlayer A multilayer wiring board having connection reliability, productivity, and cost is provided.
上記課題を解決するために為された多層配線基板の製造方法の発明として、請求項１に係る発明は、基板上に半導体配置部と、配線層と、該半導体配置部を囲む金属めっき枠を有する多層配線基板の製造方法であって、基板上の導体層をエッチングして配線層及び金属めっき枠パターンを形成する工程と、配線層及び金属めっき枠パターン上に金属めっき層を積層する工程とを有する多層配線基板の製造方法である。
As an invention of a manufacturing method of a multilayer wiring board made to solve the above-mentioned problems, the invention according to claim 1 includes a semiconductor placement portion, a wiring layer, and a metal plating frame surrounding the semiconductor placement portion on the substrate. A method of manufacturing a multilayer wiring board having: a step of etching a conductor layer on the substrate to form a wiring layer and a metal plating frame pattern; and a step of laminating a metal plating layer on the wiring layer and the metal plating frame pattern; A method for manufacturing a multilayer wiring board having
また、請求項２に係る発明は、前記配線パターン及び金属めっき枠パターン上に金属めっき層を積層する工程において、配線パターン上の所定の部位にソルダーレジストを形成する工程を有することを特徴とする請求項１に記載の多層配線基板の製造方法である。The invention according to claim 2 is characterized in that in the step of laminating a metal plating layer on the wiring pattern and the metal plating frame pattern, a step of forming a solder resist at a predetermined portion on the wiring pattern is provided. A method for manufacturing a multilayer wiring board according to claim 1.
本発明の多層配線基板の製造方法によれば、多層配線基板表面に剛性を強化する金属めっき枠を形成することにより、高温時の熱履歴により発生した応力を、効果的に緩和させることができる。従って、加熱処理時の残留応力を少なくすることが可能となり、その結果、優れた低反り性を有する。また、金属めっき枠は、配線層形成工程において同時に形成することができる。以上から、優れた層間接続信頼性および生産性、コスト性に優れ、配線の高密度化に対応した多層配線基板を提供することができる。
According to the method for manufacturing a multilayer wiring board of the present invention, by forming a metal plating frame that reinforces rigidity on the surface of the multilayer wiring board, it is possible to effectively relieve stress generated due to thermal history at high temperatures. . Accordingly, it is possible to reduce the residual stress during the heat treatment, and as a result, it has excellent low warpage. Further, the metal plating frame can be formed at the same time in the wiring layer forming step. As described above, it is possible to provide a multilayer wiring board that is excellent in interlayer connection reliability, productivity, and cost, and that supports high density wiring.
図１は、本発明の多層配線基板の構造の一実施例を表す側断面の模式図である。
本発明の多層配線基板は、当該基板の最外層表面に、半導体配置部７を囲むように、金属めっき枠４が形成されている。半導体配置部には、配線層５が形成され、配線層には半導体と接続するバンプ等を含む。図２には半導体を図１の多層配線基板に実装した半導体パッケージの例を示した。図２の構成例では、バンプ１０を介してフリップチップ方式にて電気的に接続し、半導体と基板との間にアンダーフィル１１を充填している。このように基板に半導体チップを直接実装する場合、前述のように高温時の熱履歴により応力が生じる。特に、基板厚の薄い基板では、剛性が低いために反りが生じやすい。
FIG. 1 is a schematic side sectional view showing an embodiment of the structure of the multilayer wiring board of the present invention.
In the multilayer wiring board of the present invention, the metal plating frame 4 is formed on the outermost layer surface of the board so as to surround the semiconductor placement portion 7. A wiring layer 5 is formed in the semiconductor placement portion, and the wiring layer includes bumps and the like connected to the semiconductor. FIG. 2 shows an example of a semiconductor package in which a semiconductor is mounted on the multilayer wiring board of FIG. In the configuration example of FIG. 2, the underfill 11 is filled between the semiconductor and the substrate by being electrically connected by a flip chip method via the bumps 10. When the semiconductor chip is directly mounted on the substrate in this way, stress is generated due to the thermal history at a high temperature as described above. In particular, a substrate with a thin substrate is likely to warp due to low rigidity.
そこで本発明の多層配線基板では、半導体配置部と同一側の基板表面でその周囲に金属めっき枠４を配置する構成とすることで、上記課題を解決した。このような構成とすることにより、半導体を実装した際、金属めっき枠で半導体を囲むことになり、半導体周辺の基板の剛性が向上し、変形が抑制されるため、基板の反りを低減することができる。 Therefore, in the multilayer wiring board of the present invention, the metal plating frame 4 is arranged around the substrate surface on the same side as the semiconductor arrangement portion, thereby solving the above problem. By adopting such a configuration, when the semiconductor is mounted, the semiconductor is surrounded by a metal plating frame, the rigidity of the substrate around the semiconductor is improved, and deformation is suppressed, so that the warpage of the substrate is reduced. Can do.
金属めっき枠厚み８は、特に限定されるものではないが、厚みが薄くなると、剛性の効果が低減されることから、２μｍ以上が望ましい。 The metal plating frame thickness 8 is not particularly limited. However, when the thickness is reduced, the rigidity effect is reduced, so that the thickness is preferably 2 μm or more.
金属めっき枠４の幅は、特に限定されるものではないが、幅が狭くなると、剛性の効果が低減されることから、２ｍｍ以上が望ましい。 The width of the metal plating frame 4 is not particularly limited, but if the width is narrowed, the effect of rigidity is reduced, so that it is preferably 2 mm or more.
金属めっき枠４は、後述のように、一層又は複数の金属めっき層で構成されている。金属めっき枠の形状は、反りを低減させるために向上させるものであれば特に制限はなく、半導体の形状、配置等に合わせて任意に設計することが可能である。 The metal plating frame 4 is composed of one or more metal plating layers as described later. The shape of the metal plating frame is not particularly limited as long as it is improved in order to reduce warpage, and can be arbitrarily designed according to the shape, arrangement, etc. of the semiconductor.
金属めっき枠４の一層目のめっき層２は、その上層の二層目のめっき層３の下地層とすることができる。具体的にはニッケルめっきであることが好ましい。理由としては、上層に金めっきをする場合に下層の銅箔と合金を形成することを防止することができる点、一般的な方法で無電解めっきすることができる点が挙げられる。 The first plating layer 2 of the metal plating frame 4 can be used as a base layer for the second plating layer 3 that is the upper layer. Specifically, nickel plating is preferable. The reason is that when gold plating is performed on the upper layer, formation of an alloy with the lower layer copper foil can be prevented, and electroless plating can be performed by a general method.
二層目のめっき層３は、金めっき等を用いることにより、耐薬品性等の化学的特性を向上させることができる。また、膜厚を大きくすることにより、基板の剛性をあげて、さらに反りの低減を図ることもできる。二層よりもさらに多くの層を形成する場合には、耐薬品性のある金めっき層は最外層に形成することが好ましい。これ以外の積層構成としては、例えば、一層目に下地層として無電解銅めっき層を形成し、二層目に電解銅めっき層を形成しても良い。 The second plating layer 3 can improve chemical characteristics such as chemical resistance by using gold plating or the like. Further, by increasing the film thickness, it is possible to increase the rigidity of the substrate and further reduce the warpage. When forming more layers than two layers, it is preferable to form the chemical-resistant gold plating layer as the outermost layer. As a laminated structure other than this, for example, an electroless copper plating layer may be formed as an underlayer on the first layer, and an electrolytic copper plating layer may be formed on the second layer.
また、金属めっき層の下層に、銅箔等の導体層５からなる金属めっき枠パターン６が形成されていても良い。この場合は配線層についても導体層からなり、半導体と接続するためのバンプ等のソルダーレジストの開口部のみに金属めっき枠と同様、金属めっき層を形成された構成とすることができる。 Moreover, the metal plating frame pattern 6 which consists of conductor layers 5, such as copper foil, may be formed in the lower layer of a metal plating layer. In this case, the wiring layer is also made of a conductor layer, and a metal plating layer can be formed only in the opening of a solder resist such as a bump for connection to a semiconductor, like the metal plating frame.
多層配線基板１の厚みは、特に限定されるものではないが、基板が厚くなると、金属めっき枠による剛性の効果が低減されるため、５００μｍ以下が望ましい。 The thickness of the multilayer wiring board 1 is not particularly limited. However, when the board becomes thick, the effect of rigidity by the metal plating frame is reduced, so that it is preferably 500 μm or less.
次に、本発明の多層配線基板の製造方法について説明する。
本発明の多層配線基板の製造方法には、公知の製造プロセスを用いることができる。具体的には、サブトラクティブ法、アディティブ法、セミアディティブ法等である。いずれにしても、配線層の形成工程と同時に、金属めっき枠又は金属めっき枠パターンを形成することを特徴とする。
Next, the manufacturing method of the multilayer wiring board of this invention is demonstrated.
A well-known manufacturing process can be used for the manufacturing method of the multilayer wiring board of this invention. Specifically, a subtractive method, an additive method, a semi-additive method, and the like. In any case, the metal plating frame or the metal plating frame pattern is formed simultaneously with the wiring layer forming step.
サブトラクティブ法では、金属箔（銅箔）が有する絶縁層にスルーホール等を形成した後、エッチング等により、配線層および金属めっき枠パターンを形成する。次に、無電解めっき又は電解めっきにより金属めっき枠を形成する。配線層にめっき層を形成しない場合には、めっき工程の前に、配線層の所定の個所にソルダーレジストを被覆しても良い。以上の工程で配線層と、金属めっき枠を形成することができる。 In the subtractive method, a through hole or the like is formed in an insulating layer of a metal foil (copper foil), and then a wiring layer and a metal plating frame pattern are formed by etching or the like. Next, a metal plating frame is formed by electroless plating or electrolytic plating. When a plating layer is not formed on the wiring layer, a solder resist may be coated on a predetermined portion of the wiring layer before the plating step. The wiring layer and the metal plating frame can be formed by the above steps.
アディティブ法の例としては、配線層及び金属枠の領域以外にレジストパターンを形成し、次に無電解めっき工程で導体層を形成し、配線層及び金属めっき枠の一層目のめっき層を形成することができる。次に、無電解めっき又は電解めっきにより金属めっき枠の二層目のめっき層を形成することができる。配線層にめっき層を形成しない場合には、めっき工程の前に、配線層の所定の個所にソルダーレジストを被覆しても良い。以上の工程で配線層と、金属めっき枠を形成することができる。 As an example of the additive method, a resist pattern is formed in a region other than the wiring layer and the metal frame region, a conductor layer is then formed in an electroless plating process, and a first plating layer of the wiring layer and the metal plating frame is formed. be able to. Next, the second plating layer of the metal plating frame can be formed by electroless plating or electrolytic plating. When a plating layer is not formed on the wiring layer, a solder resist may be coated on a predetermined portion of the wiring layer before the plating step. The wiring layer and the metal plating frame can be formed by the above steps.
セミアディティブ法の例としては、無電解めっきにより下地層を形成した後、配線層及び金属枠の領域以外にレジストパターンを形成し、次に電解めっき工程により導体層を形成した後、レジストパターン及び配線層及び金属めっき枠パターンの領域以外の下地層を除去する。次に、無電解めっき又は電解めっきにより金属めっき枠を形成する。配線層にめっき層を形成しない場合には、めっき工程の前に、配線層の所定の個所にソルダーレジストを被覆しても良い。以上の工程で配線層と、金属めっき枠を形成することができる。 As an example of the semi-additive method, after forming an underlayer by electroless plating, a resist pattern is formed in a region other than the wiring layer and the metal frame region, and then a conductor layer is formed by an electrolytic plating process. The underlying layer other than the wiring layer and metal plating frame pattern regions is removed. Next, a metal plating frame is formed by electroless plating or electrolytic plating. When a plating layer is not formed on the wiring layer, a solder resist may be coated on a predetermined portion of the wiring layer before the plating step. The wiring layer and the metal plating frame can be formed by the above steps.
上記工程では、基本的に配線層と、金属めっき枠を同じ工程で形成していることから、その膜厚も同じものとなる。ここで金属めっき枠の膜厚を大きくする場合には、配線層を半導体と接続するバンプ等の所定の部位を除いてソルダーレジストで覆った後に、めっきすることにより、膜厚を大きくすることができる。めっきは無電解めっきおよび電解めっきいずれも可能である。 In the above process, since the wiring layer and the metal plating frame are basically formed in the same process, the film thickness is also the same. Here, when increasing the film thickness of the metal plating frame, it is possible to increase the film thickness by plating after covering the wiring layer with a solder resist except for a predetermined portion such as a bump connected to the semiconductor. it can. The plating can be either electroless plating or electrolytic plating.
本発明における多層配線基板の用途としては、特に限定されるものではないが、熱履歴による残留応力を低減できるため高信頼性を有することから、例えば、半導体搭載用、または半導体搭載用インターポーザー用途に最適である。
以下、実施例に基づき本発明をさらに具体的に説明する。
The use of the multilayer wiring board in the present invention is not particularly limited, but since it has high reliability because residual stress due to thermal history can be reduced, for example, for semiconductor mounting or for semiconductor mounting interposer Ideal for.
Hereinafter, the present invention will be described more specifically based on examples.
（実施例１）
両面に銅箔が設けられたガラス・エポキシ基板の所定箇所に、両面の導通をはかるためのスルーホール用貫通孔をドリルにより開口した。次に得られたガラス・エポキシ基板に無電解めっき法及び電解めっき法により導体層を形成した。ガラス・エポキシ基板の両面の銅層表面にドライフィルムレジストを貼り付け、露光、現像、エッチングにより配線を形成し、コア層を得た。
Example 1
Through-holes for through-holes were opened with a drill at predetermined locations on a glass / epoxy substrate having copper foils on both sides for conducting both sides. Next, a conductor layer was formed on the obtained glass / epoxy substrate by electroless plating and electrolytic plating. A dry film resist was applied to the surfaces of the copper layers on both sides of the glass / epoxy substrate, and wiring was formed by exposure, development, and etching to obtain a core layer.
次に、得られた基板にプリプレグと銅箔を組み合わせて積層し、積層された基板に、層間導通をはかるため、レーザを用いて表層と内層とを接続するビアを開け、得られたガラス・エポキシ基板に無電解めっき法、電解めっき法により導体層を形成した。更に、上記積層工程を同様に再度、繰り返し、積層された最外層の配線部の上に、ドライフィルムレジストを貼り付け、前記同様に露光、現像、エッチングにより配線層と、半導体チップ搭載側には金属めっき枠パターンを形成した。 Next, the prepreg and the copper foil were laminated on the obtained substrate, and the vias connecting the surface layer and the inner layer were opened using a laser in order to achieve interlayer conduction in the laminated substrate. A conductor layer was formed on the epoxy substrate by electroless plating or electrolytic plating. Further, the above laminating process is repeated again in the same manner, and a dry film resist is pasted on the laminated wiring portion of the outermost layer, and the wiring layer and the semiconductor chip mounting side are exposed, developed and etched in the same manner as described above. A metal plating frame pattern was formed.
その後、実装に必要な開口部及び金属めっき枠パターンを除き、露出している配線パターン上にソルダーレジストを形成した。そして、その開口部と金属めっき枠パターンに無電解めっき法により厚み４ｕｍのニッケルめっき層を形成し、次いで無電解めっき法により金めっき層を形成し、図１のように半導体チップを搭載可能な基板厚２６０ｕｍの多層配線基板を得た。 Thereafter, a solder resist was formed on the exposed wiring pattern except for the opening and the metal plating frame pattern necessary for mounting. Then, a nickel plating layer having a thickness of 4 μm is formed on the opening and the metal plating frame pattern by an electroless plating method, and then a gold plating layer is formed by an electroless plating method, and a semiconductor chip can be mounted as shown in FIG. A multilayer wiring board having a substrate thickness of 260 μm was obtained.
（実施例２）
前記実施例１の製造方法は同様にするが、コア層を厚くして、基板厚３２０ｕｍの多層配線基板を得た。
(Example 2)
Although the manufacturing method of Example 1 was the same, the core layer was thickened to obtain a multilayer wiring board having a substrate thickness of 320 um.
（実施例３）
前記実施例１の製造方法は同様にするが、コア層を厚くして、基板厚３８０ｕｍの多層配線基板を得た。
(Example 3)
Although the manufacturing method of Example 1 was the same, the core layer was thickened to obtain a multilayer wiring board having a substrate thickness of 380 um.
（実施例４）
前記実施例１の製造方法は同様にするが、コア層を厚くして、基板厚４４０ｕｍの多層配線基板を得た。
Example 4
Although the manufacturing method of Example 1 was the same, the core layer was thickened to obtain a multilayer wiring board having a substrate thickness of 440 μm.
（比較例１）
前記実施例１の製造方法において、金属めっき枠パターンを形成する工程と金属めっき枠パターン上に金属めっきする工程を含んでないこと以外は実施例１と同様の工程で、基板厚２６０ｕｍの多層配線基板を得た。
(Comparative Example 1)
In the manufacturing method of the first embodiment, a multilayer wiring board having a substrate thickness of 260 um is the same as the first embodiment except that the process of forming the metal plating frame pattern and the step of metal plating on the metal plating frame pattern are not included. Got.
（比較例２）
コア層を厚くしたこと以外は前記比較例１と同様の工程で基板厚３２０ｕｍの多層配線基板を得た。
(Comparative Example 2)
A multilayer wiring board having a substrate thickness of 320 um was obtained by the same process as in Comparative Example 1 except that the core layer was thickened.
（比較例３）
コア層を厚くしたこと以外は前記比較例１と同様の工程で基板厚３８０ｕｍの多層配線基板を得た。
(Comparative Example 3)
A multilayer wiring board having a substrate thickness of 380 um was obtained by the same process as in Comparative Example 1 except that the core layer was thickened.
（比較例４）
コア層を厚くしたこと以外は前記比較例１と同様の工程で基板厚４４０ｕｍの多層配線基板を得た。
(Comparative Example 4)
A multilayer wiring board having a substrate thickness of 440 um was obtained in the same process as Comparative Example 1 except that the core layer was thickened.
（反り評価）
実施例１〜４および比較例１〜４によって得られた多層配線基板に対して、実施例１〜４および比較例１〜４によって得られた多層配線基板に対して、８５℃、８５％の環境下、１６８時間吸湿前処理を行った後、２６０℃を１０秒以上の条件で３回、リフロー炉に投入し、反り量を測定し表１に記載した。尚、表１に記載の反り量は実施例１〜４および比較例１〜４でそれぞれ５個片用意して、５個片の反り量の平均値とした。
(Warp evaluation)
With respect to the multilayer wiring board obtained by Examples 1-4 and Comparative Examples 1-4 with respect to the multilayer wiring board obtained by Examples 1-4 and Comparative Examples 1-4, 85 degreeC, 85% Under the environment, after moisture absorption pretreatment for 168 hours, 260 ° C. was put in a reflow furnace three times under the condition of 10 seconds or more, and the amount of warpage was measured and listed in Table 1. In addition, the amount of curvature described in Table 1 was prepared in each of Examples 1 to 4 and Comparative Examples 1 to 4, and the average value of the amount of warpage of the five pieces was used.
（ビア接続信頼性評価）
実施例１〜４および比較例１〜４でそれぞれ５個片用意して、気漕冷熱衝撃試験を以下の条件、試験条件１：−５５℃〜１２５℃、各３０分、１０００サイクルで行った。試験終了後、５個片全てで導体回路が断線しなかった場合は○、５個片中、１つでも断線した場合は×として表１に記載した。
(Via connection reliability evaluation)
Five pieces were prepared for each of Examples 1 to 4 and Comparative Examples 1 to 4, and the air-cooling thermal shock test was conducted under the following conditions and test conditions 1: -55 ° C to 125 ° C, 30 minutes each, 1000 cycles. . When the conductor circuit was not disconnected in all five pieces after the test was completed, the results are shown in Table 1 as ◯ when one of the five pieces was disconnected.
表１から明らかなように、実施例１〜４の反り量は比較例１〜４と比較して、反りが低減され、またビア接続信頼性試験後に実施例１〜４では導体回路が断線していないため、実施例１〜４では目的の諸特性、即ち、低反り性、および高い層間の接続信頼性を示した。 As is apparent from Table 1, the warpage amount of Examples 1 to 4 is less than that of Comparative Examples 1 to 4, and the conductor circuit is disconnected in Examples 1 to 4 after the via connection reliability test. Therefore, in Examples 1 to 4, target characteristics, that is, low warpage and high connection reliability between layers were shown.
以上の結果より、本発明の多層配線基板の製造方法は、熱履歴による残留応力が少なく、優れた低反り性を有し、および優れた層間接続信頼性、かつ、生産性およびコスト性に優れ、配線の高密度化に対応した多層配線基板を提供することが確認された。 From the above results, the manufacturing method of the multilayer wiring board of the present invention has little residual stress due to thermal history, excellent low warpage, excellent interlayer connection reliability, and excellent productivity and cost. It was confirmed that a multilayer wiring board corresponding to high density wiring was provided.
１…多層配線基板
２…一層目のめっき層（ニッケルめっき）
３…二層目のめっき層（金めっき）
４…金属めっき枠
５…配線層
６…金属めっき枠パターン
７…半導体配置部
８…金属めっき枠厚み
９…半導体
１０…バンプ
１１…アンダーフィル
１２…ソルダーレジスト
1 ... multilayer wiring board 2 ... first plating layer (nickel plating)
3 ... Second plating layer (gold plating)
DESCRIPTION OF SYMBOLS 4 ... Metal plating frame 5 ... Wiring layer 6 ... Metal plating frame pattern 7 ... Semiconductor arrangement | positioning part 8 ... Metal plating frame thickness 9 ... Semiconductor 10 ... Bump 11 ... Underfill 12 ... Solder resist
Claims (2)
2. The multilayer wiring board according to claim 1 , wherein in the step of laminating the metal plating layer on the wiring layer and the metal plating frame pattern, a step of forming a solder resist at a predetermined portion on the wiring layer is provided. Production method.
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| JP5157587B2 true JP5157587B2 (en) | 2013-03-06 |
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| JP2000299399A (en) * | 1999-04-12 | 2000-10-24 | Sony Corp | Semiconductor device |
| JP4672290B2 (en) * | 2004-06-16 | 2011-04-20 | 富士通株式会社 | Circuit board, package board manufacturing method, and package board |
| JP4452222B2 (en) * | 2005-09-07 | 2010-04-21 | 新光電気工業株式会社 | Multilayer wiring board and manufacturing method thereof |
| JP5144222B2 (en) * | 2007-11-14 | 2013-02-13 | 新光電気工業株式会社 | Wiring board and manufacturing method thereof |
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