JP5164136B2 - Power semiconductor module design method - Google Patents

Description

  The present invention relates to a method for designing a power semiconductor module, and in particular, in a power semiconductor module used in a power converter for driving an electric device such as a motor, it is possible to suppress current oscillation (oscillation) at turn-off. Relates to the design method

  A power semiconductor module using a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) has been increased in capacity. As the capacity increases, a plurality of power semiconductor chips (power semiconductor elements) are connected in parallel inside the power semiconductor module. For this reason, there are a plurality of resonance loops formed by the connection for connecting to a circuit outside the module and the capacitance component of the power semiconductor chip inside the package of the power semiconductor module.

  In addition, since power semiconductor chips of various withstand voltage classes (for example, 600 V to 6500 V) are used for the power semiconductor module, the size of the capacity component of the power semiconductor chip may be different for each power semiconductor module. For this reason, the resonance frequency of a power semiconductor module exists more complicatedly. It has been confirmed that oscillation occurs when the resonance frequency matches the characteristics of a power semiconductor element such as an IGBT chip. For this reason, it is difficult to increase the capacity of the power semiconductor module or to reduce noise.

  This oscillation is often observed during the IGBT turn-off period. The oscillation phenomenon is more important with respect to EMC (Electro-Magnetic Compatibility). It has been reported that this oscillation must be avoided because it has a negative impact on EMC.

  In order to avoid oscillation, it is necessary to specify a resonance loop. However, it is difficult to specify (estimate) a resonance loop in a power semiconductor module having a complicated three-dimensional structure. For this reason, conventionally, a prototype of a power semiconductor module is evaluated, and the evaluation result is fed back to the design to depend on a method for avoiding oscillation. For this reason, it has been difficult to improve design efficiency and reduce costs.

Even if the resonance loop can be specified, a method for suppressing the oscillation is required separately. As a method for this purpose, a method of inserting a resistance element or a high-frequency loss element in a resonance loop has been proposed. For example, Japanese Patent Laid-Open No. 4-65866 (Patent Document 1) discloses a technique using a resistance element. Japanese Patent Laying-Open No. 2001-185679 (Patent Document 2) discloses a technique using a ferrite core as a high-frequency loss element.
JP-A-4-65866 JP 2001-185679 A

  As described above, in order to avoid oscillation of the power semiconductor module, evaluation by trial manufacture is necessary, and thus there are problems in terms of design efficiency and cost. In addition, when the method of inserting a high-frequency loss element in the resonance loop is applied, the number of components and the loss of the power semiconductor module are increased, so that the cost, the loss, and the size can be reduced. There are challenges.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a power semiconductor module design method capable of avoiding oscillation and reducing noise and size.

  In summary, the present invention provides a method for designing a power semiconductor module including one or more power semiconductor elements having negative resistance characteristics within an operating frequency range, and performs device simulation of the one or more power semiconductor elements Calculating a negative resistance region, creating an equivalent circuit of the power semiconductor module, calculating a resonance frequency of the equivalent circuit, and the resonance frequency is outside the negative resistance region. Determining whether or not.

  According to the present invention, the oscillation phenomenon due to the negative resistance characteristic of the power semiconductor element mounted on the power semiconductor module can be avoided, so that the noise of the semiconductor module can be reduced. In addition, according to the present invention, since the oscillation phenomenon can be avoided without increasing the number of parts, the semiconductor module can be downsized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated.

  First, the configuration of the power semiconductor module will be described with reference to the drawings. In order to show the effect of the embodiment of the present invention in an easy-to-understand manner, a power semiconductor module having a configuration in which a high-frequency loss element is inserted in a resonance loop will be described below.

  FIG. 1 is a schematic side view of a power semiconductor module in which a high-frequency loss element is inserted in a resonance loop. FIG. 2 is a schematic top view of a part of the power semiconductor module shown in FIG.

  Referring to FIGS. 1 and 2, power semiconductor module 100 is used for a power conversion device (an inverter or the like) that drives an electric device such as a motor. The power semiconductor module 100 includes a base plate 1, an insulating metallized substrate 2, an IGBT chip 3 </ b> A, a reflux diode chip 3 </ b> B, aluminum wires 4, 12 and 13, and a main electrode terminal 5.

  A material such as Cu, AlSiC, or Cu—Mo is used for the base plate 1. The surface of the base plate 1 is plated with Ni, and a resist is applied to the surface side (side on which the insulating metallized substrate 2 is mounted). The insulating metallized substrate 2 is made of a ceramic substrate and Al (or Cu) patterns mounted on both sides thereof. The number of insulating metallized substrates 2 is determined according to the scale of the module, for example, a plurality of sheets are prepared.

  The IGBT chip 3A and the reflux diode chip 3B are joined (soldered) on the insulating metallized substrate 2, and the insulating metallized substrate 2 is joined to the base plate 1. The aluminum wire 4 connects the emitter of the IGBT chip 3A and the anode of the reflux diode chip 3B. The aluminum wire 12 is a gate wire connected to the gate of the IGBT chip 3A. The aluminum wire 13 is an emitter sense wire connected to the emitter of the IGBT chip 3A. The main electrode terminal 5 is a terminal through which a main current flows with an external circuit. The main electrode terminal 5 is made of a Cu thin plate having a Ni plating on its surface, and is joined to a pattern on the insulating metallized substrate 2.

  The power semiconductor module 100 further includes a control circuit board 6, a case 7, a connection pin 8, a gate relay terminal 9, a gate balance resistor 10, high frequency loss elements 11 and 15, and an emitter balance resistor 14. . The control circuit board 6 is composed of a multilayer printed board, and is connected to the gate wiring pattern connected to the gate electrode of the IGBT chip 3A to control the gate voltage of the IGBT chip 3A, and to the emitter electrode and the collector electrode of the IGBT chip 3A, respectively. An emitter wiring pattern and a collector wiring pattern are formed. Each wiring is configured to be joined to a pattern on the insulating metallized substrate 2 via a connection pin (terminal) 8, a gate relay terminal 9, and an emitter relay terminal. The case 7 (not shown in FIG. 2) is attached to the base plate 1 with screws and silicone rubber.

  The gate balance resistor 10 is provided corresponding to each IGBT chip 3A. The high-frequency loss element 11 is formed of, for example, a ferrite core and is inserted into the gate of the IGBT chip 3A. The emitter balance resistor 14 is provided corresponding to each IGBT chip 3A. The high-frequency loss element 15 is formed of, for example, a ferrite core and is inserted into the emitter of the IGBT chip 3A.

  In the inverter on which the power semiconductor module 100 is mounted, the power semiconductor module 100 operates in accordance with a signal from the control circuit. Therefore, the power semiconductor module 100 is required to operate normally without malfunction according to the command of the signal. However, current oscillation may occur when the IGBT chip 3A is turned off. As a method for preventing this problem, as shown in FIG. 2, for example, a method of inserting a gate balance resistor or a high-frequency loss element into each gate wiring of a plurality of IGBT chips connected in parallel is used.

  However, the insertion of the gate balance resistor in this case leads to a decrease in switching speed, resulting in an increase in switching loss. In addition, oscillation cannot be suppressed unless the high-frequency current flows through a path that passes through the gate balance resistor or the high-frequency loss element (ferrite core). Furthermore, in the conventional technology, it is difficult to avoid oscillation by predicting this path before making a prototype of the power semiconductor module.

  The inventor relates to such an oscillation phenomenon. There are two cases of (1) oscillation that occurs when current flows through the gate wiring, and (2) oscillation that occurs when oscillation current flows through the main circuit collector-emitter wiring. Confirmed to do. In the case of (2), as disclosed in Japanese Patent Laid-Open No. 2001-185679, in the module type semiconductor device, the collector side of the IGBT element is soldered to the pattern on the insulating substrate, and the emitter is wired by wire bonding. Therefore, it is extremely difficult to insert a high-frequency loss element between the collector and emitter wiring.

  Here, regarding the generation mechanism of electromagnetic waves generated when the power semiconductor module is turned off, “Plasma extraction transit time oscillations in bipolar power devices” (Bernd Gutsmann et al., Solid-State Electronics 46 (2002) p.133-138). )It is described in. The outline will be described below with reference to FIG.

As shown in FIG. 3, when the IGBT chip 3 </ b> A is turned off, a space charge layer (depletion layer) 21 having a thickness (W) depending on the voltage applied to the collector is formed in the n ⁻ layer 20.

When the gate signal of the IGBT is turned on and a current flows from the collector to the emitter, holes are injected from the p ⁺ layer 24 to the n ⁻ layer 20. When the gate signal is turned off, holes are not injected from the p ⁺ layer 24 into the n ⁻ layer 20, but holes remain in the n ⁻ layer 20. Next, when the collector-emitter voltage rises, holes remaining in the n ⁻ layer 20 appear at the emitter terminal. This phenomenon corresponds to the collector current flowing out again as the collector-emitter voltage increases. This current is the tail current of the IGBT element.

  Holes 25 travel in space charge layer 21 during a tail period in which a tail current is generated. At this time, the IGBT chip 3A operates as a negative resistance. The operating frequency of the IGBT chip 3 </ b> A when operating as a negative resistance is the hole travel time obtained by integrating the injection delay time and the reciprocal of the drift velocity of the holes 25 by the thickness (W) of the space charge layer 21. And the inverse of the value is obtained. The power semiconductor module operates as a negative resistance oscillator when the calculated frequency matches the parallel resonant frequency of the resonant circuit formed by the wiring in the power semiconductor module.

  The inventor applies device simulation to this phenomenon, so that the operating frequency region of the IGBT element when negative resistance occurs (hereinafter referred to as “negative resistance region”) is a delay in injection of holes from the back side of the chip. Confirmed that it depends on time. Furthermore, the inventor has confirmed that in this region, the hole injection delay time is in the range from 1/2 wavelength delay to no delay time.

  FIG. 4 is a diagram showing an analysis result of the negative resistance when the collector-emitter voltage Vce is 1000 V to 2250 V in the IGBT chip 3A. From the results shown in FIG. 4, the frequency range of the negative resistance is estimated to be in the range of 40 MHz to 120 MHz.

  Furthermore, in order to confirm the validity of the negative resistance region, the inventor has demonstrated a negative resistance oscillator by device simulation. The operation of the IGBT during the tail period is equal to the operation of the thyristor. In consideration of calculation load, a model in which the IGBT was replaced with a thyristor was used. The parallel resonance frequency is formed by the capacitance of the thyristor and the inductance of the circuit.

  FIG. 5 is a diagram illustrating a result of analyzing the IGBT element by a simulator under a condition in which the IGBT element oscillates. For the device simulator, Medici (software from Synopsys) was used. Further, as oscillation conditions, the collector voltage was 1500 V and the resonance frequency was 80 MHz. FIG. 5 shows that oscillation is superimposed on the collector-emitter voltage Vce and the collector current Ic after the IGBT element is turned off.

  Next, as shown in FIG. 6, the inventor has a dependency relationship between the negative resistance region and the resonance frequency, and the oscillation at turn-off can be avoided by setting the parallel resonance frequency outside the negative resistance region. It was confirmed. In FIG. 6, the symbol “◯” indicates that oscillation has occurred, and the symbol “×” indicates that oscillation has not occurred. FIG. 6 shows that oscillation occurs when the resonance frequency is in the negative resistance region (ie, between 1/2 wavelength delay and no delay time), and oscillation occurs when the resonance frequency is outside the negative resistance region. Indicates that this has not occurred.

  Based on the principle described above, as a method for avoiding oscillation, (1) the resonance frequency of the power semiconductor module is removed from the negative resistance region of the IGBT chip, and (2) a resistance element or a high-frequency loss element in the resonance loop. There are two possible ways to insert However, (2) may be difficult to realize due to the structure of the power semiconductor module. Therefore, (1) is adopted in this embodiment.

[Embodiment 1]
FIG. 7 is a diagram showing a configuration example of a computer that executes a method for designing a power semiconductor module according to the embodiment of the present invention. With reference to FIG. 7, a mouse 114, a keyboard 116, and a display 118 are connected to a computer 150.

  The computer 150 is connected to the bus 120, a CPU (Central Processing Unit) 102, a ROM (Read Only Memory) 104 storing a program sent to the operating system, and the program to be executed And a RAM (Random Access Memory) 106 for storing data during program execution, and a hard disk (HDD) 108. The hard disk (HDD) 108 stores software (device simulator, electromagnetic field analysis software, etc.) for executing this design method.

  FIG. 8 is a flowchart illustrating a method for designing a power semiconductor module according to the first embodiment of the present invention. In the first embodiment, the resonance frequency of the power semiconductor module on which one power semiconductor chip is mounted is extracted, and oscillation is avoided by obtaining the relationship between the resonance frequency and the negative resistance region of the power semiconductor chip.

  Referring to FIG. 8, the negative resistance region and the parasitic capacitance component of the power semiconductor chip are extracted by the processes of steps S1 to S3. The parasitic impedances (inductance component L, capacitance component C, and resistance component R) of the package (indicated as “PKG” in FIG. 8) on which the power semiconductor chip is mounted are extracted by the processes in steps S11 to S13.

  In step S1, the chip structure of the power semiconductor element is determined. In step S2, a negative resistance region of the power semiconductor chip is calculated by executing device simulation.

  Step S2 includes steps S2A to S2C. In step S2A, the computer executes device simulation of the power semiconductor chip using a device simulator such as the above-mentioned Medici. In step S2B, the hole drift velocity distribution is extracted by simulation. As shown in Expression (1), the frequency f in the negative resistance region of the power semiconductor element depends on the time for which holes travel in the space charge layer and the injection delay time during the turn-off period of the power semiconductor chip.

1 / f = (injection delay time) + (hole travel time) (1)
The injection delay time is reported to be 1/2 wavelength to no delay time. The power semiconductor chip becomes a negative resistance in that region. In step S2C, the negative resistance region of the power semiconductor chip is calculated based on this relationship. However, the negative resistance alone does not oscillate, and a parallel resonance circuit that amplifies the signal is required (see FIG. 6).

  If the resonant frequency of the parallel resonant circuit exists in the negative resistance region, the power semiconductor module oscillates. Therefore, in step S3, the parasitic capacitance component of the power semiconductor element is extracted from the simulation result.

  In step S11, the structure of the power semiconductor module package is determined. The “package structure” specifically includes, for example, the structure of a base plate, an aluminum wire or an insulating metallized substrate, and the structure of a main electrode for connecting a power semiconductor chip to external wiring.

  In step S12, an electromagnetic field simulation using electromagnetic field analysis software (for example, Q3D Extractor manufactured by Ansoft) is executed on the package structure obtained in step S11. In step S13, the impedance of the power semiconductor module including the main electrode terminal, the wire, and the insulating metallized substrate is extracted by the simulation in step S12. However, since the resistance component and the inductance component have frequency dependency, when extracting the LCR matrix in the electromagnetic field analysis, the matrix is extracted after correcting the frequency according to the negative resistance region.

  In step S4, an equivalent circuit model is created using the parasitic capacitance component of the power semiconductor chip obtained in step S3 and the parasitic impedance (LCR matrix) obtained in step S13. Next, in step S5, a parallel resonance frequency is calculated from this equivalent circuit model. Subsequently, in step S6, it is determined whether or not the parallel resonance frequency exists outside the negative resistance region. The determination that the parallel resonance frequency exists outside the negative resistance region in step S6 means that the design of the power semiconductor module is appropriate (OK), that is, current oscillation at the time of turning off the IGBT element can be avoided. To do.

  On the other hand, when it is determined in step S6 that the parallel resonance frequency exists inside the negative resistance region, the design of the power semiconductor module is not appropriate (NG), that is, current oscillation occurs when the IGBT element is turned off. means.

  When the process of step S6 ends, the entire process ends. For example, the designer ends design of the power semiconductor module or performs redesign based on the determination result in step S6. If there is a parallel resonance frequency inside the negative resistance region in step S6, for example, the computer automatically verifies (resets) the package structure to change the equivalent circuit model, and the step You may perform the process of S5 and S6 again.

  According to the first embodiment, since it is possible to predict the presence or absence of oscillation on the simulation, it is not necessary to make a prototype. Therefore, the design efficiency can be improved. Further, since oscillation can be avoided, the noise of the power semiconductor module can be reduced.

  Furthermore, since a high frequency loss element can be made unnecessary, it is not necessary to secure an area on the substrate for mounting the high frequency loss element on the substrate. As a result, the power semiconductor module can be reduced in size and cost.

[Embodiment 2]
In the first embodiment, the number of power semiconductor chips is single. In the second embodiment, it is possible to avoid oscillation by extracting the resonance frequency in a power semiconductor module on which a plurality of power semiconductor chips are mounted and obtaining the relationship between the resonance frequency and the negative resistance region of the power semiconductor chip. To.

  The configuration of the computer for executing the design method according to the second embodiment is the same as that shown in FIG. The flowchart showing the design method according to the second embodiment is basically the same as the flowchart of FIG.

  In a power semiconductor module on which a plurality of power semiconductor chips are mounted, a main electrode terminal (main electrode terminal 5 shown in FIG. 2) for connecting the mounted chip to external wiring, an aluminum wire (aluminum wire 4 shown in FIG. 2). , 12, 13) and the impedance of the insulating substrate (insulating metallized substrate 2 shown in FIG. 2) exist in a complicated manner, so that a large number of resonance frequencies exist. For this reason, since oscillation is more likely to occur than in a power semiconductor module on which a single power semiconductor chip is mounted, it is not easy to increase the capacity. Furthermore, when oscillation occurs in a path that passes between a plurality of power semiconductor chips, a balance resistor (the gate balance resistor 10 and the emitter balance resistor 14 shown in FIG. 2) is required. To increase. As a result, it is difficult to reduce the loss.

  According to the second embodiment, the parallel resonance frequency can be changed on the simulation by appropriately changing the equivalent circuit model. Therefore, oscillation of the power semiconductor module can be avoided without inserting a balance resistor. This makes it possible to reduce the loss.

  Further, as in the first embodiment, it is not necessary to secure an area necessary for mounting the balance resistor on the substrate, so that the power semiconductor module can be reduced in size and cost. Furthermore, according to the second embodiment, since the resonance frequency can be changed by simulation, it is not necessary to insert a high-frequency loss element between the collector main electrode and the emitter main electrode. This eliminates the need for a high-frequency loss element for preventing oscillation even when the structure of the power semiconductor module is complicated. Therefore, the power semiconductor module can be reduced in size and cost.

  In the present embodiment, the power semiconductor element is an IGBT element and a diode. However, in a power semiconductor module equipped with a power semiconductor element having negative resistance characteristics in a certain operating frequency range, the parallel resonant frequency of the equivalent circuit composed of the capacitance component of the power semiconductor element and the parasitic impedance of the package is the power semiconductor element. If it is within the negative resistance region, oscillation may occur. Oscillation can be avoided by applying the present invention to the design of such a power semiconductor module. Therefore, the power semiconductor element is not limited to the IGBT or the diode, and may be another element. For example, as another power semiconductor element, a thyristor which is a kind of semiconductor switch element can be cited.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a schematic side view of the power semiconductor module in which the high frequency loss element was inserted in the resonance loop. It is a schematic top view in a part of the power semiconductor module shown in FIG. It is a figure explaining the phenomenon which arises at the time of turn-off of an IGBT element. It is a figure which shows the analysis result of the negative resistance in collector chip | tip emitter voltage Vce in 1000V to 2250V in IGBT chip | tip 3A. It is a figure which shows the result of having analyzed the IGBT element with the simulator on the conditions which the IGBT element is oscillating. It is a figure which shows the relationship between a negative resistance area | region and a resonant frequency. It is a figure which shows the structural example of the computer which performs the design method of the power semiconductor module according to Embodiment 1 of this invention. It is a flowchart explaining the design method of the power semiconductor module of Embodiment 1 of this invention.

Explanation of symbols

1 Base plate, 2 Insulated metallized substrate, 3A IGBT chip, 3B Reflux diode chip, 4, 12, 13 Aluminum wire, 5 Main electrode terminal, 6 Control circuit board, 7 Case, 8 Connection pin, 9 Gate relay terminal, 10 Gate Balance resistor, 11, 15 High frequency loss element, 14 Emitter balance resistor, 20 n ⁻ layer, 21 Space charge layer, 24 p ⁺ layer, 25 hole, 100 power semiconductor module, 102 CPU, 104 ROM, 106 RAM, 108 HDD , 114 mouse, 116 keyboard, 118 display, 120 bus, 150 computer.

Claims (2)

A method of designing a power semiconductor module including one or more IGBT elements having negative resistance characteristics within an operating frequency range,
By performing a device simulation of the one or more of the IGBT element, a step of calculating a negative resistance region of said one or more of the IGBT element,
Creating an equivalent circuit of the power semiconductor module;
Calculating a resonance frequency of the equivalent circuit;
Determining whether the resonance frequency exists outside the negative resistance region ,
In the step of calculating the negative resistance region, a hole drift velocity distribution of the IGBT element is extracted, and a reciprocal of a sum of a hole injection delay time and a hole travel time is used to calculate the negative resistance region in the negative resistance region. A method for designing a power semiconductor module that calculates a frequency . The power semiconductor module design method according to claim 1, wherein the power semiconductor module further includes a free-wheeling diode provided corresponding to the IGBT element .

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