JP5166148B2 - ESD protection circuit and semiconductor device - Google Patents

Description

  The present invention relates to an ESD protection circuit and a semiconductor device.

  Field effect transistors in semiconductor integrated circuits have been scaled as their performance has increased, but in recent years, the thickness of the gate insulating film has been reduced to nearly 1 nm in terms of silicon dioxide. Absent.

  When the gate insulating film is thinned, the electrical breakdown voltage is significantly reduced depending on the film thickness. In a semiconductor device including a field effect transistor having such a thin gate insulating film, when static electricity of a machine or a human enters the semiconductor device during manufacturing or use, a high voltage is applied to the gate insulating film. It can be destroyed. Such a phenomenon is called ESD (Electro Static Discharge) destruction.

  Thus, many semiconductor devices have an ESD protection circuit for preventing an external surge current from entering to prevent the gate insulating film from being destroyed by ESD (for example, see Patent Document 1).

  In the ESD protection circuit disclosed in Patent Document 1, the drain of the internal circuit is not directly connected to the external GND terminal via an inverter between the external GND terminal and the drain of the internal circuit. Even when the gate input is to be set to the GND level, it is possible to prevent current from flowing from the drain of the P-type transistor to VDD through the well, and to allow electrons to flow from the drain of the N-type transistor to the external power supply potential VDD terminal. It is preventing.

  However, the ESD protection circuit disclosed in Patent Document 1 causes a voltage overshoot at an early stage when the protection element responds to the surge in the case of a fast surge such as CDM (Charged Device Model) which is one of ESD standards. There is a problem that the gate insulating film of the internal circuit is destroyed.

In particular, in the case of a power supply circuit in which power supply is separated on a small scale, there is a problem that ESD destruction by the CDM mode becomes remarkable.
Japanese Patent Laid-Open No. 11-14117 JP 2007-36029 A

An object of the present invention is to provide an ESD protection circuit having a high response speed and a semiconductor device using the ESD protection circuit.

An ESD protection circuit according to an embodiment of the present invention includes a first power supply input to which a first potential is applied and a second power supply input to which a second potential lower than the first potential is applied. comprising a plurality of inverters connected in said plurality of inverters, by the output terminal of the preceding stage of the inverter is connected to an input terminal of subsequent stage of the inverter are connected in series, the last stage of the plurality of inverters The output terminal of the inverter is in an open state, and when the plurality of inverters respond to an ESD surge, the potential of the connection node between the output terminal and the input terminal is the first potential and the second potential. When ing the protective potential between the potential, the plurality of inverters through current from the first power input toward the second power input flows, the said first and second power supply first 1 When the second potential is applied, the logic values of the plurality of inverters are held in a constant state.

  According to the present invention, an ESD protection circuit having a high response speed and a semiconductor device using the same can be obtained.

  Embodiments of the present invention will be described below with reference to the drawings.

  1A and 1B are diagrams showing an ESD protection circuit according to a first embodiment of the present invention and a semiconductor device using the same, FIG. 1A is a circuit diagram showing the semiconductor device, and FIG. 1B is a first ESD protection. It is a circuit diagram which shows a circuit.

  As shown in FIG. 1A, a semiconductor device 10 of this embodiment is, for example, a logic LSI, and includes an internal circuit 11, a first ESD circuit 12 that protects the internal circuit 11 from surges, and a second ESD circuit. 13.

The first ESD protection circuit 12 responds to a fast surge such as CDM (Charged Device Model) which is one of ESD standards, and the gate insulating film of the MOS transistor 14 in the internal circuit 11 is destroyed. To prevent.
The second ESD protection circuit 13 is an ESD protection circuit that responds to a surge slower than the CDM, and prevents the gate insulating film of the MOS transistor 14 in the internal circuit 11 from being destroyed. The second ESD protection circuit 13 only needs to have a slower response speed than the first ESD protection circuit 12, and a normal ESD protection circuit can be used.

  The internal circuit 11, the first ESD protection circuit 12, and the second ESD protection circuit 13 include a first external power supply input terminal 15 to which a first potential (VDD) is applied, and a second voltage lower than the first potential VDD. The second external power supply input terminal 16 to which the potential VSS (here, the ground potential GND) is applied is connected.

As shown in FIG. 1B, the first ESD protection circuit 12 includes a plurality of inverters (logic gate circuits) 17 connected in a ring shape with the output terminal of the previous stage connected to the input terminal of the subsequent stage. Yes.
That is, the first ESD protection circuit 12 is an even-numbered inverter ring, and connects the output terminal of the previous-stage inverter 17 to the input terminal of the subsequent-stage inverter 17 and connects the output terminal of the final-stage inverter 17 to the first-stage inverter 17. Is connected to the input terminal, and a closed loop is formed in which the output of the final stage is fed back to the input of the first stage.

FIG. 2 is a circuit diagram showing the inverter 17. As shown in FIG. 2, the inverter 17 is a CMOS inverter in which a P-channel MOS transistor 21 and an N-channel MOS transistor 22 are complementarily connected.
A first power supply terminal 23 of the inverter 17 is connected to the first external power supply input terminal 15, and a second power supply terminal 24 is connected to the second external power supply input terminal 16.
More specifically, inverter 17 includes a P-type transistor 21 and an N-type transistor 22 connected in series between first external power supply input terminal 15 and second external power supply input terminal 16. The gates of the P-type transistor 21 and the N-type transistor 22 are commonly connected as the input terminal 25. The drain of the P-type transistor 21 and the drain of the N-type transistor 22 are commonly connected as an output terminal 26. The source of the P-type transistor 21 is connected to the first power supply terminal 23, and the source of the N-type transistor 22 is connected to the second power supply terminal 24.

  As is well known, the CMOS inverter is given an intermediate potential when the input voltage Vin is lower than the first potential VDD and higher than the second potential VSS when the input / output voltage changes, that is, in the initial stage when the CMOS inverter responds. When this occurs, both the P-MOS transistor 21 and the N-MOS transistor 22 may become conductive, and a through current flows from the first potential VDD toward the second potential VSS.

  FIG. 3 is a timing chart showing the operation of the first ESD protection circuit 12. When the first and second potentials VDD and VSS are not applied to the first and second external power supply terminals 15 and 16, the static electricity charged in the package of the semiconductor device 10 is caused by the first and second external power supply input terminals 15. , 16 shows a simulation result when a CDM surge is generated.

In the figure, a solid line 31 with a black circle indicates a CDM surge voltage (VDD-VSS) applied between the first external power input terminal 15 and the second external power input terminal 16, and a solid line with a black square. Reference numeral 32 denotes an input voltage (Vin−VSS) generated between the input terminal 25 of the inverter 17 and the second external power supply input potential terminal 16.
A solid line 33 indicated by black triangles indicates an output voltage (Vout−VSS) generated between the output terminal of the inverter 17 and the external reference potential terminal 16, and a solid line 34 indicated by × indicates a CDM surge current (through current) flowing through the inverter 17. ).

  As shown in FIG. 3, when a fast CDM surge with a rise time of 1 ns or less occurs, the input potential Vin and the output potential Vout of the inverter 17 included in the first ESD protection circuit 12 are not fixed in such a short time, The input terminal 25 and the output terminal 26 of the inverter 17 behave as floating nodes.

In such a situation, the input voltage 32 and the output voltage 33 of the inverter 17 are in an intermediate potential between the first potential VDD and the second potential VSS in a self-aligned manner, so that the CDM surge current 31 ( Through current) flows.
More specifically, in the initial operation in which the plurality of inverters 17 respond to the ESD surge, the protective potential applied to the input terminal 25 or the output terminal 26 is a potential that is higher than the second potential Vss by the threshold voltage of the N-type transistor 22. And a potential that is lower than the first potential VDD by the absolute value of the threshold voltage of the P-type transistor 21. Thereby, both the P-type transistor 21 and the N-type transistor 22 of the inverter 17 are turned on.
For example, 8V is applied to VDD as a surge voltage, and Vss is set to 0V. If the potential of the input terminal 25 (32 in FIG. 3) rises to 6V, a potential difference of −2V is applied between the source and gate of the P-type transistor 21, and a potential difference of 6V between the source and gate of the N-type transistor. Is applied. If the absolute value of the threshold voltage of the P-type transistor 21 is set to less than 2V and the threshold voltage of the N-type transistor 22 is set to less than 6V, both the P-type transistor 21 and the N-type transistor 22 are turned on. . As a result, a through current flows through the inverter 17 (first-stage inverter).
At this time, the output terminal 26 becomes 2V. The output terminal 26 is connected to the input terminal of the next-stage inverter (second-stage inverter). Therefore, 2V is input to the input terminal of the second stage inverter. In this case, a potential difference of −6 V is applied between the source and gate of the P-type transistor of the second-stage inverter, and a potential difference of 2 V is applied between the source and gate of the N-type transistor. If the absolute value of the threshold voltage of the P-type transistor is set to less than 6V and the threshold voltage of the N-type transistor is set to less than 2V, both the P-type transistor and the N-type transistor are turned on. Thereby, a through current also flows through the second-stage inverter.
At this time, the output terminal of the second stage inverter becomes 6V. Therefore, 6V is applied to the input terminal of the next-stage inverter (third-stage inverter). Therefore, the operation of the third stage inverter is the same as the operation of the first stage inverter. The operation of the inverter at the next stage after the third stage inverter (fourth stage inverter) is the same as the operation of the second stage inverter. In this way, the inverter that inputs 6V and outputs 2V and the inverter that inputs 2V and outputs 6V are alternately connected.
In order for the inverters that perform these two types of operations to have the same configuration, the threshold voltage of the N-type transistor 22 is set to the minimum potential difference among the potential differences between the input terminal 25 and the second potential Vss in the plurality of inverters 17. Must be less than 2 V (less than 2 V in the above example). Further, when the plurality of inverters 17 respond to the ESD surge, the absolute value of the threshold voltage of the P-type transistor 21 is less than the minimum potential difference among the potential differences between the first potential VDD and the input terminal 25 in the plurality of inverters 17. (Less than 2V in the above example). Thereby, all the inverters 17 having the same configuration are turned on at the time of the ESD surge response, and a through current can flow.

  As a result, the first ESD protection circuit 12 operates to discharge the CDM surge, and works to keep the potential difference between the first external power input terminal 15 and the second external reference potential terminal 16 within a certain value.

  As a result, overshoot of the CDM surge voltage 31 is suppressed, and the gate insulating film of the MOS transistor 14 in the internal circuit 11 can be protected from ESD breakdown.

  FIG. 4 is a diagram showing the result of the surge breakdown test of the semiconductor device 10 in comparison with the comparative example. FIG. 4A is a diagram showing this example, and FIG. 4B is a diagram showing the comparative example. Here, the comparative example means a case where the semiconductor device 10 does not have the first ESD protection circuit 12.

The surge breakdown test was performed using a VF-TLP (Very Fast Transmission Line Pulse) apparatus that can apply a pulse current simulating a surge current to a DUT (Device Under Test).
For comparison, a test result with a normal TLP device having a current pulse rise time longer than that of the VF-TLP device is also shown. First, a comparative example will be described.

As shown in FIG. 4B, in the comparative example, the surge breakdown current of the VL-TLP test shows an extremely low value of about 1A.
This is because the response speed of the second ESD protection circuit 13 to the ESD surge is slower than the rising speed of the CDM surge, so that the first external power supply is caused by the overcurrent of the CDM surge before the second ESD protection circuit 13 operates. This is because the potential of the pad of the input terminal 15 is boosted above the breakdown voltage of the gate insulating film of the MOS transistor 14 of the internal circuit 11 and is destroyed by the initial voltage overshoot.

  On the other hand, the surge breakdown current in the normal TLP test shows a high value of about 8A. This is because the conventional second ESD protection circuit 13 has a sufficient response speed with respect to an ESD surge slower than the CDM surge.

As shown in FIG. 4A, in this example, the surge breakdown current in the VL-TLP test is as high as about 8A.
This is because an initial voltage overshoot does not occur because the response speed of the first ESD protection circuit 12 to the ESD surge is sufficiently higher than the rising speed of the CDM surge.

The surge breakdown current in the normal TLP test also shows a high value of about 8A. This is because the conventional second ESD protection circuit 13 functions.
FIG. 5 is a circuit diagram showing an example of a normal second ESD protection circuit 13. This is an example of a GG (Grounded Gate) MOS that uses an NPN bipolar transistor parasitic on the MOS transistor 41.

During normal operation in which the first and second external power supply input terminals 15 and 16 are supplied with the first and second potentials VDD and VSS, the even-numbered inverter ring of the first ESD protection circuit 12 operates dynamically ( Therefore, the potential of the connection node between the output terminal at the previous stage and the input terminal at the subsequent stage is fixed to the first potential VDD or the second potential VSS.
As a result, the first ESD protection circuit 12 consumes little AC current or DC current, and does not affect the normal operation of the semiconductor device 10.

Further, the even-numbered inverter ring is configured such that the input terminal of the inverter constituting the ring is connected to the output of the preceding inverter. All input terminals are coupled to the first potential VDD and the second potential VSS via the MOS transistors 21 and 22.
Therefore, it becomes easier to behave as a floating node in the initial stage of the ESD surge than in the case where it is directly connected to the first potential VDD or the second potential VSS.

There is no particular limitation on the number of inverter stages of the first ESD protection circuit 12. As the number of inverter stages increases, the surge current capacity increases, but the occupied area increases.
Therefore, the number of inverter stages may be determined according to the required surge current capacity. As a result of various studies, the number of stages of the inverter ring is suitably four or more.

  As described above, the first ESD protection circuit 12 according to the present embodiment applies the first external power supply input terminal 15 to which the first potential VDD is applied and the second potential VSS lower than the first potential VDD. And a plurality of inverters 17 connected in a ring shape with the output terminal 26 at the front stage connected to the input terminal 25 at the rear stage.

As a result, in the initial stage in which the plurality of inverters 17 respond to the ESD surge, the connection node between the output terminal 26 in the previous stage and the input terminal 25 in the subsequent stage has an intermediate level lower than the first potential VDD and higher than the second potential VSS. When a potential is applied, a through current flows through the plurality of inverters 17 from the first potential VDD toward the second potential VSS.
Therefore, the first ESD protection circuit 12 having a high response speed and the semiconductor device 10 using the same can be obtained.

Although the case where the logic gate circuit is the CMOS inverter 17 has been described here, other logic gate circuits may be used as long as the above-described through current flows.
For example, the same effect can be expected even in a logic gate circuit that partially includes a NAND gate, a NOR gate, and the like.

Although the case where the first ESD protection circuit 12 is an even-numbered inverter ring has been described, an odd-numbered inverter ring is also possible.
The odd-numbered inverter ring performs dynamic operation (ring oscillation), and thus wasteful power is consumed. However, it functions similarly as an ESD protection circuit against a CDM surge.

FIG. 6 is a circuit diagram showing a first ESD protection circuit according to Embodiment 2 of the present invention. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and only different portions will be described.
This embodiment is different from the first embodiment in that a plurality of inverters are connected in a double ring shape that shares some inverters.

  That is, as shown in FIG. 6, the first ESD protection circuit 50 according to the present embodiment includes an inverter included between the inverter 51 and the inverter 52 and an inverter included between the inverter 53 and the inverter 54 connected in a ring shape. And a second inverter ring II in which an inverter included between the inverter 51 and the inverter 52 and an inverter included between the inverter 55 and the inverter 56 are connected in a ring shape. ing.

The output terminal of the inverter 52 is branched and connected to both input terminals of the inverter 53 and the inverter 55, and the output terminals of the inverter 54 and the inverter 56 are commonly connected to the input terminal of the inverter 51. The inverters included in between are shared by the first and second inverter rings I and II.
For example, a 2-input NAND gate circuit or a 2-input NOR gate circuit is suitable as a logic gate circuit replacing the inverter 51. One of the two input terminals is connected to the output terminal of the inverter 54, and the other is connected to the output terminal of the inverter 56.

  As described above, in the ESD protection circuit 40 of this embodiment, a plurality of inverters are connected in a double ring shape that shares some inverters. This is suitable when NOT, NAND, and NOR are mixed in the logic gate circuit.

Here, a case where a part of inverters are connected in a double ring shape has been described, but a part of inverters may be connected in a multiple ring shape.
FIG. 7 is a diagram showing a first ESD protection circuit 60 in which a plurality of inverters 17 are connected in a triple ring shape sharing some inverters.

  8A and 8B are diagrams showing an ESD protection circuit according to a third embodiment of the present invention and a semiconductor device using the same, FIG. 8A is a circuit diagram showing the semiconductor device, and FIG. 8B is a first ESD protection. It is a circuit diagram which shows a circuit.

In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and only different portions will be described.
This embodiment is different from the first embodiment in that a plurality of inverters are connected in a line.

That is, as shown in FIG. 8, the semiconductor device 70 of this embodiment includes a first ESD protection circuit 71 and a second circuit 72 connected to the first ESD protection circuit 71.
The first ESD protection circuit 71 includes a plurality of inverters 17 connected in a line by connecting the output terminal of the previous stage to the input terminal of the subsequent stage.

  The input terminal of the first stage inverter 17 is connected to the output terminal of the second circuit 72, and the output terminal of the final stage inverter 17 is not connected to the input terminal of the first stage inverter 17, and is in an open state.

In the second circuit 72, when the first potential VDD and the second potential VSS are not applied to the first and second external power supply input terminals 15 and 16, the output terminal is in a floating state, and the first and second 2 A circuit that outputs a constant value when the first potential VDD and the second potential VSS are applied to the external power supply input terminals 15 and 16.
The second circuit 72 only needs to satisfy this condition. For example, an existing circuit of the semiconductor device 70 can be used.

Further, as the second circuit 72, a power-on reset circuit that is normally used for generating a reset signal of a flip-flop can be used.
FIG. 9 is a circuit diagram showing a power-on reset circuit. As shown in FIG. 9, the power-on reset circuit includes a series circuit of a resistor 81 and a capacitor 82, and an inverter 83 whose input terminal is connected to a connection node of the resistor 81 and the capacitor 82.

  When the first potential VDD and the second potential VSS are not applied to the first and second external power supply input terminals 15 and 16, the potential of the input terminal of the inverter 83 is indefinite, and the output terminal of the inverter 83 is Act as a floating node.

As a result, when an intermediate potential lower than the first potential VDD and higher than the second potential VSS is applied to the connection node between the output terminal 26 in the previous stage and the input terminal 25 in the subsequent stage, the first inverters 17 are connected to the first potential VDD. A through current flows from the potential VDD toward the second potential VSS.
Therefore, the first ESD protection circuit 71 having a high response speed and the semiconductor device 70 using the first ESD protection circuit 71 are obtained.

On the other hand, when the first potential VDD and the second potential VSS are applied to the first and second external power supply input terminals 15 and 16, the capacitor 82 is charged through the resistor 81 and the potential of the input terminal of the inverter 83 rises. .
When the potential of the input terminal of the inverter 83 becomes the first potential VDD, the inverter 83 outputs “L” level (a constant value).

  As a result, since the input terminal of the first-stage inverter 17 is fixed at the “L” level during normal operation, the first ESD protection circuit 71 does not operate dynamically, so that the first-stage output terminal and the second-stage input terminal The potential of the connection node is fixed to the first potential VDD or the second potential VSS.

  Therefore, the first ESD protection circuit 71 consumes little AC current or DC current and does not affect the normal operation of the semiconductor device 70.

As described above, the first ESD protection circuit 71 of the present embodiment includes the plurality of inverters 17 connected in a line shape with the output terminal of the previous stage connected to the input terminal of the subsequent stage.
According to this, there is an advantage that the return wiring for connecting the output terminal of the last stage inverter to the input terminal of the first stage inverter becomes unnecessary.

  Although the case where the output terminal of the final stage inverter 17 is in the open state has been described here, the output terminal of the final stage inverter 17 may be connected to an arbitrary third circuit 90 as shown in FIG. it can.

The present invention can be configured as described in the following supplementary notes.
(Supplementary note 1) The ESD protection circuit according to claim 1, wherein the plurality of logic gate circuits are connected in a multiple ring shape sharing a part of the logic gate circuits.

(Supplementary Note 2) An internal circuit connected between a first external power input terminal to which a first potential is applied and a second external power input terminal to which a second potential lower than the first potential is applied; A plurality of logic gate circuits connected in a line are connected between the first external power input terminal and the second external power input terminal, and the output terminal of the previous stage is connected to the input terminal of the subsequent stage. In an initial stage in which the plurality of logic gate circuits respond to an ESD surge, an intermediate potential lower than the first potential and higher than the second potential is applied to a connection node between the output terminal and the input terminal. When applied, a through current flows from the first potential to the second potential in the plurality of logic gate circuits, and the first and second potentials are applied to the first and second external power supply input terminals. When the first stage ESD protection circuit logic values are given in a constant state to said input terminal of said logic gate circuit.

  FIG. 11 is a configuration diagram of an ESD protection circuit according to the fourth embodiment of the present invention and a semiconductor device using the ESD protection circuit. In the semiconductor device 20 according to the fourth embodiment, in addition to the second external power input terminal 16 connected to the ground potential Vss, the first external power input terminal 15 and the third external power input terminal 15 connected to the plurality of potentials VDD1 and VDD2, respectively. The external power input terminal 25 is provided. That is, Example 4 is an embodiment having a plurality of power supplies having different potentials. The potential VDD2 is a potential higher than Vss and lower than VDD1. Although only two types of power supply potentials VDD1 and VDD2 are shown in FIG. 11, as described later, the semiconductor device of the present invention may have three or more types of power supply potentials.

  In the fourth embodiment, each configuration and connection relation of the internal circuit 11, the first ESD protection circuit 12, the second ESD protection circuit 13, the first external power input terminal 15 and the second external power input terminal 16 are as follows. The configuration and connection relationship in any one of the first to third embodiments may be the same.

  In the fourth embodiment, the internal circuit 21 connected between the second external power input terminal 16 and the third external power input terminal 25, the second external power input terminal 16, and the third external power input terminal A third ESD protection circuit 23 connected between the first external power supply input terminal 15 and the second external power supply input terminal 16, and a power supply potential VDD2. And a third external power input terminal 25 connected to.

  The configuration of the third ESD protection circuit 23 may be the same as the configuration of the second ESD protection circuit 13. That is, the third ESD protection circuit 23 is an ESD protection circuit that responds to an ESD surge slower than the CDM, like the second ESD protection circuit 13, and the gate insulating film of the MOS transistor 24 in the internal circuit 21. To prevent being destroyed. The third ESD protection circuit 23 only needs to have a response speed slower than that of the first ESD protection circuit 12 and the surge transfer circuit 31, and a normal ESD protection circuit can be used. The response speed of the third ESD protection circuit 23 may be almost the same as that of the second ESD protection circuit 13.

  The response speed of the surge transfer circuit 31 is approximately the same as or higher than the response speed of the first ESD protection circuit 12. The surge transfer circuit 31 is a circuit that operates when the second external power input terminal 25 becomes higher in potential than the first external power input terminal 15.

  The internal circuit 11 and the internal circuit 21 to be protected operate by receiving different power supply potentials VDD1 and VDD2, respectively. When a CDM surge is input to the first external power supply input terminal 15, Example 4 operates in the same manner as in the first embodiment. Therefore, description of the operation in this case is omitted.

  Here, no ESD protection circuit corresponding to the first ESD protection circuit 12 is provided between the third external power supply input terminal 25 and the second external power supply input terminal 16. That is, a protection circuit that responds to a fast surge such as a CDM surge is not provided for the internal circuit 21. Accordingly, when a CDM surge is input to the third external power supply input terminal 25, the fourth embodiment operates as follows.

  When a CDM surge is input to the third external power supply input terminal 25, the third ESD protection circuit 23 does not operate at the initial stage. However, since the potential of the third external power input terminal 25 is considerably larger than the potential of the first external power input terminal 15, the surge transfer circuit 31 sends a surge current from the third external power input terminal 25 to the first. Transfer to the external power input terminal 15 at high speed. As a result, the surge current passes through the first ESD protection circuit 12 and flows to the second potential VSS. As a result, the voltage overshoot between the power supply potential VDD2 and the reference potential VSS can be suppressed, and the internal circuit 21 can be protected from the CDM surge.

  The surge transfer circuit 31 together with the first ESD protection circuit 12 becomes a part of a discharge path for suppressing the voltage overshoot of the power supply potential VDD2. Therefore, the surge transfer circuit 31 needs to operate at a higher speed than the second and third ESD protection circuits 13 and 23 in the response speed to the CDM surge, and the first ESD protection circuit 23 It is necessary to operate the same or faster (Condition 1).

  Further, the surge transfer circuit 31 should not be conducted during normal operation, and operates only when an ESD surge occurs (condition 2). That is, the surge transfer circuit 31 needs to be turned on only when an EDS surge occurs, and is applied between the first external power input terminal 15 and the third external power input terminal 25 in normal operation. Must not conduct at a certain potential difference.

  12A to 12E are diagrams showing specific examples of the surge transfer circuit 31 that satisfies the conditions 1 and 2. FIG.

  As shown in FIG. 12A, the surge transfer circuit 31 may be a single diode. The anode of the diode is connected to the third external power supply input terminal 25, and the cathode of the diode is connected to the first external power supply input terminal 15. The single diode operates at a higher speed than an inverter, a diode string, a thyristor, or the like that can form the first ESD protection circuit 12. Therefore, the single diode can satisfy the condition 1.

  Further, since VDD2 is lower than VDD1 in normal operation, the surge transfer circuit 31 separates the first external power supply input terminal 15 and the third external power supply input terminal 25 from each other. On the other hand, when the CDM surge is applied to the third external power input terminal 25, the potential of the third external power input terminal 25 is higher than the potential of the first external power input terminal 15 in a short time. Overshoot to. In this case, the surge transfer circuit 31 causes a surge current to flow from the third external power input terminal 25 to the first external power input terminal 15. Therefore, the single diode can satisfy the condition 2.

  As shown in FIG. 12B, the surge transfer circuit 31 may be a diode string in which a plurality of diodes are connected in series. The anode of the diode string is connected to the third external power supply input terminal 25, and the cathode of the diode string is connected to the first external power supply input terminal 15.

  By changing the number of diode stages, the reaction speed of the surge transfer circuit 31 can be made lower than the reaction speed of the first ESD protection circuit 12. For example, when the first ESD protection circuit 12 is also composed of a diode string, the number of diode stages of the surge transfer circuit 31 is smaller than the number of diode stages of the first to third ESD protection circuits 12, 13 and 23. You only have to set it. Thereby, the diode string can satisfy the condition 1.

  Similarly to the single diode shown in FIG. 12A, this diode string separates between the first external power input terminal 15 and the third external power input terminal 25 in normal operation. Yes. However, when a CDM surge is applied to the third external power input terminal 25, a surge current flows to the first external power input terminal 15. Therefore, the diode string can satisfy the condition 2.

  As shown in FIG. 12C, the surge transfer circuit 31 may be a thyristor. By adjusting the distance between the anode and the cathode of the thyristor, the reaction rate of the surge transfer circuit 31 can be made lower than the reaction rate of the first ESD protection circuit 12. For example, it can be set below the reaction speed of the first ESD protection circuit 12. For example, when the first ESD protection circuit 12 is also composed of a thyristor, the distance between the anode and the cathode of the thyristor of the surge transfer circuit 31 is the second ESD protection circuit 13 or the third It is shorter than that of the ESD protection circuit 23. When a thyristor is used, it is necessary to increase the speed of the trigger element attached to it.

  In the normal operation, the thyristor separates between the first external power input terminal 15 and the third external power input terminal 25, and a CDM surge is applied to the third external power input terminal 25. In the case of a failure, a surge current is passed to the first external power input terminal 15. Therefore, the thyristor can satisfy the condition 2.

  As shown in FIG. 12D or FIG. 12E, the surge transfer circuit 31 may be configured by NMOS or PMOS. When the surge transfer circuit 31 is an NMOS, the gate is connected to the second external power input terminal 16. When the source is connected to the second external power input terminal 16 together with the gate, the surge transfer circuit 31 is a GGNMOS (Gate Grounded NMOS).

  When the surge transfer circuit 31 is a PMOS, the gate is connected to the first external power supply input terminal 15 together with the source. By adjusting the channel length of the NMOS or PMOS, the reaction speed of the surge transfer circuit 31 can be made lower than the reaction speed of the first ESD protection circuit 12. For example, when the first ESD protection circuit 12 is also composed of NMOS or PMOS, the channel length of the NMOS or PMOS constituting the surge transfer circuit 31 is shorter than that of the first ESD protection circuit 12. Thereby, the NMOS and the PMOS can satisfy the condition 1.

  In addition, these NMOS and PMOS are separated between the first external power input terminal 15 and the third external power input terminal 25 in normal operation, and CDM surge is applied to the third external power input terminal 25. Is applied to the first external power supply input terminal 15. Therefore, the NMOS and the PMOS can satisfy the condition 2.

  11, only two power supply potentials VDD1 and VDD2 are shown, but the number of power supplies may be 3 or more (VDDn (n is an integer of 3 or more). In this case, the most potential among VDDn A first ESD protection circuit 12 capable of coping with CDM surge is connected to an external power input terminal corresponding to a high power source.

  Furthermore, a surge transfer circuit 31 is provided between VDD (i−1) and VDDi (3 ≦ i ≦ n). The cathode side of the surge transfer circuit 31 is connected to the input terminal having the higher power supply potential, and the anode side thereof is connected to the input terminal having the lower power supply potential. Thus, a forward bias is not applied to the surge transfer circuit 31 during normal operation. Therefore, Condition 2 can be satisfied.

  The plurality of surge transfer circuits 31 may employ any of the configurations shown in FIGS. 12A to 12E. The plurality of surge transfer circuits 31 may all have the same configuration or different configurations.

  In the fourth embodiment, when a CDM surge is input to any one of the external power input terminals, the surge current is transferred to the first ESD protection circuit 12 via one or a plurality of surge transfer circuits 31, 1 flows through the ESD protection circuit 12 to Vss. Thereby, a plurality of internal circuits connected to each power source are protected from CDM surge.

  In the fourth embodiment, even when a plurality of separated power supplies are provided, it is not necessary to provide the first ESD protection circuit 12 capable of coping with CDM for each power supply, and one first ESD is provided. The protection circuit 12 only needs to be provided in common for a plurality of external power supply input terminals.

  The surge transfer circuit 31 has a smaller installation area than the first ESD protection circuit 12. For example, the surge transfer circuit 31 can be composed of a single diode. The first ESD protection circuit 12 needs to be a diode string composed of at least a plurality of diodes. Even when the surge transfer circuit 31 and the first ESD protection circuit 12 are formed of a diode string, the number of diode stages in the surge transfer circuit 31 is smaller than that of the first ESD protection circuit 12. Even when the surge transfer circuit 31 and the first ESD protection circuit 12 are formed of thyristors, the anode-cathode distance of the surge transfer circuit 31 is shorter than that of the first ESD protection circuit 12. Even if the surge transfer circuit 31 and the first ESD protection circuit 12 are composed of NMOS or PMOS, the gate length of the surge transfer circuit 31 is shorter than that of the first ESD protection circuit 12.

  Even if the surge transfer circuit 31 and the first ESD protection circuit 12 are different types of ESD protection circuits, the surge transfer circuit 31 has a smaller installation area than the first ESD protection circuit 12.

  As in the fourth embodiment, by providing one first ESD protection circuit 12 in common to a plurality of external power supply input terminals, the chip size of the entire semiconductor device can be reduced. Furthermore, Example 4 can obtain any of the effects of Example 1 to Example 3.

  The configuration of the semiconductor device according to the fifth embodiment may be the same as that of the semiconductor device according to the fourth embodiment. Therefore, Embodiment 5 will be described with reference to FIG.

  In the fifth embodiment, the potential VDD1 of the first external power input terminal 15 provided with the first ESD protection circuit 12 capable of dealing with CDM surge can always deal with CDM surge during normal operation and standby. The potential is the same as or lower than the potential VDD2 of the third external power supply input terminal 25 having no ESD protection circuit.

  For example, during standby, the third external power input terminal 25 is disconnected from the potential VDD2, while the first external power input terminal 15 maintains a connection with the potential VDD1. In other words, the third external power input terminal 25 is disconnected from the potential VDD2 during standby in order to reduce power consumption while the first external power input terminal 15 is always powered on.

  As a result, the surge transfer circuit 31 does not operate even during standby unless an ESD surge occurs. Therefore, in the fifth embodiment, power consumption can be suppressed by partially disconnecting the power supply from the power supply input terminal during standby, and at the same time, when an ESD surge occurs, the internal circuit is protected. be able to.

  When there are three or more power supply voltages, the configuration of the fifth embodiment may be the same as the configuration of the fourth embodiment. In the fifth embodiment, only the maximum voltage of the power supply voltage VDDn is always turned on. As a result, when a high-speed ESD surge such as CDM is applied, the fifth embodiment can secure a discharge path for suppressing voltage overshoot and uses a partial power-off technique. Power consumption can be suppressed.

  As a power supply (VDD1) connected to the first external power supply input terminal 15, it is conceivable to use a power supply for an I / O (Input / Output) circuit (a power supply for driving a signal input / output circuit). This is because the I / O circuit power supply generally uses a higher voltage than the power supply used in the internal circuit. In general, it is unclear when a signal is input to a signal input terminal. Therefore, the power supply for the I / O circuit is normally always turned on. Therefore, the power supply for the I / O circuit is suitable as a power supply connected to the first external power supply input terminal 15 connected to the first ESD protection circuit 12 capable of coping with CDM surge.

  In the fifth embodiment, the power supply other than the power supply connected to the power supply input terminal corresponding to the ESD protection circuit capable of dealing with the CDM surge is cut off from the power supply input terminal during standby. Thereby, the power consumption at the time of standby can be suppressed. In the fifth embodiment, the effects of the fourth embodiment can be further obtained.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the ESD protection circuit which concerns on Example 1 of this invention, and a semiconductor device using the same, FIG. 1 (a) is a circuit diagram which shows a semiconductor device, FIG.1 (b) shows a 1st ESD protection circuit. circuit diagram. 1 is a circuit diagram showing a logic gate circuit of a first ESD protection circuit according to Embodiment 1 of the present invention; 3 is a timing chart showing the operation of the first ESD protection circuit according to the first embodiment of the invention. FIG. 4A is a diagram illustrating a surge breakdown test result of a semiconductor device according to Example 1 of the present invention in comparison with a comparative example, and FIG. 4A is a diagram illustrating the present example, and FIG. 4B is a diagram illustrating the comparative example. . The circuit diagram which shows the normal 2nd ESD protection circuit. The circuit diagram which shows the 1st ESD protection circuit which concerns on Example 2 of this invention. The circuit diagram which shows another 1st ESD protection circuit which concerns on Example 2 of this invention. FIGS. 8A and 8B are diagrams showing an ESD protection circuit and a semiconductor device using the same according to Embodiment 3 of the present invention, FIG. 8A is a circuit diagram showing the semiconductor device, and FIG. 8B is a first ESD protection circuit. circuit diagram. FIG. 6 is a circuit diagram showing a second circuit of a semiconductor device according to Example 3 of the invention. The circuit diagram which shows another 1st ESD protection circuit which concerns on Example 3 of this invention. The block diagram of the ESD protection circuit according to Example 4 which concerns on this invention, and a semiconductor device using the same. The figure which shows the specific example of the surge transfer circuit 31. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 70 Semiconductor device 11 Internal circuit 12, 50, 60, 71 1st ESD protection circuit 13 2nd ESD protection circuit 14 MOS transistor 15 1st external power supply input terminal 16 2nd external power supply input terminals 17, 51-56 , 83 Inverter (logic gate circuit)
21 P-MOS transistor 22 N-MOS transistor 23 First power supply terminal 24 Second power supply terminal 25 Input terminal 26 Output terminal 72 Second circuit 81 Resistor 82 Capacitor 90 Third circuit VDD First potential VSS Second potential

Claims (5)

A plurality of inverters connected between a first power input to which a first potential is applied and a second power input to which a second potential lower than the first potential is provided;
The plurality of inverters are connected in series by connecting the output terminal of the preceding inverter to the input terminal of the succeeding inverter ,
The output terminal of the final stage inverter among the plurality of inverters is in an open state,
When said plurality of inverters to ESD surge responds, when the potential at the node between the input terminal and the output terminal is ing the protective potential between said second potential and the first potential, the through current from the first power input toward the second power input flows into a plurality of inverters,
An ESD protection circuit, wherein logic values of the plurality of inverters are held in a constant state when the first and second potentials are applied to the first and second power inputs. . 2. The ESD protection circuit according to claim 1, wherein the plurality of inverters are connected in a line by connecting an output terminal of the preceding inverter to an input terminal of the succeeding inverter . The inverter comprises one or more inverters;
The inverter includes a P-type transistor and an N-type transistor connected in series between the first power input and the second power input,
The gates of the P-type transistor and the N-type transistor are commonly connected as the input terminal,
Each one end of the P-type transistor and the N-type transistor is commonly connected as the output terminal,
The other end of the P-type transistor is connected to the first external power input terminal,
The other end of the N-type transistor is connected to the second external power input terminal,
When a plurality of inverters respond to an ESD surge, the protection potential is a potential that is higher than the second potential by the threshold voltage of the N-type transistor and an absolute value of the threshold voltage of the P-type transistor from the first potential. The ESD protection circuit according to claim 1, wherein the ESD protection circuit is a potential between a potential lower by a value. A surge transfer unit connected between a third power input to which a third potential higher than the second potential and lower than the first potential is applied, and the first power input;
When an ESD surge is input to the third power input, the surge transfer unit transfers a surge current from the third power input to the first power input.
The ESD protection circuit according to claim 1, wherein the plurality of inverters are provided in common to the first and third power supply inputs.   The ESD protection circuit according to claim 4, wherein the third potential is equal to or lower than the first potential.

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