JP5167675B2 - Semiconductor fuse device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor fuse device having a structure for cutting off current by fusing a semiconductor fuse wiring structure and a method for manufacturing the same.

This type of semiconductor fuse device is disclosed in Patent Document 1, for example. FIG. 10 shows a schematic diagram of a conventional semiconductor fuse device. As shown in FIG. 10, a metal wiring layer (main wiring layer) 2 is formed on an insulating layer 1, and a metal wiring layer (main wiring layer) 4 is formed on the metal wiring layer 2 via an insulating layer 3. Is formed. Between the metal wiring layers 2 and 4, the contact 4 a of the metal wiring layer 4 is formed so as to contact only the upper surface of the metal wiring layer 2, and the diameter of the contact 4 a is smaller than the other parts. When an overcurrent flows through the contact 4a, the contact 4a portion is melted.
Japanese Patent Laid-Open No. 06-151424

However, in the structure described above, the contact area between the contact 4a and the metal wiring layer 4 is larger than the internal resistance of the contact 4a because the cross-sectional area of the contact 4a and the contact area between the metal wiring layer 4 are the same. There was a problem that it was. Therefore, there is a problem in that it is difficult to design a breaking current because the breaking current of the fuse is limited by the contact resistance.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor fuse device capable of easily designing a breaking current.

  According to the first aspect of the present invention, the fuse wiring portion includes a to-be-melted portion formed by structurally connecting a plurality of main wiring layers, and is provided in a region different from the to-be-melted portion and is connected to the main wiring. Since the contact portion in contact with the upper surface and the side surface of the layer is formed, the contact resistance can be reduced as compared with the conventional case, and the breaking current design can be easily performed.

In addition, the main wiring layer is made of polycrystalline silicon, and the fuse wiring portion is made up of a metal layer and a barrier metal film provided between the metal layer and the main wiring layer. The contact resistance with silicon can be reduced.

According to the invention described in claim 3 , since the fuse wiring portion is formed in an uneven shape at least at the interface of the contact portion that contacts the main wiring layer, the contact portion is formed flat. As a result, the contact area between the fuse wiring portion and the main wiring layer can be increased, and the contact resistance can be reduced.
According to the fourth aspect of the present invention, since the melted part of the fuse wiring part is composed of only a single metal layer, it is easy to adjust the disconnection temperature of the fuse wiring part.

  According to the fifth aspect of the present invention, since the space is provided between the protective film that covers the part to be melted of the fuse wiring part and the part to be melted, the part to be melted is formed by applying an overcurrent. Even if fusing and unwanted materials are scattered, it is possible to suppress adverse effects on other semiconductor structure regions as much as possible.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
FIG. 1A is a top view of a fuse wiring portion constituting the semiconductor fuse device, and FIG. 1B is a cross-sectional view of the fuse wiring portion (a cross section taken along line AA in FIG. 1A). FIG. 1C shows a state where the melted portion of the semiconductor fuse device is blown.

  As shown in FIG. 1B, the semiconductor fuse device 10 is formed on the semiconductor layer 11 via an interlayer insulating film 12. The interlayer insulating film 12 has a flat upper surface, and a plurality of impurity-doped polycrystalline silicon layers 13 as main wiring layers are formed on the interlayer insulating film 12. A fuse wiring portion 14 is formed between the plurality of polycrystalline silicon layers 13. The fuse wiring part 14 includes a melted part 14a formed on the upper surface of the interlayer insulating film 12, a side wall part 14b formed along a part of the side wall surface part 13a of the polycrystalline silicon layer 13, and polycrystalline silicon. And a flat portion 14 c formed along a part of the upper surface portion 13 b of the layer 13. The fuse wiring portion 14 has a side wall portion 14b and a flat portion 14c formed with substantially the same film thickness, and the side wall portion 14b and a part of the side surface portion 13a of the polycrystalline silicon layer 13 are in contact with each other. 14c and a part of the upper surface portion 13b of the polycrystalline silicon layer 13 are in contact with each other. Reference numerals 13c and 14d are attached to the contact portions.

  The fuse wiring portion 14 is made of aluminum (Al), and includes a to-be-melted portion 14a that is melted by an overcurrent, and the to-be-melted portion 14a is formed on the upper surface of the interlayer insulating film 12. It is configured. The to-be-melted portion 14a has a cross-sectional area orthogonal to the direction in which the current flows, and is substantially the same as or narrower than the cross-sectional area of the side wall portion 14b and the flat portion 14c. Can be adjusted.

  In addition, the to-be-melted part 14a and the contact part 13c (14d) are provided in another area | region. The main part of the fuse wiring part 14 is formed in a concave shape. The protective film 15 is formed of, for example, a silicon nitride film (SiN) or PIQ, and is formed so as to cover the fuse wiring portion 14. Moreover, the space part 16 is provided in the area | region enclosed in the concave shape by the to-be-cut part 14a and the side wall part 14b.

  As shown in FIGS. 1B and 1C, the space 16 is provided between the melted part 14 a and the protective film 15. The space portion 16 is configured to be able to accommodate a fusing material trace that has been melted and scattered by an overcurrent flowing through the melted portion 14a. Thereby, even if the to-be-melted part 14a is melted, it is possible to suppress as much as possible that an adverse effect is exerted on the formation region of another semiconductor structure. The space 16 may be provided as necessary.

  The operation of the above configuration will be described. A current flows between the plurality of polycrystalline silicon layers 13. At this time, when an overcurrent is applied to the to-be-cut portion 14a having a particularly small cross-sectional area, the to-be-cut portion 14a is blown and a fusing mark remains in the space portion 16 as shown in FIG.

  A method of manufacturing the above structure will be described with reference to FIGS. For the sake of convenience of explanation, as to manufacturing components (referred to as manufacturing elements) corresponding to the constituent elements (referred to as structural elements) of the respective films and layers described above, the reference numerals assigned to the structural elements are used as necessary. A reference numeral added with 100 is added as a manufacturing element code. Accordingly, the manufacturing elements shown below correspond to the structural elements with the reference numerals obtained by subtracting 100 from the reference numerals assigned to the manufacturing elements.

  As shown in FIG. 2, an interlayer insulating film 112 and a polycrystalline silicon layer 113 are sequentially stacked on the semiconductor layer 111, and the polycrystalline silicon layer 113 is divided into a plurality of grooves 113z as shown in FIG. . Next, as shown in FIG. 4, an aluminum layer 114 is isotropically formed inside the groove 113z by a sputtering method and divided into the design dimensions of the fuse wiring portion 14 according to the design dimensions. The aluminum layer 114 includes an inner surface portion (lower end surface portion) 114a along the upper surface of the interlayer insulating film 112, a side wall portion 114b along a part of the side surface portion 113a of the polycrystalline silicon layer 113, and an upper surface portion 113b of the polycrystalline silicon layer 113. Are integrally formed by an upper end portion (upper end surface portion) 114c along a part of the upper portion, and these are formed in the same process. FIG. 4 shows a manufacturing method when the space portion 16 is not configured, but FIG. 5 shows a manufacturing method when the space portion 16 is configured.

  As shown in FIG. 5, by adjusting the distance between the plurality of polycrystalline silicon layers 113 and the film thicknesses of the respective films 113 and 114, the inner upper end portion 114e of the aluminum layer 114 is brought into contact and the upper portion of the aluminum layer 114 is closed. A void 116 that is entirely covered with the aluminum layer 114 is formed on the inner side of the layer 114 to form a portion that becomes a base of the fuse wiring portion 14. Next, a protective film 115 is formed on the aluminum layer 114. In this case, since the inner upper end 114e of the aluminum layer 114 is closed, the protective film 15 does not enter the void 116.

  Next, as shown in FIG. 6, the aluminum layer 114 is flowed by heat treatment at a temperature of 660 ° C. or higher, which is the melting temperature of the aluminum layer 114. Then, the inner upper end portion 114e of the void 116 is spaced outward on both sides, and the fuse wiring portion 14 can be formed while the space portion 16 is provided.

  According to the present embodiment, the contact portion 13c (14d) that structurally connects the polycrystalline silicon layer 13 and the fuse wiring portion 14 is formed on part of the side surface portion 13a and the upper surface portion 13b of the polycrystalline silicon layer 13. Accordingly, the contact area can be increased as compared with the conventional case, and the contact area between the polycrystalline silicon layer 13 and the fuse wiring portion 14 can be increased. Thereby, the contact resistance of the contact part 13c can be reduced compared with the internal resistance of the fuse wiring part 14 (aluminum).

  In addition, it is possible to easily design the breaking current by adjusting the cross-sectional area of the melted portion 14a provided in a region different from the contact portion 14d (side wall portion 14b or flat portion 14c). Moreover, the dimension design of the fuse wiring part 14 can be easily performed by the dimension design of the side wall part 14b and the flat part 14c.

  Further, since the space portion 16 is provided between the protective film 15 covering the melted portion 14a of the fuse wiring portion 14 and the melted portion 14a, the melted portion 14a is melted by applying an overcurrent. Even if the unwanted matter is scattered, it is accommodated in the space portion 16, and adverse effects on other semiconductor structure regions can be suppressed as much as possible.

(Second Embodiment)
FIG. 7 shows a second embodiment of the present invention. The difference from the previous embodiment is that a barrier wiring provided with a fuse wiring portion interposed between an aluminum layer, the aluminum layer and a polycrystalline silicon layer. It is in the place provided with the film. The same parts as those in the previous embodiment are denoted by the same reference numerals, description thereof is omitted, and only different parts will be described below.

A semiconductor fuse device 20 that replaces the semiconductor fuse device 10 includes a fuse wiring portion 17 that replaces the fuse wiring portion 14. As shown in FIG. 7, the fuse wiring portion 17 includes a barrier metal film 18 and an aluminum layer 19. The barrier metal film 18 is formed from a metal-containing material such as AlSi, Ti, or TiN. The barrier metal film 18 is formed between the aluminum layer 19 and the polycrystalline silicon layer 13 and is formed between the aluminum layer 19 and the interlayer insulating film 12 to reduce contact resistance. ing. More specifically, the barrier metal film 18 is formed along a part of the upper surface part 13 b and a part of the side surface part 13 a of the plurality of polycrystalline silicon layers 13, and the interlayer insulating film 12. Are formed on the exposed upper surface of the substrate. Since the structure of the other fuse wiring portion 17 is substantially the same as that of the fuse wiring portion 14, the description thereof is omitted.
In this embodiment, since the fuse wiring portion 17 has a structure including the aluminum layer 19 and the barrier metal film 18, the contact resistance can be reduced.

(Third embodiment)
FIG. 8 shows a third embodiment of the present invention. The difference from the second embodiment is that the part to be cut is formed by only an aluminum layer. The same parts as those of the second embodiment are denoted by the same reference numerals and description thereof is omitted, and only different parts will be described below.

  A semiconductor fuse device 30 that replaces the semiconductor fuse device 20 includes a fuse wiring portion 31 that replaces the fuse wiring portion 17. The fuse wiring portion 31 is different from the fuse wiring portion 17 in that the barrier metal film 18 is divided on the upper surface of the interlayer insulating film 12 and the aluminum layer 19 is formed along the upper surface of the interlayer insulating film 12. In other words, the melted part 31a is formed only by the aluminum layer 19a.

  In the present embodiment, since the melted part 31a is formed only by the aluminum layer 19a made of a single material, the disconnection temperature of the melted part 31a is compared with the case where the melted part is composed of two or more different materials. Adjustment can be performed easily.

(Fourth embodiment)
FIG. 9 shows a fourth embodiment of the present invention. The difference from the first embodiment is that the upper surface and side surfaces of the polycrystalline silicon layer are rough and uneven, thereby increasing the surface area and making contact. The resistance is being reduced. The same parts as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted, and only different parts will be described below.

  As shown in the semiconductor fuse device 40 of FIG. 9, the polycrystalline silicon layer 13 has a side surface portion 13a and an upper surface portion 13b which are rough. This is because, in the step of forming the polycrystalline silicon layer 13, the exposed portion of silicon is subjected to heat treatment, a Bosch process is applied to etching processing when silicon is divided into a plurality of portions, or a resist is patterned on the silicon. Sometimes it can be formed by defocusing the photolithography conditions and performing an etching process. Then, the contact area between the polycrystalline silicon layer 13 and the fuse wiring part 14 can be increased, and the contact resistance can be reduced.

(Other embodiments)
The present invention is not limited to the above embodiment, and for example, the following modifications or expansions are possible.
Although aluminum is applied as the metal layer constituting the fuse wiring portions 14 and 17, other metal may be used as necessary. Although the polycrystalline silicon layer 13 is applied as the main wiring layer, other wiring materials may be applied.
In the fourth embodiment, the fuse wiring portion 14 made of aluminum is applied. Instead, the fuse wiring having the barrier metal film 18 as described in the second or third embodiment. The units 17 and 31 may be applied.

1 is a structural view of a semiconductor fuse device showing a first embodiment of the present invention ((a) is a top view, (b) is a vertical side view taken along line AA in FIG. 1 (a), and (c) is at the time of fusing) Vertical side view) Explanatory drawing of a manufacturing process (the 1) Explanatory drawing of a manufacturing process (the 2) Explanatory drawing of a manufacturing process (the 3) Explanatory drawing of a manufacturing process (the 4) Explanatory drawing of a manufacturing process (the 5) FIG. 1B equivalent view showing the second embodiment of the present invention. FIG. 1B equivalent view showing the third embodiment of the present invention. FIG. 1B equivalent diagram showing the fourth embodiment of the present invention. Fig. 1 (b) equivalent diagram showing a conventional example

Explanation of symbols

  In the drawing, 10, 20, 30, 40 are semiconductor fuse devices, 13 is a polycrystalline silicon layer (main wiring layer), 13a is a side surface portion of the polycrystalline silicon layer (side surface portion of the main wiring layer), and 13b is polycrystalline silicon. 14 and 17 are fuse wiring parts, 14a is a melted part, 13c and 14d are contact parts, 15 is a protective film, 16 is a space part, 18 is a barrier metal film, Reference numeral 19 denotes an aluminum layer (metal layer).

Claims (7)

A structure to be structurally connectable between a plurality of main wiring layers and to be blown when an overcurrent is applied,
A plurality of contact portions that are structurally connected to the melt-cut portion and are provided in a region different from the melt-cut portion and are in contact with the top and side surfaces of the plurality of main wiring layers,
A fuse wiring portion formed in the presence of
The main wiring layer is made of polycrystalline silicon,
The fuse wiring portion is constituted by a metal layer and a barrier metal film provided between the metal layer and the main wiring layer . The semiconductor fuse device according to claim 1,
The semiconductor fuse device, wherein the fuse wiring portion is formed in a concavo-convex shape at least at an interface of a contact portion that contacts the main wiring layer . A structure to be structurally connectable between a plurality of main wiring layers and to be blown when an overcurrent is applied,
A plurality of contact portions that are structurally connected to the melt-cut portion and are provided in a region different from the melt-cut portion and are in contact with the top and side surfaces of the plurality of main wiring layers,
A fuse wiring portion formed in the presence of
The semiconductor fuse device, wherein the fuse wiring portion is formed in a concavo-convex shape at least at an interface of a contact portion that contacts the main wiring layer . The semiconductor fuse device according to claim 3 , wherein
2. A semiconductor fuse device according to claim 1, wherein a portion to be melted of the fuse wiring portion is constituted by only a single metal layer . The semiconductor fuse device according to any one of claims 1 to 4,
Provided with a protective film covering the melt-cut portion of the fuse wiring portion,
A semiconductor fuse device, wherein a space portion is provided between a portion to be cut of the fuse wiring portion and the protective film. A manufacturing method for manufacturing the semiconductor fuse device according to claim 1 or 3 ,
Forming a plurality of main wiring layers;
A plurality of contact portions that respectively contact a part of the side surfaces and the upper surface of the plurality of main wiring layers, a to-be-cut portion that is provided in a region different from the plurality of contact portions and structurally connects the plurality of contact portions, And a step of forming a fuse wiring portion provided with a semiconductor fuse device. 7. The method of manufacturing a semiconductor fuse device according to claim 6, further comprising a step of forming a rough side surface and an upper surface of the main wiring layer in an uneven shape.

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