JP5175256B2 - Capacitive touch panel and manufacturing method thereof - Google Patents

Description

  The present invention relates to a capacitive touch panel used as an input device for operation input of an electronic device, and a method for manufacturing the same.

  In order to improve the operability of portable devices, a display-integrated touch panel input device is increasingly used. Conventionally, the resistive film method has been the main method for realizing touch panels, but in recent years, the capacitive type has been expanding the market.

  FIG. 4A is a plan view showing an example of a conventional capacitive touch panel 100, and FIG. 4B is a side view seen from the left side of FIG. 4A. The capacitive touch panel 100 includes a substrate 101, a first electrode layer 102, a first insulating layer 103, a second electrode layer 104, a second insulating layer 105, a first metal film 106, and a second metal film 107. The first electrode layer 102 to the second insulating layer 105 are sequentially stacked on the substrate 101 as shown in FIG. The first electrode layer 102 is an ITO film that is a transparent conductive film. The first electrode layer 102 includes a plurality of striped (four in FIG. 4A) electrode portions 102a and a plurality of wiring portions 102b that are the respective lead wires. Become. The first insulating layer 103 is a film made of a transparent insulating material, and electrically insulates the first electrode portion 102a and the second electrode portion 104a. The second electrode layer 104 is an ITO film which is a transparent conductive film, and as shown in FIG. 4A, a plurality of stripe-shaped electrode portions orthogonal to the electrode portion 102a of the first electrode layer 102 when viewed in plan. 104a and a plurality of wiring portions 104b which are the respective lead wires. The electrode portion 102a of the first electrode and the electrode portion 104a of the second electrode arranged in this way constitute an orthogonal coordinate system, and electrostatic capacitance generated between a contact object such as a finger to the panel and each electrode portion. It is possible to detect the position coordinates of the contact object on the panel from the change of. The second insulating layer 105 is a protective film made of a transparent insulating material. The first metal film 106 and the second metal film 107 are conductors that coat each wiring part in order to reduce the resistance of the wiring part 102b of the first electrode layer and the wiring part 104b of the second electrode layer, respectively. However, depending on the length of the wiring portion, it may be applied only to one wiring portion having a longer wiring length. Note that the other end of the wiring portion 102b of the first electrode layer and the wiring portion 104b of the second electrode layer with respect to the electrode side end is crimped and connected to a printed circuit board such as an FPC at the crimping portion 108.

  Such a conventional capacitive touch panel 100 is manufactured by a complicated process similar to the TFT liquid crystal manufacturing process. FIG. 5 shows the manufacturing process. First, ITO is deposited on the transparent substrate 101 (S101), and a metal film is deposited by sputtering or the like in a stacked manner (S102). Subsequently, the metal film is patterned into the shape of the first metal film 106 (= the shape of the wiring portion 102b of the first electrode layer) (S103), and the ITO film deposited in S101 exposed in S103 is used as the first electrode layer. The electrode portion 102a is patterned into a shape (S104). Subsequently, a transparent insulating film is deposited on the first electrode layer 102 (S105), and the insulating film is patterned into a shape covering the electrode portion 102a to form the first insulating layer 103 (S106). Subsequently, ITO is deposited on the first insulating layer 103 (S107), and a metal film is deposited by sputtering or the like in a stacked manner (S108). Subsequently, the metal film is patterned into the shape of the second metal film 107 (= the shape of the wiring portion 104b of the second electrode layer) (S109), and the ITO film deposited in S107 exposed in S109 is used as the second electrode layer. The electrode portion 104a is patterned into a shape (S110). Then, a transparent insulating film is deposited on the second electrode layer 104 (S111), and the second insulating film 105 is formed by patterning the insulating film so as to cover the electrode portion 104a of the second electrode layer ( S112).

Japanese Patent Laid-Open No. 2001-216090 JP 2003-196030 A

  Since the capacitive touch panel 100 has a two-layer structure in which the wiring portion is formed by depositing a metal film on the ITO film, the ITO film, the metal film, and the insulating film are deposited and patterned as shown in FIG. It is necessary to go through a complicated manufacturing process to repeat. Moreover, it is necessary to deposit a metal film widely also in parts other than a wiring part on manufacture. For this reason, the price is several times higher than that of the resistive film type, and it has been difficult to adopt in the market.

  In the resistive film type touch panel, a method of reducing the resistance of the wiring by performing electroplating on the wiring portion instead of the metal film is disclosed (see Patent Documents 1 and 2). Even in a capacitive touch panel, if plating can be employed instead of a metal film for the coating of the wiring portion, cost reduction can be expected by simplifying the process and reducing the film forming range. However, electroplating cannot be performed on ITO.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a capacitive touch panel and a method for manufacturing the same that can reduce the cost by simplifying the process and reducing the film deposition range of the conductor by employing plating for the wiring part of the capacitive touch panel. It is to be realized.

  The method of manufacturing a capacitive touch panel according to the present invention includes a first ITO deposition step, a first ITO patterning step, a first insulation film deposition step, a first insulation film patterning step, a second ITO deposition step, and a second ITO patterning step. A second insulating film deposition step, a second insulating film patterning step, and a plating step are performed.

  In the first ITO deposition step, a transparent first ITO film is deposited on a transparent substrate.

  In the first ITO patterning step, the first ITO layer is formed by patterning the first ITO film into the shape of a plurality of striped electrode portions and a plurality of wiring portions which are the respective lead wirings.

  In the first insulating film deposition step, a transparent insulating film is deposited on the first electrode layer.

  In the first insulating film patterning step, the first insulating layer is formed by patterning the first insulating film so that the electrode portion of the first electrode layer is covered and the wiring portion is exposed.

  In the second ITO deposition step, a transparent second ITO film is deposited on the first insulating layer.

  In the second ITO patterning step, the second ITO film is formed into a plurality of stripe-shaped electrode portions orthogonal to the plurality of electrode portions of the first electrode layer in a plan view and a plurality of wiring portions which are respective lead wires. A second electrode layer is formed by patterning.

  In the second insulating film deposition step, a transparent insulating film is deposited on the second electrode layer.

  In the second insulating film patterning step, the second insulating film is patterned to form a second insulating layer so that the electrode portion of the second electrode layer is covered and the wiring portion is exposed.

  In the plating step, electroless plating is performed on the wiring portion of the first electrode layer and the wiring portion of the second electrode layer.

  According to the capacitive touch panel and the manufacturing method thereof of the present invention, it is possible to apply plating on ITO by adopting electroless plating having good affinity with ITO for the wiring part of the capacitive touch panel. In addition, since ITO can be selectively plated without patterning, the cost can be reduced by simplifying the process and reducing the film deposition range of the conductor.

The top view and side view which show the structural example of the electrostatic capacitance type touch panel of this invention. The figure which shows the example of a manufacturing process of the electrostatic capacitance type touch panel of this invention. The figure which shows the state of the film-forming and patterning in the manufacturing process of the capacitive touch panel of this invention in steps. The top view and side view which show the structural example of the conventional electrostatic capacitance type touch panel. The figure which shows the manufacturing process example of the conventional electrostatic capacitance type touch panel.

[First Embodiment]
FIG. 1A is a plan view showing an example of the capacitive touch panel 200 of the present invention, and FIG. 1B is a side view seen from the left side of FIG. 1A. The capacitive touch panel 200 includes a substrate 101, a first electrode layer 102, a first insulating layer 103, a second electrode layer 104, a second insulating layer 105, a plating part 206, and a plating part 207. That is, the conventional capacitive touch panel 100 shown in FIG. 4 is similar in structure except that the first metal film 106 and the second metal film 107 are replaced with the plating part 206 and the plating part 207, respectively. Here, the plated portions 206 and 207 will be described.

  The plated portion 206 and the plated portion 207 are conductors that are superimposed on the respective wiring portions in order to reduce the resistance of the wiring portion 102b of the first electrode layer and the wiring portion 104b of the second electrode layer, respectively. This is the same as the first metal film 106 and the second metal film 107 of the conventional capacitive touch panel 100. However, in the present invention, electroless plating (for example, electroless Ni plating) having good affinity with ITO is employed instead of the metal film formed by sputtering or the like. Therefore, unlike the conventional capacitive touch panel 100, the material film is temporarily deposited and patterned on the entire first electrode layer even though only a part of the metal film should be left. In addition, since the electroless plating can be selectively applied to the ITO film, it is not necessary to go through a complicated process of depositing and patterning a metal film. Electroless plating is suitable for both a film substrate and a glass substrate.

  FIG. 2A shows an example of a manufacturing process of the capacitive touch panel 200 of the present invention. FIG. 3 shows a manufacturing state in the middle of the process. First, ITO is deposited on the transparent substrate 101 (S1), and the ITO film is patterned into the shape of the first electrode layer 102 (electrode portion 102a and wiring portion 102b) (S2, FIG. 3 (a)). . Subsequently, a transparent insulating film is deposited so as to be laminated thereon (S3), and the first insulating layer 103 is formed by patterning the insulating film so that the electrode portion 102a is covered and the wiring portion 102b is exposed. (S4, FIG. 3 (b)). Subsequently, ITO is deposited in a laminated manner (S5), and the ITO film is patterned into the shape of the second electrode layer 104 (electrode part 104a and wiring part 104b) (S6, FIG. 3 (c)). . Subsequently, a transparent insulating film is deposited so as to be laminated thereon (S7), and the insulating film is patterned to a shape in which the electrode portion 104a of the second electrode layer is covered and the wiring portion 104b is exposed to form a second insulating film. The layer 105 is formed (S8, FIG. 3 (d)). Then, the exposed wiring portion 102b and the wiring portion 104b are subjected to electroless plating to form a plating portion 206 and a plating portion 207 (S9, FIG. 3 (e)). Here, the thickness of the plated portion is preferably 0.05 μm or more in order to reduce the resistance. Moreover, although it is desirable to apply plating to both wiring parts, depending on the length of the wiring part, it may be applied to only one wiring part having a longer wiring length.

  Here, the case where the capacitive touch panel is configured by laminating both the first electrode layer and the second electrode layer on one side of the substrate has been described. However, the first electrode layer and the second electrode layer are formed on the substrate. It is also possible to sandwich the structure. In that case, what is necessary is just to perform S9 after performing said S1-S4 about each electrode layer.

  As described above, according to the capacitive touch panel 200 of the present invention, it is possible to perform plating on ITO by adopting electroless plating having good affinity with ITO for the wiring part of the capacitive touch panel. In addition, since ITO can be selectively plated without patterning, the cost can be reduced by simplifying the process and reducing the film deposition range of the conductor. Further, by simplifying the process, it is possible to manufacture even a simple matrix liquid crystal manufacturing line. Furthermore, if the formation of the ITO electrode and the formation of the insulating film (S1 to S8 above) are performed on a large substrate in multiple planes and the electroless plating process (S9) is performed after cutting into individual pieces, the production efficiency can be improved. Can do.

<Modification>
In the process shown in FIG. 2A, the plating process is performed after the electrode portion 104a of the second electrode layer 104 is covered with the second insulating layer 105 in the steps S7 and S8. Alternatively, a masking material such as a peeling film may be printed on the electrode portion 104a. FIG. 2B shows an example of the manufacturing process in this case. S1 to S6 are the same as those in FIG. Subsequently, a masking material is printed on the electrode portion 104a (S11), electroless plating is applied to the wiring portion to form a plating (S9), and finally the masking material is peeled off (S12).

  In the case of this modification, the electrode portion can be covered by simply forming the print without depositing and patterning the insulating layer, so that the process can be simplified. In this case, since there is no second insulating layer that plays a role of protecting the electrode portion 104a, it is necessary to provide some protection on the electrode portion 104a after S12. Since it is not necessary to form by patterning, the process can be simplified as a whole.

[Second Embodiment]
When the wiring portion is plated, if the distance between adjacent wiring portions is narrow, there is a possibility that a short circuit may occur between the wirings at the edge portion of the insulating layer. Therefore, when patterning the first electrode layer 102 and the second electrode layer 104, the distance d1 between the adjacent wiring portions is predetermined for the electrode portion vicinity portion 102b1 of the wiring portion 102b and the electrode portion vicinity portion 104b1 of the wiring portion 104b. Patterning is performed so as to be longer than the distance (for example, 5 to 6 mm). As a result, while avoiding short-circuits in the vicinity of the electrode part, the distance d2 is patterned as narrowly as possible (for example, 50 to 100 μm) in the other parts (102b2, 104b2), and optimal wiring in a limited space is achieved. Can be achieved.

[Third Embodiment]
As shown in FIG. 1A, the other end of each of the wiring portions 102b and 104b subjected to electroless plating is crimped and connected to a printed circuit board such as an FPC at the crimping portion 108. When ACF (anisotropic conductive film) is used, FPC is a metal and has a light-shielding property, and plating also has a light-shielding property. Therefore, in such a case, when electroless plating is performed, the electroless plating may be prevented from being applied to the portion to be crimped and connected to the printed board. For example, it is conceivable to perform electroless plating after printing a masking material such as a peelable peeling film on the portion corresponding to the crimping portion 108 of each wiring portion.

100, 200 Capacitive touch panel 101 Substrate 102 1st electrode layer 103 1st insulating layer 104 2nd electrode layer 105 2nd insulating layer 106 1st metal film 107 2nd metal film 108 Crimp part 206,207 Plated part

Claims (5)

A first ITO deposition step of depositing a transparent first ITO film on a transparent substrate;
A first ITO patterning step of patterning the first ITO film into the shape of a plurality of stripe-shaped electrode portions and a plurality of wiring portions which are respective lead wires, and forming a first electrode layer;
A first insulating film deposition step of depositing a transparent insulating film on the first electrode layer;
A first insulating film patterning step of patterning the first insulating film so that the electrode portion of the first electrode layer is covered and the wiring portion is exposed to form a first insulating layer;
A second ITO deposition step of depositing a transparent second ITO film on the first insulating layer;
The second ITO film is patterned into a plurality of stripe-shaped electrode portions that are orthogonal to the plurality of electrode portions of the first electrode layer in plan view and a plurality of wiring portions that are the respective lead wires. A second ITO patterning step to form a second electrode layer;
A second insulating film deposition step of depositing a transparent insulating film on the second electrode layer;
A second insulating film patterning step of patterning the second insulating film so that the electrode portion of the second electrode layer is covered and the wiring portion is exposed to form a second insulating layer;
A plating step of performing electroless plating on the wiring portion of the first electrode layer and the wiring portion of the second electrode layer;
The method for manufacturing a capacitive touch panel is characterized in that electroless plating is not performed on a portion of the wiring portion that is crimped and connected to the printed circuit board . A first ITO deposition step of depositing a transparent first ITO film on a transparent substrate;
A first ITO patterning step of patterning the first ITO film into the shape of a plurality of stripe-shaped electrode portions and a plurality of wiring portions which are respective lead wires, and forming a first electrode layer;
An insulating film deposition step of depositing a transparent insulating film on the first electrode layer;
An insulating film patterning step of forming the insulating layer by patterning the insulating film so that the electrode portion of the first electrode layer is covered and the wiring portion is exposed;
A second ITO deposition step of depositing a transparent second ITO film on the insulating layer;
The second ITO film is patterned into a plurality of stripe-shaped electrode portions that are orthogonal to the plurality of electrode portions of the first electrode layer in plan view and a plurality of wiring portions that are the respective lead wires. A second ITO patterning step to form a second electrode layer;
A masking step of printing a masking material on the second electrode layer so that the electrode part of the second electrode layer is covered and the wiring part is exposed;
A plating step of performing electroless plating on the wiring portion of the first electrode layer and the wiring portion of the second electrode layer;
A peeling step for peeling the masking material;
The method for manufacturing a capacitive touch panel is characterized in that electroless plating is not performed on a portion of the wiring portion that is crimped and connected to the printed circuit board . A method for manufacturing the capacitive touch panel according to claim 1, wherein:
The wiring part consists of a part near the electrode part and the other part,
In the first ITO patterning step and the second ITO patterning step, patterning is performed so that an interval between adjacent electrode portions in the vicinity of the electrode portion is longer than a predetermined distance. On a transparent substrate, a first electrode layer which is a transparent ITO film comprising a plurality of striped electrode portions and a plurality of wiring portions which are the respective lead wires, a transparent insulating layer, and the first electrode A second electrode layer, which is a transparent ITO film composed of a plurality of stripe-shaped electrode portions orthogonal to the electrode portion of the layer when viewed in plan, and a plurality of wiring portions that are the respective lead-out wirings are sequentially laminated. A capacitive touch panel that detects the position coordinates of the contact object from the capacitance between the contact object such as a finger and the electrode part of the first electrode layer and the electrode part of the second electrode layer. There,
Electroless plating is applied to at least one of the wiring portion of the first electrode layer and the wiring portion of the second electrode layer, and there is no portion of the wiring portion that performs crimping connection with a printed circuit board. A capacitive touch panel, characterized by not being electroplated . The capacitive touch panel according to claim 4 ,
The said wiring part consists of an electrode part vicinity part and a part other than that, and the space | interval of the electrode part vicinity part of each adjacent wiring part is longer than predetermined distance, The capacitive touch panel characterized by the above-mentioned.

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