JP5176764B2 - Data communication system, image processing system, and data communication method - Google Patents

Description

  The present invention relates to a data communication system, an image processing system, and a data communication method. More specifically, the present invention relates to a data communication system, an image processing system, and a data communication method in which a plurality of devices are connected via a high-speed serial switch fabric.

  In general, in an image system that handles image data and other data, for example, an information processing apparatus such as a digital copying machine or a multifunction peripheral (MFP), a PCI bus is used as an interface between devices. However, the parallel PCI bus has problems such as racing and skew, and the transfer rate has been low for use in high-speed and high-quality image forming apparatuses. The use of a high-speed serial interface such as IEEE1394 or USB is being considered in place of the parallel interface. For example, according to Patent Document 1, it is proposed to use a high-speed serial interface such as IEEE1394 or USB as an internal interface.

  As another high-speed serial interface, an interface called PCI Express (registered trademark), which is a successor to the PCI bus system, has been proposed and has been put to practical use (for example, see Non-Patent Document 1). This PCI Express system is schematically configured as a data communication network having a tree structure (tree structure) such as a root complex-switch (arbitrary hierarchy) -device as shown in FIG. Has been.

  In recent years, the Advanced Switching Interconnect standard, which is a high-speed serial switch fabric based on the PCI Express architecture, has been formulated. This Advanced Switching Interconnect is designed to support a wider range of applications while directly adopting the physical layer and link layer technologies of PCI Express high-speed serial transmission, and its connection target is Chip-to-Chip, Assume Board-to-Board. According to this Advanced Switching Interconnect, traffic can be differentiated (prioritized) by mapping a traffic class to a virtual channel.

  Based on these technologies, a switch-connected image system, such as a printer, which uses a high-speed serial switch fabric and can freely expand devices having different traffic of various properties to the high-speed serial switch fabric. And MFPs have also been proposed (Patent Documents 2 and 3).

  In addition, the means for detecting the path from the top to the bottom of the tree structure and the means for detecting the communication parameter in the path can be executed by the hardware means of the communication device, thereby simplifying the detection process. A method has been proposed (Patent Document 4).

Furthermore, in a system that configures the PCI Express architecture and performs serial communication, the packet data is monitored in real time by the statistical information generating means, and the monitored result is fed back to the weight information updating means, so that the serial communication path is A method is disclosed that enables prioritization according to the data transfer amount of actually transferred packet data, that is, a method for arbitrating priorities in real time (Patent Document 5).
JP 2001-016382 A JP 2007-065847 A JP 2005-354658 A JP 2006-211532 A JP 2007-249816 A "Outline of PCI Express standard" Interface magazine, July '2003 Naoshi Satomi

  However, if excessive traffic occurs instantaneously at one output port of a switch in a printer or MFP to which devices are connected via a plurality of switches, the traffic at different output ports is disturbed, which is the worst. In this case, there is a problem that an abnormal image is generated because the data transfer capability is lowered even for the traffic of another switch. Further, if the data transfer amount is adjusted in real time as in the prior art, excessive traffic that temporarily occurs at the start of data communication cannot be suppressed.

  The present invention has been made in view of the above problems, and avoids excessive traffic that occurs instantaneously in the system by notifying each device included in the communication path in advance of the communication path for data communication. An object of the present invention is to provide a data communication system, an image processing system, and a data communication method.

A data communication system according to one aspect of the present invention is a data communication using a data communication network having a tree structure in which nodes, which are switches or devices, are connected by a high-speed serial bus in which a communication channel transmitted and received point-to-point is established. The lower-level device, which is a lower-level device of the tree structure, performs communication information on a communication path between nodes on which data communication is performed at the top of the tree structure before data communication. A notification unit configured to notify a highest device which is a certain device, and the highest device includes a plurality of communication paths, a permissible bandwidth of a transmission path between the nodes, and a plurality of communications using ports of each node. holding means for holding the current band path is the sum of the bandwidth used by each of the notifying means Based on the current status bandwidth notified communication information and the holding means for holding said plurality of said tolerance band sum of the bandwidth used by each communication path using said port comprises a communication path indicated by the communication information Control means for controlling the bandwidth of the communication path so as not to exceed.

  The data communication system according to another aspect of the present invention uses a data communication network having a tree structure in which nodes as switches or devices are connected by a high-speed serial bus in which a communication channel transmitted and received point-to-point is established. A data communication system for performing data communication, comprising a control line for connecting each node so that data communication is possible, wherein the device included in a communication path for performing data communication is connected to the device, and is connected to the communication path. A notification means for notifying communication information relating to data communication to the switch included via the control line; and a control means for controlling the bandwidth of each communication path, the switch being connected to the switch Band holding means for holding communication band information relating to the band of each communication path communicated between nodes, and the notification State notification means for notifying the communication state information indicating the communication state of the band in each communication path updated based on the communication information notified by the stage via the control line, the control means, The bandwidth of each communication path is controlled based on the communication status information notified by the status notification means.

Further, another data communication method of the present invention uses a data communication network having a tree structure in which nodes as switches or devices are connected by a high-speed serial bus in which a communication channel transmitted and received point-to-point is established. A data communication system that performs communication, and the highest-level device, which is the highest-level device in the tree structure, includes a plurality of communication paths, an allowable bandwidth of a transmission path between the nodes, and a port included in each node. A data communication method in a data communication system having a holding means for holding a current band that is a sum of bands used in each of a plurality of communication paths to be used, between nodes where data communication is performed before data communication A notification step of notifying communication information about a communication path to the highest-level device; and the notification step. Based on the current status bandwidth notified communication information and the holding means for holding a plurality of said tolerance band is the sum of the bandwidth used by a communication path using said port comprises a communication path indicated by the communication information And a control step of controlling the bandwidth of the communication path so as not to exceed.

  Further, another data communication method of the present invention uses a data communication network having a tree structure in which nodes as switches or devices are connected by a high-speed serial bus in which a communication channel transmitted and received point-to-point is established. A data communication system for performing communication, and a data communication method in a data communication system including a control line for connecting each node so that data communication is possible, wherein the device included in a communication path through which data communication is performed is the device A notification step of notifying communication information relating to data communication to the switch included in the communication path via the control line, and the switch based on the communication information notified by the notification step Communication status information indicating the communication status of the bandwidth in each updated communication path A status notification step of notifying via the control line, the device is based on the notified communication state information by the status notification step, and a control step of controlling the bandwidth of each communication path.

  According to the present invention, a data communication system and an image forming apparatus capable of avoiding excessive traffic that occurs instantaneously in the system by notifying each device included in the communication path in advance of a communication path for data communication. A data communication method can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  Exemplary embodiments of a data communication system and a data communication method according to the present invention are explained in detail below with reference to the accompanying drawings.

  The best embodiment for carrying out the present invention will be described with reference to the drawings. In the following, details of PCI Express are explained in the [Outline of PCI Express Standard] to [Detailed Architecture of PCI Express] columns, and Advanced Switch Interconnect using PCI Express technology [What is Advanced Switch Interconnect] Description will be given in the section of [Characteristics of Advanced Switch Interconnect technology], and the present invention will be described in the columns of [Configuration of data communication system] to [Bandwidth control processing] and in the columns of each embodiment.

[Outline of PCI Express standard]
First, this embodiment uses PCI Express (registered trademark), which is one of high-speed serial buses. As a premise of this embodiment, an outline of the PCI Express standard is based on a partial excerpt from Non-Patent Document 1. explain. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In the existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect the PCI-X bridge 105a to the host bridge 103 to which the CPU 100, the AGP graphics 101, and the memory 102 are connected. Or a PCI bridge 105b to which the PCI devices 104c and 104d are connected and a PCI bridge 107 to which the PCI bus slot 106 is connected are connected via the PCI bridge 105c (tree structure). Yes.

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. The switch 117a connected by the PCI Express 114b is connected by the PCI Express 114c, and the PCI bridge 119 to which the switch 117b to which the end point 115b and the legacy end point 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected is a PCI. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  FIG. 3 is a block diagram illustrating an example of a PCI Express platform that is actually assumed. The example shown in FIG. 3 shows an example of application to desktop / mobile. For example, a graphics hub is connected to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. 125 is connected by a x16 PCI Express 126a, and an I / O hub 127 having a conversion function is connected by a PCI Express 126b.

  For example, a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Further, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c, and the mobile dock 135, the Gigabit Ethernet 136 (Ethernet is a registered trademark), and an add-in are connected to the switch 134 by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 is a diagram illustrating a structure example of the physical layer in the case of x4. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects component links in a one-to-one relationship (point-to-point). . The transfer rate is, for example, 2.5 Gbps in one direction. The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example.

  FIG. 5 is a diagram illustrating an example of lane connection between devices. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint does not request I / O resources in the BAR (Base Address Register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. FIG. 6 is a block diagram illustrating an example of the logical structure of the switch. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double-headed arrows indicate PCI Express links 114 (or 126), and 142a to 142d indicate ports.

  Of these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
FIG. 7A is a block diagram illustrating an existing PCI architecture. As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related, and there is no concept of hierarchy.

  FIG. 7-2 is a block diagram illustrating the architecture of PCI Express. As shown in FIG. 7-2, PCI Express has an independent hierarchical structure like a general communication protocol and InfiniBand, and specifications are defined for each layer. In other words, a transaction layer 153, a data link layer 154, and a physical layer 155 are provided between the uppermost software 151 and the lowermost mechanism (mechanical) unit 152.

  Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  FIG. 8 is a block diagram showing a PCI Express hierarchical structure. The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration employs a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the cross-point of the data signal. The system extracts the clock.

[Configuration space]
FIG. 10 is an explanatory diagram showing a PCI Express configuration space. PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes.

  As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address. The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS.

  The function of converting conventional access to PCI Express access is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header.

  As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions expanded by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (Express Cards), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) interrupt requests and confirmations are communicated by using messages as "virtual wires". ) And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. FIG. 9 is a diagram illustrating a format example of a transaction layer packet. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error). Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  FIG. 11 is a schematic diagram for explaining the concept of the virtual channel. A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed.

  Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed in order to avoid overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (mechanism to check the buffer availability on the receiving side before starting data transfer and prevent overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
FIG. 12 is a diagram illustrating a format example of a data link layer packet. The transaction layer packet (TLP) is automatically divided into data link layer packets (DLLP) as shown in FIG. 12 and transmitted to each lane when transmitted from the physical layer. A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). FIG. 13 is a diagram illustrating an example of byte striping in an x4 link. The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power Management and Link State FIG. 14 is a diagram showing the definition of the link state. In order to keep the power consumption of the link low, a link state of L0 / L0s / L1 / L2 is defined as shown in FIG. L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0.

  FIG. 15 is a time chart illustrating an example of control of active state power management. As shown in FIG. 15, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[What is Advanced Switch Interconnect]
Next, the present embodiment uses the Advanced Switch Interconnect utilizing the above-described PCI Express technology, and an outline of the Advanced Switch Interconnect will be described as a premise of the present embodiment.

  In recent years, the fusion of computing and communication has rapidly progressed against the background of advances in broadband and semiconductor technologies, and the emergence of standards that can be widely applied to new application systems is desired. Therefore, the ASI (Advanced Switching Interconnect) standard using the PCI Express technology has appeared, and it is assumed to be applied to a wide range of applications from computing to communication. The formulation and dissemination of ASI specifications is managed by a non-profit organization, Advanced Switching Interconnect Special Interest Group (ASI-SIG).

[Overview of Advanced Switch Interconnect technology]
Next, an overview of the Advanced Switch Interconnect technology will be described. First, the relationship between PCI Express and ASI (Advanced Switching Interconnect) will be described. FIG. 16 is a diagram illustrating a relationship between PCI Express and ASI (Advanced Switching Interconnect) protocol stacks.

  ASI (Advanced Switching Interconnect) is a technology that uses the physical layer and link layer technology of PCI Express high-speed serial transmission as it is, and is compatible with a wider range of applications. The connection target is Chip-to-Chip. , Board-to-Board is assumed.

  PCI Express inherits PCI transactions cultivated in computing as it is, but ASI (Advanced Switching Interconnect) has expanded the functions by replacing the transaction layer of PCI Express, and more advanced data flow and protocol It can be adapted to. In addition, the connection structure has been expanded from the PCI Express tree structure so that a fabric structure with a higher degree of freedom can be created, and it also supports a multi-CPU environment. In ASI (Advanced Switching Interconnect), the routing method is remarkably improved and higher speed than other standards (Ethernet (registered trademark), InfiniBand, etc.) capable of the same fabric structure is achieved.

  The fabric management function (AS Fabric Mngmnt) shown in Fig. 16 is part of the ASI (Advanced Switching Interconnect) protocol that is configured by software. Connection setup and removal, event management, performance and operational status monitoring, and redundant routes Supports various services such as path invalidation, resource allocation and load leveling. FIG. 17 is a diagram illustrating an initialization sequence in the fabric management function.

  FIG. 18 is a diagram illustrating protocol encapsulation in ASI. In ASI (Advanced Switching Interconnect), as shown in FIG. 18, by adopting a method of encapsulating various protocols, an attempt is made to increase the speed of more advanced protocol (TCP / IP, Fiber Channel, etc.) services. .

  An upper layer of ASI (Advanced Switching Interconnect) has a part called PEI (Protocol Encapsulation Interface), and has a function of adding an ASI header to various packets arrived from the outside and converting them into ASI packets. A packet that has passed through the ASI fabric is extracted as an original packet with the ASI header removed by the PEI on the receiving side. The upstream protocol interface is called PI (pi), and it adopts a mechanism that can support various standards and also implement AS Native and Vendor Specific protocols. A profile in which PCI Express and ASI (Advanced Switching Interconnect) are connected by a bridge and the PCI Express protocol is encapsulated and transferred is defined as PI-8.

[Features of Advanced Switch Interconnect technology]
ASI (Advanced Switching Interconnect) is a feature of PCI Express, in addition to the high speed, bandwidth scalability, physical layer expandability by hierarchical structure, data reliability, etc. ) Has its own characteristics.
・ Support for unreliable (lossy) packet transmission such as video ・ Multicast and broadcast packet support ・ Multiprotocol transmission by encapsulation ・ High-speed original path routing method ・ Support for congestion management function ・ Support for fabric structure FIG. 19 is a diagram showing storage and IO resource sharing between a plurality of devices by ASI. With the above-described features, storage and IO resources can be shared between a plurality of devices as shown in FIG. In addition, standards such as PCI, PCI-X, PCI Express, HyperTransport, RapidIO, and StarFabric have so far required complex connection means because the physical layer is different even if the same load / store protocol is used.

  FIG. 20 is a diagram illustrating an example of communication by ASI. By using ASI (Advanced Switching Interconnect) technology, mutual communication as shown in FIG. 20 can be realized simply, and the communication speed between devices is increased. It is also possible to construct a local system that realizes communication such as TCP / IP at a higher speed than ordinary Ethernet (registered trademark) processing by tunneling various upper protocols. Furthermore, it is possible to improve the robustness by providing the system with redundancy by adapting to the fabric structure or to dynamically switch the routing path.

  In addition, Advanced Switching Interconnect superimposes the physical layer and data link layer of PCI Express with an optimized transaction layer and provides various functions. A characteristic function of the transaction layer is multi-level QoS (Quality of Service). QoS supports 20 virtual channels (VCs) and 8 traffic classes (TCs).

  A fabric management function (AS Fabric Mngmnt), which is higher-order software that controls Advanced Switching Interconnect (ASI), can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) Perform independent flow control. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels.

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0.

  The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC). Also, in the ASI fabric, a Congestion state may occur due to excessive traffic. When falling into the Congestion state, there is a problem that the response time of the packet becomes long and a constant service level cannot be maintained. Therefore, in the ASI (Advanced Switching Interconnect) standard, this problem is solved by providing Status-Based Flow Control (SBFC) as a Congestion Management function.

  Here, Congestion Management will be specifically described with reference to FIG. As shown in FIG. 21A, when traffics 1 to 3 exist in three switches, it is assumed that traffic 1 and traffic 2 are initially performing desired data transfer. Here, it is assumed that excessive traffic exceeding the capability of port A is generated as traffic 3. This effect appears as a decrease in traffic 2 to the same output port A. Further, not only the traffic 2 but also the traffic of the traffic 1 passing through the same link as the traffic 2 is reduced.

Therefore, as shown in FIG. 21-2, the output of the traffic 2 can be suppressed by informing the adjacent switch that the port A is crowded using the SBFC. Is no longer affected. By the way, there are three types of ASI (Advanced Switching Interconnect) virtual channels (VC) as shown below.
BVC (Bypass Capable Unicast): VC Ids 0-7
OVC (Ordered-Only Unicast): VC Ids 8-15
MVC (Multicast): VC Ids 16-19
FIG. 22 is a schematic diagram for explaining BVC. As shown in FIG. 22, BVC (Bypass Capable Unicast) allows a previously input queue to be bypassed, and allows a queue input later to leave the arbiter (arbitration circuit).

  FIG. 23 is a schematic diagram for explaining OVC. In OVC (Ordered-Only Unicast), as shown in FIG. 23, the previously input Queue is output as it is.

  FIG. 24 is a schematic diagram for explaining the MVC. In MVC (Multicast), as shown in FIG. 24, an input Queue is output in a multicast manner. The configuration of the data communication system according to the present invention will be described below.

[Configuration of Data Communication System in Embodiment 1]
FIG. 25A is a diagram of a configuration example of the data communication system according to the first embodiment of the present invention. As shown in FIG. 25A, the data communication system includes a root complex 200 including a PCI Express root complex (top device) 200, switches 201 to 203, and devices 204 to 208 connected to a CPU and a memory. A data network is constructed in a tree structure as a top-level device.

  The root complex 200 has two root ports 1 and 2, and the tree structure with each root as a root is called a root port 1 side and a root port 2 side. In the PCI Express standard, these root ports 1 and 2 are called upstream ports and are basically located upstream of data communication.

  The switches 201 to 203 have a connection switching function for performing data communication in a point-to-point manner.

  FIG. 25-2 is a diagram illustrating an internal configuration example of the root complex 200. As shown in FIG. 25-2, in the present invention, in the bandwidth control means 300 and each root port, detailed information regarding the lower tree structure by hardware, that is, the configuration of the node, communication route (communication route), communication route Holding means 301 and 302 are provided for holding a current band, which is a sum of bands for each band, and an allowable band for a transmission path between nodes.

  The bandwidth control unit 300 controls the bandwidth of each communication route so as not to exceed the allowable bandwidth held by each holding unit. The bandwidth control means 300 may be configured to be provided in each root port.

  Returning to FIG. 25A, the switch 201 connected to the root port 1 side includes the data communication notifying unit 11, and the switch 202 connected to the root port 2 side similarly includes the data communication notifying unit. 21 is provided.

  The switch 201 having the data communication notifying unit 11 is connected to the switch 203 having the communication notifying unit 12 and the device 204 having the data communication notifying unit 13.

  Further, the device 203 having the data communication notifying unit 14 and the device 208 having the data communication notifying unit 15 are connected to the switch 203 having the data communication notifying unit 12.

  Similarly, the device 202 having the data communication notification unit 22 and the device 206 having the data communication notification unit 23 are connected to the switch 202 having the data communication notification unit 21. Each data communication means is configured by hardware.

  As described above, the configuration of the present invention has regularity and is very easy to implement. Specifically, hardware data communication notification means may be provided in the downstream port in the root complex 200 and in the upstream port in the switches and devices.

FIG. 26 is a diagram illustrating an example of a communication route on the root port 1 side and the root port 2 side in the first embodiment. FIG. 27 is a diagram illustrating a communication route on the side of the root port 2 and a communication route between devices via a switch according to the first embodiment. These two figures may be originally represented by one figure, but are divided into two figures for easy viewing. Now, assume that each communication route is assigned in order from A as follows.
[Root port 1 side]
A: Root port 1-switch 201-switch 203-device 207
B: Root port 1-switch 201-switch 203-device 208
C: Root port 1-Switch 201-Device 204
D: Device 207-Switch 203-Switch 201-Device 204
E: Device 208-Switch 203-Switch 201-Device 204
[Root port 2 side]
F: Root port 2-Switch 202-Device 205
G: Root port 2-Switch 202-Device 206
H: Device 205-Switch 202-Device 206
FIG. 28 is a diagram illustrating an example of data held by the holding unit. As shown in FIG. 28, the communication routes A to G are set in registers provided on the root port 1 side and the root port 2 side.

  In FIG. 28, 11 to 18 and 21 to 28 on the horizontal axis correspond to the data communication notification means, and 11 to 15 are used on the root port 1 side, and 21 to 23 are used on the root port 2 side. Show. The unassigned part can be expanded in the future.

  In the example shown in FIG. 28, the communication route is shown using the data communication means, but a switch or devices 201 to 208 may be used. Although the setting state is indicated by “◯”, this is qualitative, and it may be identified whether the flag is set or represented by a number.

  For example, referring to FIG. 28, it can be seen that the communication routes of FIGS. 26 and 27 are mapped to registers. Further, since the data communication notifying means knows its own band (allowable band) in advance, the information is also notified to the data communication notifying means on the side of the root port 1 and the transmission path included in the communication route is also notified. The allowable bandwidth is automatically written to the register by hardware.

  Note that register values automatically set by hardware can be operated from higher layers (drivers and applications) after register values are determined, that is, after configuration.

  In the example of FIG. 28, for example, the allowable bandwidth of the route (transmission path) 11 is 400, but when considering the balance of the entire system, for example, when it is desired to narrow the bandwidth at first due to current consumption, etc. It is also possible to change to 300. Of course, forcible writing from software is possible, but it is also possible to restore the initial value in a very short time, for example, several system clocks, by applying a hardware reset of the register.

  FIG. 29 is a diagram illustrating an example of a communication route at a certain time in the first embodiment. The device 204 and the device 207 communicate with each other through the communication route D, and the route complex 200 (the root port 1 side) and the device 208 communicate with each other through the communication route B. At the same time, the route complex 200 (route port 2 side) and the device 206 communicate with each other through the communication route G, and the device 205 and the device 206 communicate with each other through the communication route H.

  FIG. 30 is a diagram illustrating an example of a register value of a communication status of a communication route at a certain time in the first embodiment. As shown in FIG. 30, the communication status is stored in a register. At this time, unlike FIG. 28, a specific communication band is written in numerical values. As shown in this figure, the current bandwidth of all routes on the root port 1 side and the root port 2 side is less than the allowable bandwidth. Here, the current bandwidth is the sum of the communication routes A, B,... For each route 11, 12,.

  FIG. 31 is a diagram illustrating a state in which data communication is to be started using a new communication route. As shown in FIG. 31, data communication is newly started on communication route C and communication route F. First, a device (a device located at a lower level of the tree structure) or a root port that intends to newly use the root transmits a packet to be written to the register to the root port. The root port decrypts this and writes the decrypted value to the register. FIG. 32 shows a state after the decrypted value is written to the register.

  FIG. 32 is a diagram illustrating an example in which the requested bandwidth of the new route is overwritten in the register. As shown in FIG. 32, in the new route C, since 200 is requested as the bandwidth (requested bandwidth) to be used, first, the requested bandwidth 200 is overwritten in the corresponding register (see communication routes C 11 and 13). In addition, since 100 is requested as the bandwidth to be used in the new communication route F, first, the requested bandwidth 100 is overwritten in the corresponding register (see communication routes F 21 and 22).

  Here, as shown in FIG. 32, the current bandwidth 300 exceeds the allowable bandwidth 200 of the transmission path connected to the data communication notification means 13. At this time, the bandwidth control means 300 inside the route complex 200 controls the bandwidth so as not to exceed the allowable bandwidth for the new communication route C.

[Band Control Processing in Embodiment 1]
FIG. 33 is a flowchart for appropriately controlling the communication status in the first embodiment. In step 101, the device (the device located in the lower part of the tree structure) determines whether or not a data communication request has been received. If the determination result in step 101 is NO (no request is received), the process returns to step 101 and the same determination is made.

  If the determination result in step 101 is YES (requested), the process proceeds to step 102, where the data communication notification means of the device notifies (transmits) the route complex (top device) 200 with the communication route and the requested bandwidth as a packet. To do.

  Proceeding to step 103 following step 102, the root port of the root complex 200 decodes the packet, and writes the requested bandwidth obtained by the decryption to the corresponding register of the communication route obtained by the decryption. The register corresponds to holding means.

  Proceeding to step 104 following step 103, the root complex 200 determines whether or not the current bandwidth after the requested bandwidth is written to the register exceeds the allowable bandwidth.

  If the determination result in step 104 is YES (determined that it has exceeded), the process proceeds to step 105, and the bandwidth of each communication route is recalculated so as not to exceed the allowable bandwidth based on the requested bandwidth and the current bandwidth. The recalculated bandwidth is then overwritten in the register.

  Subsequent to step 105 or if the determination result in step 104 is NO (determined that it has not exceeded), the process proceeds to step 106, where the root port of the root complex is the bandwidth set in the register for each device of the communication route. To be notified.

  Proceeding to step 107 following step 106, the device set as the communication route starts data communication according to the notified band. In addition, when the bandwidth of the communication route is changed, the device that has already performed data communication continues data communication according to the bandwidth notified from the root port.

  The processing shown in FIG. 33 will be specifically described. When the processing in step 103 is completed, the state shown in FIG. 32 is obtained. At this time, the current band of the transmission path (hereinafter referred to as route 13) connected to the data communication notification unit 13 on the root port 1 side is connected to the data communication notification unit 22 on the root port 2 side by the processing of step 104. It can be seen that the current bandwidth of the transmission line (hereinafter referred to as route 22) exceeds the allowable bandwidth.

  Here, since the transmission path cannot flow data exceeding the allowable bandwidth, each communication route shares the data bandwidth in the same transmission path. For example, in the route 13, 100 is allowed for 200 requested bandwidths, and therefore 100 is written in the register. At this time, the same value is also written in the registers of other routes (transmission paths) passing through the communication route C, and it is checked whether each route (transmission path) exceeds the allowable bandwidth. If it exceeds, the same processing is performed again. In the route 22, 50 is allowed for 100 requested bandwidths, so 50 is written in the register.

  FIG. 34 is a diagram illustrating an example of register values after bandwidth control in the first embodiment. As shown in FIG. 34, “100” is written to the “11” and “13” registers of the communication route C, and “50” is written to the “21” and “22” registers of the communication route F. .

  Thus, bandwidth control that does not exceed the allowable bandwidth is possible. In the above-described example, the bandwidth is controlled only for the new communication route. However, the bandwidth of the communication route that is already performing data communication may be controlled. As a result, the current bandwidth should not exceed the allowable bandwidth.

  When the processing of step 105 shown in FIG. 33 is completed, the register values shown in FIG. 34 are written. Next, the value shown in FIG. 34 in the process of step 106 is notified to each related route as a packet.

  FIG. 35 is a diagram illustrating a state in which data communication is started through a new communication route in the first embodiment. According to the bandwidth notified in step 106 of FIG. 33, data communication is started for the new communication routes C and F. In addition, the existing communication routes B, D, G, and H are continuously performed until the data communication is completed. At this time, when a bandwidth change occurs in the existing communication route, data communication is continued according to the changed bandwidth.

  As described above, according to the data communication system according to the first embodiment, the data communication is started after presetting the usable bandwidth before starting the data transfer. Excessive traffic can be avoided.

  Further, after the data transfer is completed, there is a time allowance, and there is no need to urgently change the bandwidth or release the bandwidth, or if not required, the host may rewrite the register value by software control. In this method, the time required for setting is determined by the number of registers to be rewritten.

  On the other hand, if there is not enough time, and an urgent bandwidth change or bandwidth release is required or required, the initial value can be set by performing a hardware reset of the register as described above. It is possible to return. The shortest reset time is implemented by the hardware when the end of data transfer is detected. In this method, initialization is possible in a very short time of several clocks.

  The next shortest reset time is a method of applying a reset in software. In this method, the reset can be applied in several μs to several hundred μs. Note that the reset described here can be applied to all the registers, or can be applied only to the route where data communication has been completed. In such a case, it is not necessary to use a particularly difficult technique for mounting in hardware.

  Here, a case will be described where an error occurs when a packet including a requested bandwidth is transmitted to the root port based on the above-described procedure in order to newly start data communication in the first embodiment. When an error occurs, an error packet indicating that an error has occurred is sent from the root port, or the packet is not returned to the destination due to a lost packet. .

  When an error packet is received, the bandwidth request packet can be retransmitted and the subsequent correct procedure can be taken. If the packet does not return, if you wait for a certain period of time and then perform retransmission, you can follow the correct procedure. That is, unlike a mechanism that adjusts priority in real time as in the prior art, even if an error occurs during actual operation, data loss occurs in some traffic. Can be avoided.

  A data communication system according to the second embodiment will be described. The second embodiment is characterized in that priority is provided to each of the communication routes A to H.

  Since the configuration of the data communication system according to the second embodiment is the same as that of the first embodiment, a description thereof will be omitted. Differences in data held by the holding unit will be described below.

  FIG. 36 is a diagram illustrating an example of register values on the root port 1 side according to the second embodiment. FIG. 37 is a diagram illustrating an example of register values on the root port 2 side according to the second embodiment. 36 and 37, priority information is newly added.

  In the example shown in FIGS. 36 and 37, priority is provided, and a route is assigned in advance for each priority. In the example shown in FIG. 36 and FIG. 37, the priority 100 means that the communication route assigned here has priority over any other communication route (can be read as 100% usage rate). If this is the case, it means that the entire band can be used, and the priority can be set up to 80. The registers are the same except that priority is added compared to the case of the first embodiment. The priority value can be changed as appropriate.

  Next, FIG. 38 is a diagram illustrating an example of register values of the communication status on the side of the root port 1 at a certain time in the second embodiment. FIG. 39 is a diagram illustrating an example of a register value of the communication status on the side of the root port 2 at a certain time. In this situation, communication is newly started on the communication route C and the communication route F. First, the device or root port included in the new communication transmits a packet for writing to the register to the root port. The root port decrypts this, and writes the requested bandwidth obtained by the decryption to the register. The state after being written in the register is shown in FIGS.

  FIG. 40 is a diagram illustrating a state where the register value of the communication status on the side of the root port 1 in the second embodiment is overwritten. FIG. 41 is a diagram illustrating a state where the register value of the communication status on the side of the root port 2 in the second embodiment is overwritten. In the example shown in FIGS. 40 and 41, the requested bandwidth obtained by decoding the packet is overwritten as it is.

  FIG. 42 is a flowchart for appropriately processing the communication status according to the second embodiment according to the band. The processing shown in FIG. 42 that performs the same processing as in FIG. 33 is assigned the same reference numeral as in FIG.

  That is, since the process shown in FIG. 42 is different from the process shown in FIG. 33 in step 201 relating to the recalculation process of the current band, step 201 will be described below. Before the processing of step 201, the register state shown in FIGS.

  In step 201, the bandwidth control unit 300 of the highest device controls the bandwidth of the route 13 and the route 22 so as not to exceed the allowable bandwidth. Note that it is known that it is necessary to control the bandwidth of the route 13 and the route 22 by the processing in step 104.

  Next, the specific processing of step 201 will be described with reference to FIGS. Referring to FIG. 40, in route 13, communication route C requests bandwidth 200 with a priority of 80, but communication route D already uses bandwidth 100 with a priority of 20.

To use route 13 efficiently according to priority,
“Maximum allowable bandwidth in communication route C route 13”
= "Priority of communication route C" / ("Priority of communication route C" + "Priority of communication route D")
X “Allowable bandwidth of route 13” (1)
= 160
“Maximum allowable bandwidth in route 13 of communication route D”
= "Priority of communication route D" / ("Priority of communication route C" + "Priority of communication route D")
X “Allowable bandwidth of route 13” (2)
= 40
It becomes. A value calculated based on the weight obtained by using the priority of each communication route is a bandwidth allocated to each communication route. However, when the value calculated above exceeds the required bandwidth, the required bandwidth is set as the upper limit. In addition, the value calculated above is also reflected in the band on other transmission paths in the same communication route.

  FIG. 43 is a diagram illustrating an example of a registration value on the side of the root port 1 when the current bandwidth in the second embodiment is calculated based on the priority. FIG. 44 shows the above calculation applied to the root port 2 side.

  FIG. 44 is a diagram illustrating an example of a registration value on the side of the root port 2 when the current bandwidth in the second embodiment is calculated based on the priority. As shown in FIGS. 43 and 44, it can be seen that the current bandwidth, which is the sum of the bandwidths calculated based on the priority, does not exceed the allowable bandwidth.

  FIG. 45 is a diagram illustrating a state where communication is newly performed in the communication route C and the communication route F, and the communication band is reset in the communication route D and the communication route H, and communication is performed. When the process of step 107 in FIG. 42 ends, the state shown in FIG. 45 is obtained.

  As described above, when it is found that the data communication system in the second embodiment exceeds the allowable bandwidth before the start of data communication, based on the weight obtained using the priority given to each communication route, By calculating the bandwidth, the bandwidth can be controlled according to the importance of the communication route.

  An image processing system according to the third embodiment will be described. In the image processing system according to the third embodiment, the data communication system described in the above embodiment is applied to the data communication system of the image forming apparatus. First, the hardware configuration of the image forming apparatus will be described.

[Hardware configuration of image forming apparatus]
A hardware configuration of the image forming apparatus according to the third exemplary embodiment will be described. FIG. 46 is a diagram illustrating a schematic hardware configuration of the image forming apparatus according to the third embodiment.

  As shown in FIG. 46, the image forming apparatus 400 includes a control unit 401, a main storage unit 402, an auxiliary storage unit 403, a network I / F 404, a document storage unit 405, an input unit 406, a display unit 407, a plotter unit 408, a scanner. Part 409.

  The control unit 401 is a CPU that controls each device, calculates data, and processes in a computer. The control unit 401 is an arithmetic device that executes a program stored in the main storage unit 402. The control unit 401 receives data from the input device or the storage device, calculates and processes the data, and outputs the data to the output device or the storage device.

  The main storage unit 402 is a ROM (Read Only Memory), a RAM (Random Access Memory), or the like, and a storage device that stores or temporarily stores programs and data such as an OS and application software that are basic software executed by the control unit 401 It is.

  The auxiliary storage unit 403 is an HD (Hard Disk) or the like, and is a storage device that stores data related to application software and the like. The auxiliary storage unit 403 stores various information (for example, user information) managed by the image forming apparatus, and is managed by functions such as a database (DB: DataBase) and a file system (FS: File System). .

  The network I / F 404 is a peripheral device having a communication function connected via a network such as a LAN (Local Area Network) or a WAN (Wide Area Network) constructed by a data transmission path such as a wired and / or wireless line. An interface of the image forming apparatus. The document storage unit 405 is a document box or the like having a document storage function.

  The input unit 406 and the display unit 407 include a key switch (hard key) and an LCD (Liquid Crystal Display) having a touch panel function (including a GUI software key: Graphical User Interface), and the functions of the image forming apparatus It is a display and / or input device that functions as a UI (User Interface) when using.

  When the plotter unit 408 receives image data composed of C (cyan), M (magenta), Y (yellow), and K (black), it uses the inkjet method to transfer the received image data to a recording medium (printing paper). A plotter device that outputs (prints).

  A scanner unit 409 includes a line sensor composed of a CCD (Charge Coupled Devices) photoelectric conversion element, an A / D converter, and a drive circuit for driving them, and scans a document set on a document reading surface (on a contact glass). This is a reading device that generates digital image data of 8 bits for each of RGB (reads information from a document and digitizes it).

  As described above, the image forming apparatus executes a program stored in a storage device such as the main storage unit 402 or the auxiliary storage unit 403 by the control unit 401 and sends a control signal (control command) to each device (each By controlling the apparatus), applications such as copy, fax, scanner, and printer that the image forming apparatus has are realized, and information managed by the image forming apparatus or information managed in the system to which the image forming apparatus is connected Can be processed.

Further, as a general concept regarding printing, there are a printer and a copier. A printer refers to a function of outputting data acquired from a network or the like using a plotter without using a scanner. On the other hand, copier refers to a function of outputting data from a scanner using a plotter. These individual functions can be operated simultaneously in some combinations. For example, the following two operations correspond to the case where all these functions are operating simultaneously.
(Operation 1) Printer + Scanner + Facsimile + Document storage (Operation 2) Copier (floor & scanner) + Facsimile + Document storage Considering these two operations, it is necessary to devise appropriate measures to execute them without failure. Hereinafter, a case where the priority and allowable bandwidth in the registers of FIGS. 36 and 37 are applied to the MFP will be described. First, attach importance to each process. Arranging each process in order of importance,
(Operation 1) Printer>Scanner>Facsimile> Document storage (Operation 2) Copier (floor &scanner)>Facsimile> Document storage.

  In the case of operation 1, the importance of the printer is increased, and in the case of operation 2, the importance is increased. In the case of operation 2, it is further assumed that the plotter is more important than the scanner. That is, the “plotter” function is the most important. This is because if the data communication for the plotter is delayed, it immediately leads to a printing failure.

  Note that the facsimile is used exclusively with the plotter and the scanner, and the data can be stored in the storage unit inside the image forming apparatus. Therefore, the importance of each process is as described above. The importance described here can correspond to the priority and allowable bandwidth of the present invention.

  That is, since the communication route with the plotter has the highest importance, a large allowable bandwidth is allocated in advance, and conversely, a small allowable bandwidth is allocated for document storage. Furthermore, the priority in the register can be basically associated with the importance. Also, according to the situation, it is possible to increase the allowable bandwidth and set the priority to be low.

  Now, in a high-speed image forming apparatus, the plotter is a key component of the device, and is a device that is required to perform data communication at the highest speed. In some cases, data communication for other functions may be prioritized even if it is almost completely stopped. Therefore, the image processing system according to the third embodiment provides an optimum system for implementing this.

  Control of each function corresponding to the starting order is also important. For example, if it is assumed in the operation 1 that the functions are executed in order of decreasing importance, the operation of the document storage function is started first, and then the operation of the facsimile is started. If arbitration is required in the data communication inside the image forming apparatus, the data communication is performed so that the facsimile operation is prioritized.

  Next, when the scanner operation is started, data communication is performed so that the scanner operation has priority. Similarly, when the operation of the plotter is started, data communication is performed so that the plotter operates at the most important importance. As described above, the priority of the communication route according to the second embodiment can be configured in association with the importance of each process according to the third embodiment.

  In addition, it is preferable that the time for changing the setting of the importance is as short as possible. Therefore, in the third embodiment, since it is possible to realize setting change in hardware that takes less time than setting change in software, the setting change in hardware is adopted. In some cases, software settings can also be changed. By implementing software settings, it is possible to provide an optimal and flexible system for data communication settings. it can.

  As described above, in the image processing system according to the third embodiment, by applying the data communication system according to the present invention to the data communication system in the image forming apparatus, excessive traffic is instantaneously generated in the data communication process related to the image processing. Even this can be avoided. That is, when the data communication system according to the present invention is applied to the data communication system inside the image forming apparatus, it can be seen that it is very useful.

  A data communication system according to the fourth embodiment will be described. In the fourth embodiment, excessive traffic that occurs instantaneously can be avoided by newly providing a control line between the nodes and exchanging information related to data communication through the control line.

  FIG. 47 is a diagram illustrating the configuration of the data communication system according to the fourth embodiment. As shown in FIG. 47, the data communication system includes a route complex 500, switches 501-503, devices 504-508, high-speed serial buses 31-35, 41-43, control lines 511-515, 521-523. Is done.

  In the data communication system according to the fourth embodiment, the nodes are connected by a control line in addition to connecting the nodes by a high-speed serial bus.

  As shown in FIG. 47, the data communication system has a PCI Express root complex (top device) 500 connected to a CPU and a memory. The root complex 500 has two root ports, which are called the root port 1 side and the root port 2 side, respectively. In addition, a data network is constructed in a tree structure with the root complex 500 as the highest device.

  The root complex 500 has two root ports 1 and 2, which are called a root port 1 side and a root port 2 side, respectively. In the PCI Express standard, these are called upstream ports and are basically located upstream of data communication.

  The switches 501 to 503 have a connection switching function for performing data communication in a point-to-point manner.

  FIG. 48 is a diagram illustrating an internal configuration of a switch and a device. As shown in FIG. 48, in the data communication system according to the fourth embodiment, in each switch, a band holding unit 601 that holds communication band information related to a communication band at each node, a calculation unit 602 that calculates a communication band, and a band update Updating means 603 for performing communication, and state notifying means 604 for notifying the communication state of the communication band at that time.

  As shown in FIG. 48, each root port and / or device has a notification means 605 for notifying information related to data communication and a band control means 606 for controlling the communication band.

  FIG. 48A shows the internal structure of the switch. Band holding means 601 holds the band of the transmission path (high-speed serial bus) connected to the switch. For example, for each transmission path, the information “band” “100” is stored in the communication route A and the band “0” is stored in the other communication routes.

  When the communication unit 602 acquires communication information from the device via the control line, the calculation unit 602 calculates how to set the bandwidth of the transmission path for each communication route. For example, since only the communication route A was used for the transmission line 31, a bandwidth of 100% was set. However, when the acquired communication information shows that the communication route B is also used for the transmission line, The bandwidth is calculated so that the communication route A has a 50% bandwidth and the communication route B has a 50% bandwidth.

  Note that when the priority is set for each communication route, for example, when the communication route A is set to give twice as much bandwidth as the other communication routes, the computing unit 602 has priority information. The band to be set is calculated based on

  The updating unit 603 writes (updates) the band calculated and set by the calculating unit 602 in the band holding unit 601. As a result, the latest communication state of the transmission path is held in the band holding means 601.

  When the communication information is acquired from the device via the control line, the status notification unit 604 notifies the device of the communication status information of the transmission path updated by the update unit 603. The communication state information of the transmission path is information indicating how much bandwidth is set for each communication route. The communication status information can be obtained from information held in the band holding means 601.

  FIG. 48B shows the internal structure of the device. The notifying unit 605 notifies the communication information indicating that communication is to be performed via the control line to the switch included in the communication route through which data communication is to be performed.

  When acquiring the communication status information from the switch, the bandwidth control unit 606 controls the bandwidth of each communication route according to the bandwidth indicated by the communication status information.

  Here, since the point-to-point bandwidth is uniquely determined for the computing means 602 in the PCI Express standard, the total bandwidth is constant when data from two or more paths is transmitted / received to a specific transmission path. It means that it becomes.

  On the other hand, the data communication system according to the fourth embodiment keeps in mind that each band can be individually controlled when there are a plurality of data communication routes. For example, it is assumed that there are two communication routes A and B in a certain transmission line, and a bandwidth twice as large as the communication route B is allocated to the communication route A. When only data from the communication route A is transmitted / received, the communication route B is not used, so the entire bandwidth of the transmission path is assigned to the communication route A. If data from the communication route B is also started to be transmitted / received, approximately two-thirds of the total bandwidth is allocated to the communication route A, and approximately one-third of the bandwidth is allocated to the communication route B.

  Furthermore, the fourth embodiment includes control lines 511 to 515 and 521 to 523 associated with each transmission path in a one-to-one manner, separately from the transmission paths 31 to 35 and 41 to 43 in the PCI Express standard.

  Next, the bit assignment of the control line in the fourth embodiment will be described. Since the control line 511 has two transmission lines 32 and 33 on the downstream side from the switch 501, two bits are assigned, one bit each. The control line 512 is assigned a total of 4 bits because there are two transmission lines, one transmission line 31 on the upstream side, one transmission line 33 on the same level, and two transmission lines 34 and 35 on the downstream side.

  Since the control line 513 has one transmission line 31 on the upstream side and one transmission line 32 on the same level, a total of 2 bits are allocated. Since the control line 514 has one transmission line 32 on the upstream side and one transmission line 35 on the same level, a total of 2 bits are allocated. Since the control line 515 is the same as the control line 514, 2 bits are allocated.

  Since the control line 521 has two transmission lines 42 and 43 downstream from the switch 502, two bits are assigned, one for each. Since the control line 522 has one transmission line 41 on the upstream side and one transmission line 43 at the same level, a total of 2 bits are allocated. Since the control line 523 is the same as the control line 522, 2 bits are allocated.

FIG. 49 is a diagram illustrating a communication route on the side of the root port 1 in the fourth embodiment. FIG. 50 is a diagram illustrating a communication route on the side of the root port 2 and a communication route between devices via a switch according to the fourth embodiment. 49 and 50 may originally be represented by one figure, but are divided into two figures for easy viewing. Now, each communication route is assigned in order from A as follows.
[Root port 1 side]
A: Root port 1-switch 501-switch 503-device 507
B: Root port 1-switch 501-switch 503-device 508
C: Root port 1-Switch 501-Device 504
D: Device 507-Switch 503-Switch 501-Device 504
E: Device 508-Switch 503-Switch 501-Device 504
[Root port 2 side]
F: Root port 2-Switch 502-Device 505
G: Root port 2-Switch 502-Device 506
H: Device 505-Switch 502-Device 506
As described above, depending on the communication route, it can be seen that data is transmitted and received in a considerably complicated manner.

  FIG. 51 is a diagram illustrating an example of a communication state at a certain time in the fourth embodiment. The device 503 and the device 504 communicate with each other through the communication route D, and the device 505 communicates with the root port 1 side through the communication route B.

At the same time, the root port 2 side communicates with the device 506 through the communication route G, and the device 505 communicates with the device 506 through the communication route H. The state of each control line at this time is as follows.
511: 32 = on / 33 = off 512: 31 = on / 33 = on / 34 = on / 35 = on 513: 31 = off / 32 = on 514: 32 = on / 35 = off 515: 32 = on / 34 = off 521: 42 = off / 43 = on 522: 41 = off / 43 = on 523: 41 = on / 42 = on “On” represents a state in which data communication is performed, and “off” represents data Indicates that no communication is taking place. To make the above notation easy to understand, rewriting the above with “ON” as “◯” and “OFF” as “X”, the following is obtained.
511: 32 = ○ / 33 = ×
512: 31 = O / 33 = O / 34 = O / 35 = O
513: 31 = × / 32 = ○
514: 32 = ○ / 35 = ×
515: 32 = ○ / 34 = ×
521: 42 = × / 43 = ○
522: 41 = × / 43 = ○
523: 41 = ○ / 42 = ○
As is clear from the above, since all the communication routes are used in the control line 512, if a bandwidth is allocated in advance to each of the communication routes 31, 33, 34 and 35, excessive traffic is instantaneously generated in the system. Even if there is a possibility of occurrence, data communication is performed according to a predetermined band, so that a communication system that does not fail in data transmission / reception can be obtained.

  That is, when a new data communication is performed from now on, a communication including a new communication route is performed by a route port or device on the new communication route notifying the switch of communication information using the notification means 603 shown in FIG. A bandwidth that does not cause a failure in data transmission / reception can be set in advance for the route.

  A case where data communication is started using a new communication route will be described. FIG. 52 is a diagram illustrating a state when data communication is started using a new route according to the fourth embodiment.

  First, a device or a root port that intends to perform data communication through the new communication route C asserts the transmission line 33 of the control line 511 and the transmission line 31 of the control line 513. In addition, a device or a root port that intends to perform data communication using the new communication route F asserts the transmission path 42 of the control line 521 and the transmission path 41 of the control line 522.

  As described above, when there are more than two communication links that have only had a single communication route so far, data transmission / reception is performed according to a pre-assigned bandwidth, which may cause excessive traffic instantaneously in the system. Even if there is a characteristic, since it is configured to avoid this, it is possible to obtain a communication system that does not cause a failure in data transmission / reception.

  As described above, according to the data communication system according to the fourth embodiment, each switch knows the communication state in each communication route, so that the bandwidth that can be used by each communication route is set in advance before data communication. Temporary excessive traffic that may occur at the start can be avoided.

  As for bandwidth control of the transmission line connecting the switches, it may be determined in advance that either one calculates and sets the bandwidth and the other performs bandwidth control according to the set bandwidth. For example, if two switches are in an upstream / downstream relationship, the upstream switch calculates and sets the bandwidth, the downstream switch performs bandwidth control, and if the two switches are at the same level, The calling side switch may calculate and set the bandwidth, and the called side switch may perform bandwidth control.

  A data communication system according to the fifth embodiment will be described. In the fifth embodiment, the notification unit 605 can specify a band to be used numerically via a control line.

  In the first embodiment, the notification unit 605 only notifies information about which communication route is used as communication information. In the fifth embodiment, the notification unit 605 uses the bandwidth used for communication information. It is possible to notify including the numerical value of. Therefore, for example, an 8-bit control signal line is assigned to each control line for each communication route so that the band can be designated numerically.

  The computing means 603 sets the bandwidth of the new communication route based on the acquired bandwidth value. If the obtained bandwidth value is used as it is, it will exceed the allowable bandwidth, giving priority to the bandwidth of the new communication route and reducing the bandwidth of other currently used communication routes so that the allowable bandwidth is not exceeded. Also good.

  As described above, according to the data communication system according to the fifth embodiment, data communication can be performed in a band desired by the new communication route by designating numerically the bandwidth of the communication route to be used. At this time, the bandwidth may be controlled so that the bandwidth of the new communication route is set with priority over the currently used communication route.

  A data communication system according to the sixth embodiment will be described. In the sixth embodiment, even after the bandwidth in the transmission path is set once, the bandwidth can be changed when a predetermined condition is satisfied.

  In the sixth embodiment, when the bandwidth of each communication route is updated based on the bandwidth calculated by the calculation unit 602, the band can be changed before the communication information is notified from the notification unit 605 next time.

  For example, it is assumed that there is a transmission path originally used by the communication routes A, B, and D. Each communication route performs communication using bandwidths of 30%, 30%, and 40%, respectively. At this time, it is assumed that the data communication of the route D is completed. When detecting that the data communication of the communication route D has been completed or notified from another device, the calculating means 602 calculates and sets 50% bandwidths for the communication routes A and B, respectively. In addition, when priority is set for the communication route, the bandwidth may be calculated based on the priority.

  As described above, according to the data communication system according to the sixth embodiment, even when the bandwidth is once set (controlled), the bandwidth is changed again when the situation changes or the predetermined condition is satisfied. Can be used efficiently to perform data communication.

  A data communication system according to the seventh embodiment will be described. In the seventh embodiment, the bandwidth of each communication route is controlled in parallel with data communication.

  The notification unit 605 according to the seventh embodiment notifies the switch of communication information via the control line at the same time or after the start of data communication. When the switch acquires the communication information, the calculation unit 602 calculates the bandwidth of each communication route in parallel with the data communication.

  The bandwidth calculated and set by the computing means 602 is overwritten (updated) on the bandwidth holding means 601 by the updating means 603. Next, the status notification unit 604 notifies the device of the updated bandwidth of each communication route as communication status information. The device notified of the communication status information controls the bandwidth indicated by the communication status information by the bandwidth control unit 606 and continues data communication of each communication route.

  As described above, according to the data communication system according to the seventh embodiment, by controlling the bandwidth of each communication route in parallel with the data communication, it is possible to prevent a decrease in data communication capability without delaying the data communication timing. Can do.

  An image processing system according to the eighth embodiment will be described. In the eighth embodiment, each data communication system described in the fourth to seventh embodiments is applied to the data communication system of the image forming apparatus described in the third embodiment.

  As described in the third embodiment, in an image processing system, real-time performance is extremely important, such as processing that does not require real-time performance such as image processing such as compression, expansion, and rotation, and plot-out processing. Various processes with different priorities are mixed. Therefore, if the data communication systems described in the fourth to seventh embodiments are applied to this image processing system, an image system in which no abnormal image occurs can be obtained.

The block diagram which shows the structural example of the existing PCI system. The block diagram which shows the structural example of a PCI Express system. The block diagram which shows the structural example of the PCI Express platform by desktop / mobile. The schematic diagram which shows the structural example of the physical layer in the case of x4. The schematic diagram which shows the example of lane connection between devices. The block diagram which shows the logical structural example of a switch. Block diagram showing the existing PCI architecture. The block diagram which shows the architecture of PCI Express. The block diagram which shows the hierarchical structure of PCI Express. Explanatory drawing which shows the example of a format of a transaction layer packet. Explanatory drawing which shows the configuration space of PCI Express. The schematic diagram for demonstrating the concept of a virtual channel. Explanatory drawing which shows the example of a format of a data link layer packet. The schematic diagram which shows the example of byte striping in x4 link. Explanatory drawing explaining the definition of the link state of L0 / L0s / L1 / L2. The time chart which shows the control example of active state power management. Explanatory drawing which shows the relationship between PCI Express architecture and Advanced Switching Interconnect. Explanatory drawing which shows the initialization sequence in a fabric management function. Explanatory drawing which shows the encapsulation of the protocol in Advanced Switching Interconnect. Explanatory drawing which shows the sharing of the storage and IO resource between several devices by Advanced Switching Interconnect. Explanatory drawing which shows the example of communication by Advanced Switching Interconnect. Explanatory drawing which shows Congestion Management. Explanatory drawing which shows Congestion Management. The schematic diagram for demonstrating BVC (Bypass Capable Unicast). The schematic diagram for demonstrating OVC (Ordered-Only Unicast). The schematic diagram for demonstrating MVC (Multicast). 1 is a diagram showing a system configuration in Embodiment 1. FIG. FIG. 3 is a diagram illustrating an internal configuration example of a Root Complex in the first embodiment. The figure which shows the root | route of the Root Complex port 1 side in Example 1. FIG. FIG. 3 is a diagram illustrating a route on the Root Complex port 2 side and a communication route between devices via a switch in the first embodiment. 6 is a diagram illustrating an example of data held by a holding unit in Embodiment 1. FIG. The figure which shows an example of the communication route in a certain time in Example 1. FIG. The figure which shows an example of the register value of the communication condition of the communication route in a certain time in Example 1. FIG. The figure which shows the state which is going to start communication by the new communication route in Example 1. FIG. The figure which shows the state in which the register value of the communication condition of the root port 1 and the root port 2 side was overwritten in Example 1. FIG. 5 is a flowchart for appropriately processing a communication state according to a band in the first embodiment. FIG. 34 is a diagram illustrating a state in which values calculated according to the flowchart of FIG. 33 are set in the root port 1 side and root port 2 side registers in the first embodiment. The figure which shows the state in which communication was started by the new communication route in Example 1. FIG. FIG. 10 is a diagram illustrating an example of a register that holds each root number, each priority, an allowable band, and a current band on the side of the root port 1 in Example 2, and an initial setting value for the register. FIG. 6 is a diagram illustrating an example of a register that holds each route number, each priority, an allowable band, and a current band on the root port 2 side in the second embodiment, and an initial setting value for the register. The figure which shows an example of the register value of the communication condition of the root port 1 side in a certain time in Example 2. FIG. The figure which shows an example of the register value of the communication condition of the root port 2 side in a certain time in Example 2. FIG. The figure which shows the state in which the register value of the communication condition by the side of the root port 1 was overwritten in Example 2. FIG. The figure which shows the state in which the register value of the communication condition of the root port 2 side was overwritten in Example 2. FIG. 9 is a flowchart for appropriately processing a communication state according to a band in the second embodiment. The figure which shows an example of the register value by the side of the root port 1 when the present zone | band is calculated based on a priority in Example 2. FIG. The figure which shows an example of the register value by the side of the root port 2 when the present zone | band is calculated based on a priority in Example 2. FIG. The figure which shows the state in which the communication band is newly reset in the route C and the route F in Example 2, and the communication band is reset in the route D and the route H. FIG. 10 is a diagram illustrating a hardware configuration of an image forming apparatus according to a third embodiment. FIG. 10 is a diagram illustrating an example of a system configuration in a fourth embodiment. The figure which shows the internal structural example of a switch and a device. The figure which shows the communication route of the root port 1 side in Example 4. FIG. The figure which shows the communication route of the root port 2 side in Example 4, and the communication route of the devices via a switch. The figure which shows an example of the communication route in a certain time in Example 4. FIG. The figure which shows the state which is going to start data communication by the new communication route in Example 4. FIG.

Explanation of symbols

1, 2, Root port 11, 12, 13, 14, 15 Data communication notification means 21, 22, 23 Data communication notification means 200, 500 Route complex 201, 202, 203 Switch 204, 205, 206, 207, 208 Device 300 Bandwidth Control unit 301, 302 Holding unit 400 Image forming apparatus 501, 502, 503 Switch 504, 505, 506, 507, 508 Device 511, 512, 513, 514, 515, 521, 522, 523 Control circuit 601 Band holding unit 602 Calculation Means 603 Update means 604 Status notification means 605 Notification means 606 Band control means

Claims (10)

A data communication system that performs data communication using a data communication network having a tree structure in which nodes that are switches or devices are connected by a high-speed serial bus that establishes a communication channel that is transmitted point-to-point,
Subordinate devices that are subordinate devices of the tree structure are:
Prior to data communication, comprising a notification means for notifying communication information relating to a communication path between nodes where data communication is performed to a highest-level device which is a device at the highest level of the tree structure;
The top-level device is
Holding means for holding a plurality of communication paths, a permissible band of a transmission path between each node, and a current band that is a sum of bands used in each of a plurality of communication paths using a port of each node;
Based on the communication information notified by the notification means and the current bandwidth held by the holding means , the sum of the bands used in each of the plurality of communication paths including the communication path indicated by the communication information and using the port A data communication system comprising: control means for controlling a bandwidth of the communication path so that does not exceed the allowable bandwidth. The communication information includes a requested bandwidth indicating a bandwidth requested in a communication path through which data communication is performed,
The control means includes
The data communication system according to claim 1, wherein it is determined whether or not a bandwidth obtained by adding the requested bandwidth to the current bandwidth exceeds the allowable bandwidth, and when the bandwidth exceeds the allowable bandwidth, the bandwidth of the communication path is controlled. The holding means is
Further hold the priority set for each communication path,
The control means includes
The data communication system according to claim 2, wherein when the result of the determination exceeds the allowable bandwidth, the bandwidth of each communication path is controlled based on the priority and the allowable bandwidth. The control means includes
For the allowable bandwidth, the maximum usable bandwidth in each communication path is calculated based on the weight obtained by the priority of each communication path, and the bandwidth of each communication path is controlled based on the calculated bandwidth. The data communication system according to claim 3. A data communication system that performs data communication using a data communication network having a tree structure in which nodes that are switches or devices are connected by a high-speed serial bus that establishes a communication channel that is transmitted point-to-point,
It has a control line that connects each node so that data communication is possible,
The device included in a communication path through which data communication is performed is:
Notifying means connected to the device and notifying the switch included in the communication path of communication information related to data communication via the control line;
Control means for controlling the bandwidth of each communication path,
The switch is
Bandwidth holding means for holding communication bandwidth information relating to bandwidths of a plurality of communication paths communicated between nodes connected to the switch;
State notification means for notifying, via the control line, communication state information indicating communication states of bands in a plurality of communication paths updated based on the communication information notified by the notification means;
The control means includes
A data communication system for controlling bandwidths of a plurality of communication paths based on communication state information notified by the state notification means. The communication information includes numerical information indicating a band when data communication is performed on the communication path,
When the switch acquires the numerical information,
The band holding means includes
The data communication system according to claim 5, wherein the communication band information updated based on the numerical information is held. The switch is
When the communication information is acquired, calculation means for calculating the bandwidth of each communication path based on the acquired communication information,
The data communication system according to claim 5, further comprising an update unit that updates a communication state of the band based on the band calculated by the calculation unit.   An image processing system in which the data communication system according to claim 1 is applied to a data communication system inside an image forming apparatus. A data communication system for performing data communication using a data communication network having a tree structure in which nodes, which are switches or devices, are connected by a high-speed serial bus in which a communication channel transmitted and received point-to-point is established. The highest-level device, which is the highest-level device in the structure, includes a plurality of communication paths, a permissible bandwidth of a transmission path between each node, and a band used in each of a plurality of communication paths using a port of each node. A data communication method in a data communication system including a holding unit that holds a current bandwidth that is a sum of
Prior to data communication, a notification step of notifying the highest-level device of communication information regarding a communication path between nodes in which data communication is performed;
Based on the communication information notified by the notification step and the current band held by the holding unit, a sum of bands used in a plurality of communication paths including the communication path indicated by the communication information and using the port is calculated. A control step of controlling the bandwidth of the communication path so as not to exceed the allowable bandwidth;
A data communication method comprising: A data communication system that performs data communication using a data communication network having a tree structure in which nodes that are switches or devices are connected by a high-speed serial bus that establishes a communication channel that is transmitted and received point-to-point. A data communication method in a data communication system comprising a control line for connecting data communication possible,
A notification step in which the device included in a communication path in which data communication is performed is connected to the device and notifies the switch included in the communication path of communication information related to data communication via the control line;
A state notification step of notifying, via the control line, communication state information indicating communication states of bands in a plurality of communication paths updated based on the communication information notified by the notification step;
A data communication method comprising: a control step in which the device controls bandwidths of a plurality of communication paths based on the communication state information notified in the state notification step.

Images