JP5182011B2 - Semiconductor device and test method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a semiconductor device test method.

  In recent years, electronic devices are required to reduce power consumption from the viewpoint of environmental problems. Among portable electronic devices, a portable electronic device is supplied with a power supply voltage by a battery or the like during use, and the operation time of the portable electronic device depends on power consumption. For this reason, especially in portable electronic devices, low power consumption is required. Along with this, semiconductor devices (LSIs) mounted on electronic devices are also required to reduce power consumption.

  Under these circumstances, the ratio of leakage current to the current consumption of the entire circuit has been increasing as semiconductor miniaturization technology and operating voltage have been lowered in recent years. Conventionally, power gating is known as a technique for reducing leakage current.

Power gating is a technique for supplying a power supply voltage to a functional block in the active mode and stopping the supply of the power supply voltage to the functional block in the standby mode.
More specifically, the LSI is divided into a plurality of functional blocks having different functions. In the LSI, for a functional block that is a target of power gating among a plurality of functional blocks, a power cutoff circuit is provided between the functional block and a power source that supplies a power source voltage. In the active mode, the power cut-off circuit connects a functional block that is a target of power gating and a power supply, and supplies a power supply voltage to the functional block. On the contrary, in the standby mode, the power cutoff circuit shuts off the function block that is the target of power gating and the power supply, and stops the supply of the power supply voltage to the function block.

That is, the LSI can reduce the leakage current of the functional block that is the target of power gating in the standby state, and thus can reduce power consumption.
By the way, a test described below is known as a test of a power shut-off circuit that performs power gating (hereinafter referred to as a power shut-off test) (see, for example, Patent Document 1).

  An LSI for which a power shut-off test is performed includes a functional block scan chain and a power shut-off scan chain. Here, the scan chain is a chain in which flip-flop circuits are connected in series in order to test whether or not a flip-flop circuit formed in an LSI is faulty.

  Then, a test pattern and a clock are input to the scan chain in the power interruption test. Next, the scan chain sequentially reads the input test pattern from the scan chain in synchronization with the clock, and compares the read data with the same test pattern as the input test pattern. Subsequently, if inconsistent data is found in the comparison result, a faulty flip-flop circuit is specified based on the inconsistent data.

  The functional block scan chain connects flip-flop circuits formed in the functional block in series and tests whether or not the flip-flop circuit is faulty. The power shut-off scan chain connects flip-flop circuits that control supply / stop of the power supply voltage to the functional block in series and tests whether or not the flip-flop circuit is faulty.

  Since the LSI configured the functional block scan chain and the power shut-off scan chain separately, when testing the functional block scan chain, the flip-flop circuit constituting the power shut-off scan chain uses the power supply voltage to the functional block. It is possible to maintain the supply / stop settings. In other words, when the supply of power supply voltage to the function block scan chain is stopped, the power supply voltage is supplied to the power cutoff scan chain, so the setting of supply / stop of the power supply voltage of the function block is retained. ing.

  Therefore, the power shut-off scan chain inputs a test pattern for setting power supply voltage supply / stop of the functional block. The power shut-off scan chain controls the power supply voltage of the functional block based on the input test pattern for supplying / stopping the power supply voltage of the functional block. At this time, the tester device measures the power supply voltage of the functional block at each time. Then, the tester device compares the power supply voltage of the functional block based on the test pattern input to the power shut-off scan chain with the measured power supply voltage of the functional block to determine whether they match.

In other words, if the power supply voltage of the functional block based on the test pattern input to the power supply shut-off scan chain matches the measured power supply voltage of the functional block, the tester device confirms that the power supply cutoff circuit is properly connected to the power supply. Pass is determined as being able to block the functional block. On the other hand, if the power supply voltage of the functional block based on the test pattern input to the power-off scan chain and the measured power supply voltage of the functional block do not match, the tester device has And it is determined as Fail because the function block cannot be blocked.
JP 2006-170663 A

  However, since the power shut-off test uses a power shut-off scan chain, a lot of man-hours are required for generating a test pattern. In addition, the area for the power-supply cutoff scan chain is increased.

  An object of the semiconductor device and the semiconductor device testing method is to easily perform a power-off test while reducing a circuit area.

The semiconductor device is provided between the that function block having a scan chain including a plurality of flip-flop circuits connected in series, the pre-Symbol function block and the power supply wiring, the power supply voltage to the functional block A power cutoff circuit for controlling supply , an output signal of the scan chain included in the functional block, and the power supply voltage are input, the output signal of the scan chain is compared with the power supply voltage, and a comparison result is output. In the test mode, the power shutoff circuit shuts off the supply of the power supply voltage to the functional block when the output signal of the scan chain is in a high potential logic state .

According to this semiconductor device, the test circuit compares the power supply voltage with the output signal from the existing scan chain of the functional block. Based on the comparison result of the test circuit, the tester device determines whether the power shutoff circuit is able to block the power supply voltage and the functional blocks.

  The disclosed semiconductor device and semiconductor device testing method can easily perform a power-off test while reducing the circuit area.

A first embodiment embodying the present invention will be described below with reference to FIG.
FIG. 1 is an electric block circuit diagram of a semiconductor device (LSI) 10 of this embodiment.
As shown in FIG. 1, the LSI 10 includes first and second functional blocks 11 and 12, a power control unit 13, a power shut-off circuit 14, and a test dedicated circuit 15. The LSI 10 has a test mode for testing the LSI 10 using a tester device (not shown) in addition to the active mode and the standby mode.

  In the present embodiment, the first functional block 11 is connected to the power supply lines L1 and L2, and the power supply voltage VIN is always supplied from the power supply line L1 when the LSI 10 is in any of the active mode, standby mode, and test mode. Has been.

  The second functional block 12 is connected to the power supply line L1 via the power supply cutoff circuit 14 and the power supply voltage VIN from the power supply line L1 is supplied via the power supply cutoff circuit 14. The second functional block 12 is configured to perform power gating. That is, the second functional block 12 is supplied with the control voltage VIN2 based on the power supply voltage VIN via the power supply cutoff circuit 14 when the LSI 10 is in the active mode. On the other hand, in the second functional block 12, the supply of the control voltage VIN2 based on the power supply voltage VIN is cut off by the power cut-off circuit 14 when the LSI 10 is on standby.

  The power control unit 13 receives an H level power test signal Se for instructing the start of a power shut-off test from a tester device (not shown). The power controller 13 outputs the input data D and the clock CLK to the second functional block 12 based on the input H level power test signal Se.

  The power supply control unit 13 outputs input data D for each cycle in synchronization with the clock CLK. The input data D is generated in the power supply control unit 13 so that at least the data in the first cycle (hereinafter referred to as head input data) is H level data and is output to the second functional block. When the power supply control unit 13 outputs a predetermined number of clocks CLK (the number of flip-flop circuits FF of the scan chain 16 provided in the second function block 12 described later), the power supply control unit 13 does not output the clock CLK thereafter. ing.

  The power supply control unit 13 outputs an H level cutoff control signal PCTL for supplying the power supply voltage VIN to the power cutoff circuit 14 based on the H level power supply test signal Se. Then, when a predetermined number of clocks CLK (the number of flip-flop circuits FF to be described later) are output to the second functional block 12, the power supply control unit 13 loses the H level cutoff control signal PCTL and supplies power. An L level cutoff control signal PCTL for stopping the supply of the voltage VIN is output to the power cutoff circuit 14.

  In the power cutoff circuit 14, a plurality of first to nth N-channel MOS transistors T1 to Tn are connected in parallel. The sources of the N-channel MOS transistors T1 to Tn are connected to the power supply line L1, and the drains of the N-channel MOS transistors T1 to Tn are connected to the second functional block 12. Further, the cutoff control signal PCTL from the power supply control unit 13 is input to the gates of the N-channel MOS transistors T1 to Tn.

The power cutoff circuit 14 connects the first to nth N-channel MOS transistors T1 to Tn in parallel to reduce the on-resistance, thereby reducing the voltage drop of the power supply voltage VIN.
The power cutoff circuit 14 receives the cutoff control signal PCTL from the power supply control unit 13, turns on / off the first to nth N-channel MOS transistors T1 to Tn based on the inputted cutoff control signal PCTL, and supplies the power supply voltage VIN and the second function. Connect or disconnect with block 12.

  That is, when the H level cutoff control signal PCTL is input, the power cutoff circuit 14 turns on all the N-channel MOS transistors T1 to Tn at the same time, and connects the power line L1 and the second functional block 12. On the other hand, when the L-level cutoff control signal PCTL is input, the power cutoff circuit 14 turns off all the N-channel MOS transistors T1 to Tn at the same time and shuts off the power supply line L1 and the second functional block 12.

  That is, the power shutoff circuit 14 electrically connects the power supply line L1 and the second functional block 12 so that the power shutoff circuit 14 is connected to the power supply circuit from the connection point (first node N1) between the power shutoff circuit 14 and the second functional block 12. A control voltage VIN 2 that is lower than the voltage VIN by the voltage drop in the power supply cutoff circuit 14 is supplied to the second functional block 12.

  On the other hand, the power shutoff circuit 14 stops the supply of the control voltage VIN2 to the second functional block 12 by electrically shutting off the power supply line L1 and the second functional block 12. When the power supply line L1 and the second functional block 12 are electrically cut off, the control voltage VIN2 is a floating potential, and the control voltage VIN2 gradually decreases to the GND level due to a parasitic component of the wiring or circuit element. .

  The second functional block 12 is supplied with a control voltage VIN2 as a power supply voltage from the power supply cutoff circuit. The second functional block 12 includes a scan chain 16. The scan chain 16 has a plurality of flip-flop circuits FF connected in series. The clock CLK from the power supply control unit 13 is input to the flip-flop circuit FF. The input data D output from the power supply control unit 13 in synchronization with the clock CLK is first input to the first flip-flop circuit FF, and sequentially shifted to the subsequent flip-flop circuit FF in response to the clock CLK. Finally, the final flip-flop circuit FF outputs the scan-out signal So to the test dedicated circuit 15.

That is, as shown in FIG. 2, H level head input data D is input from the power supply controller 13 to the scan chain 16 in synchronization with the clock CLK.
Then, as shown in FIG. 2D, when the number of clocks CLK of the number of flip-flop circuits FF constituting the scan chain 16 is input (time tkA), the H-level head input from the last flip-flop circuit FF of the scan chain 16 The data D is output to the test dedicated circuit 15 as the H level scan-out signal So.

  Then, after the H-level scan-out signal So is output, that is, after a predetermined number of clocks CLK have been output, as shown in FIG. The H level cutoff control signal PCTL output from 13 to the power cutoff circuit 14 disappears and becomes the L level cutoff control signal PCTL. As a result, the power supply line L1 and the second functional block 12 are electrically disconnected, and the control voltage VIN2 of the first node N1 becomes a floating potential, but gradually decreases to the L level due to the wiring and parasitic components of the circuit elements. .

  As a result, the H-level scan-out signal So output from the final flip-flop circuit FF of the scan chain 16 becomes the L-level and is output to the test dedicated circuit 15 with the disappearance of the control voltage VIN2. ing.

  The test dedicated circuit 15 includes first and second AND circuits 21 and 22 and a comparison circuit 31. The first AND circuit 21 receives the power supply voltage VIN from the power supply line L1. The first AND circuit 21 receives the test mode control signal St from the tester device that is output together with the H-level power supply test signal Se that is output from the tester device to the power supply control unit 13.

  Note that the test-dedicated circuit 15 receives an H-level test mode control signal St from the tester device in the test mode. On the contrary, the test dedicated circuit 15 outputs an L level test mode control signal St from the tester device in the active mode and the standby mode.

  The first AND circuit 21 outputs the first logic signal Sr1 at the H level to the plus input terminal of the comparison circuit 31 when both the input power supply voltage VIN and the test mode control signal St are at the H level.

  On the other hand, the second AND circuit 22 receives the test mode control signal St from the tester device and the scan-out signal So from the scan chain 16 of the second functional block 12. The second AND circuit 22 outputs the second logic signal Sr2 at the H level to the plus input terminal of the comparison circuit 31 when both the input test mode control signal St and the scan-out signal So are at the H level.

  The comparison circuit 31 inputs the first logic signal Sr1 to the plus input terminal and the second logic signal Sr2 to the minus input terminal. The comparison circuit 31 compares the input first logic signal Sr1 and the second logic signal Sr2, and outputs a test result signal Sk to the tester device according to the result. In the comparison circuit 31, when the positive input terminal and the negative input terminal are offset, and the same voltage is input to the positive input terminal and the negative input terminal, the second logic signal Sr2 input to the negative input terminal is It is recognized that it is larger than the first logic signal Sr1 input to the plus input terminal.

  That is, when the first logic signal Sr1 is greater than the second logic signal Sr2, the comparison circuit 31 outputs the H-level test result signal Sk assuming that the power supply voltage VIN and the second functional block are cut off. Conversely, when the first logic signal Sr1 is smaller than the second logic signal Sr2, the comparison circuit 31 outputs the L-level test result signal Sk on the assumption that the power supply voltage VIN and the second functional block 12 are not interrupted. .

  Therefore, as shown in FIG. 4G, the test dedicated circuit 15 outputs the H level test result signal Sk after the delay by the scan chain 16 and the test dedicated circuit 15 from time tkA (time tkA2). When an L level test result signal Sk is output from tkB after being delayed by the power cutoff circuit 14, the scan chain 16, and the test dedicated circuit 15 (time tkB2), the tester apparatus determines that the power cutoff test is Pass, that is, Then, it is determined that the power gating (power cutoff circuit 14) of the LSI 10 operates normally.

  On the contrary, when the test dedicated circuit 15 outputs the L level test result signal Sk at the time tkA2 or when the test dedicated circuit 15 outputs the H level test result signal Sk at the time tkB2, the tester device performs the Fail test for the power shutoff test. That is, it is determined that the power gating (power cutoff circuit 14) of the LSI 10 did not operate normally.

As described above, according to the present embodiment, the following effects can be obtained.
(1) When the scan-out signal So of the scan chain 16 is at the H level, the power shutoff circuit 14 shuts off the power supply voltage VIN and the second functional block 12. Then, the test dedicated circuit 15 compares the power supply voltage VIN with the scan-out signal So, and the tester device determines whether the power supply cutoff circuit 14 can cut off the power supply line L1 and the second functional block 12. For this reason, the power cutoff test can be easily performed simply by inputting the input data D of H level to the scan chain 16 and the test-dedicated circuit 15 comparing the power supply voltage VIN with the scan-out signal So. Further, the test dedicated circuit 15 can be configured with a small-scale circuit.

  (2) The test dedicated circuit 15 includes first and second AND circuits 21 and 22 before the comparison circuit 31. The first AND circuit 21 receives the test mode control signal St and the power supply voltage VIN, and the second AND circuit 22 receives the test mode control signal St and the control voltage VIN2. For this reason, in the test mode, the first and second logic signals Sr1 and Sr2 at L level are always input to the plus input terminal and the minus input terminal in the test mode, so that the comparison circuit 31 does not operate. Therefore, the test dedicated circuit 15 can reduce power consumption in the operation mode.

(Second Embodiment)
A second embodiment embodying the present invention will be described below with reference to FIGS. In the first embodiment, the test dedicated circuit 15 inputs the power supply voltage VIN, the test mode control signal St, and the scan-out signal So. The test dedicated circuit 15 outputs the test result signal Sk based on the input power supply voltage VIN, the test mode control signal St, and the scan-out signal So.

  In the second embodiment, the test dedicated circuit 15a receives the power supply voltage VIN and the logic determination signal Sg based on the voltage of the first node N1 (control voltage VIN2). The test dedicated circuit 15a outputs a test result signal Sk based on the input power supply voltage VIN and the logic determination signal Sg.

FIG. 3 is an electric block circuit diagram of the LSI 10a of this embodiment.
The power control unit 13a receives an H level power test signal Se for instructing the start of a power shut-off test from a tester device (not shown). The power control unit 13a outputs an H level cutoff control signal PCTL for supplying the power supply voltage VIN to the power cutoff circuit 14a based on the H level power test signal Se. Then, as shown in FIG. 4, when a predetermined time has elapsed (time tk1), the power supply control unit 13a loses the H level cutoff control signal PCTL and stops the supply of the power supply voltage VIN. A level cutoff control signal PCTL is output to the power cutoff circuit 14a.

That is, unlike the power supply control unit 13 of the first embodiment, the power supply control unit 13a of the present embodiment generates the input data D and the clock CLK and does not output it to the second functional block 12.
The power cutoff circuit 14a includes a logic determination circuit 40 as a delay circuit.

  The logic determination circuit 40 includes first and second inverter circuits 41 and 42 and a capacitor C1. The first inverter circuit 41 receives the control voltage VIN2 that is the voltage of the first node N1. The first inverter circuit 41 outputs an H level signal based on the control voltage VIN2 of the voltage value at that time when the power cutoff circuit 14a supplies the control voltage VIN2 based on the power supply voltage VIN to the second functional block 12. The signal is output to the second inverter circuit 42 in the next stage. On the other hand, in the first inverter circuit 41, the supply of the control voltage VIN2 based on the power supply voltage VIN is cut off by the power supply cut-off circuit 14, the first node N1 enters a floating state, and the control voltage VIN2 is discharged soon. As shown in d), when the voltage drops to a predetermined voltage (threshold voltage Vth of the first inverter circuit 41) (time tk2), an L level output signal is output to the second inverter circuit 42 in the next stage.

The second inverter circuit 42 inverts the output signal Sgx from the first inverter circuit 41 and outputs the inverted signal to the test-dedicated circuit 15a as the logic determination signal Sg.
That is, when the power shutoff circuit 14a does not shut off the power supply line L1 and the second functional block 12, the logic determination circuit 40 including the first and second inverter circuits 41 and 42 is based on the control voltage VIN2. 2 The logic decision signal Sg of H level is output from the inverter circuit 42 to the test dedicated circuit 15a. Conversely, when the power shutoff circuit 14a shuts off the power supply line L1 and the second functional block 12, the logic determination circuit 40 becomes a floating potential as shown in FIG. Based on the control voltage VIN2 lowered to the threshold voltage Vth) of the inverter circuit 41, the L-level logic determination signal Sg is output from the second inverter circuit 42 to the test dedicated circuit 15a.

  A connection point (second node N2) between the second inverter circuit 42 and the test dedicated circuit 15a is grounded via the capacitor C1. The capacitor C1 is charged with the electric charge from the power supply voltage VIN via the second inverter circuit 42 when the logic determination signal Sg of H level is output from the second inverter circuit 42 to the test dedicated circuit 15a. Further, the capacitor C1 discharges the charge charged through the second inverter circuit 42 to the ground when the L level logic determination signal Sg is output from the second inverter circuit 42 to the test dedicated circuit 15a.

  That is, as shown in FIG. 4 (e), the second inverter circuit 42 inverts the H level output signal Sgx from the first inverter circuit 41, and uses the inverted signal as the L level logic determination signal Sg. Output to the circuit 15a. At this time, as shown in FIG. 4 (d), the control voltage VIN2 has not been lowered to the GND level. However, the power shutoff test is to be performed after the control voltage VIN2 reaches the GND level, that is, after the supply of the control voltage VIN2 based on the power supply voltage VIN to the second functional block 12 is completely shut off. . For this reason, when the power cutoff circuit 14a shuts off the power supply line L1 and the second functional block 12, the capacitor C1 is switched from the control voltage VIN2 to the GND level as shown in FIG. tk3) As shown in FIG. 4G, the falling of the logic determination signal Sg is delayed so that the test result signal Sk becomes L level (time tk4).

  Therefore, the capacitor C1 has a reference for the test-dedicated circuit 15a for the logic determination signal Sg for a time period from when the control voltage VIN2 drops to a predetermined potential (threshold voltage Vth of the first inverter circuit 41) until it reaches the GND level. The capacitance value is set so as to delay the time to fall to the voltage (Vk).

  The test dedicated circuit 15 a is configured by the comparison circuit 31. The comparison circuit 31 inputs the power supply voltage VIN to the plus input terminal and the logic determination signal Sg to be inputted to the minus input terminal. The comparison circuit 31 compares the input power supply voltage VIN with the logic determination signal Sg and outputs a test result signal Sk according to the result. That is, the comparison circuit 31 outputs the test result signal Sk at the H level when the power supply voltage VIN is smaller than the logic determination signal Sg. On the contrary, the comparison circuit 31 outputs the L-level test result signal Sk when the power supply voltage VIN is larger than the logic determination signal Sg.

  Therefore, when the test dedicated circuit 15 outputs the test result signal Sk at the H level at time tk1 and outputs the test result signal Sk at the L level at time tk4, the tester device determines that the power interruption test is Pass. That is, it is determined that the power gating (power cutoff circuit 14) of the LSI 10 operates normally.

  On the other hand, when the test dedicated circuit 15 outputs the L level test result signal Sk at time tk1 or when the test dedicated circuit 15 outputs the H level test result signal Sk at time tk4, the tester device performs the Fail test on the power shutoff test. That is, it is determined that the power gating (power cutoff circuit 14) of the LSI 10 did not operate normally.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The test dedicated circuit 15a compares the logic determination signal Sg with the power supply voltage VIN, and the tester device determines the power interruption test according to the comparison result. For this reason, the power cutoff test of this embodiment does not use the second functional block 12. The power shutdown test of the first embodiment requires time until the H level input data D is input and the H level scan-out signal So is output in the second functional block 12. Accordingly, the power shutdown test of the present embodiment can reduce the time required for the second functional block of the first embodiment, so that the time of the power shutdown test can be shortened compared to the first embodiment. it can.

  (2) The power cutoff circuit 14a is provided with a logic determination circuit 40 between the first node N1 and the second node N2. Therefore, by setting the capacitance value of the capacitor C1, the tester device can perform the power interruption test when the control voltage VIN2 has dropped to the L level.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. The third embodiment is different from the second embodiment in that the LSI 10b includes two power cut-off circuits and controls supply / stop of the power supply voltage VIN to the corresponding functional block.

  As shown in FIG. 5, the LSI 10b includes first and second power shutoff circuits 14a and 14b. The first power cutoff circuit 14a receives the first cutoff control signal PCTL1 from the power control unit 13a, and the first to nth N-channel MOS transistors T1 to T1 in the first power cutoff circuit 14a according to the first cutoff control signal PCTL1. Tn is turned on and off all at once, and the power supply line L1 and the second functional block 12 are connected or disconnected.

  When the first power cut-off circuit 14a receives the H-level first cut-off control signal PCTL1, the first to nth N-channel MOS transistors T1 to Tn in the first power cut-off circuit 14a are turned on all at once, and the power line L1 The second functional block 12 is connected. On the other hand, when the first power cutoff circuit 14a receives the L-level first cutoff control signal PCTL1, the first to nth N-channel MOS transistors T1 to Tn in the first power cutoff circuit 14a are turned off all at once. The line L1 and the second functional block 12 are shut off.

  That is, the first power supply cutoff circuit 14a connects the power supply line L1 and the second functional block 12, and a voltage lower than the power supply voltage VIN by the voltage drop of the first power supply cutoff circuit 14a (first control voltage VIN2a) has the second function. Supply to block 12. On the other hand, the first power supply cutoff circuit 14 a cuts off the power supply voltage VIN and the second functional block 12 and stops supplying the power supply voltage VIN to the second functional block 12.

The first power shutoff circuit 14a outputs the first logic determination signal Sg1 from the logic determination circuit 40 provided in the circuit 14a to the test dedicated circuit 15b.
The second power cutoff circuit 14b receives the second cutoff control signal PCTL2 from the power supply control unit 13, and responds to the second cutoff control signal PCTL2 to include the first to nth N-channel MOS transistors T1 to T1 in the second power cutoff circuit 14b. Tn is turned on and off all at once, and the power supply line L1 and the third functional block 53 are connected or disconnected.

  When the second power cut-off circuit 14b receives the H-level second cut-off control signal PCTL2, the first to n-th N-channel MOS transistors T1 to Tn in the second power cut-off circuit 14b are turned on all at once, and the power line L1 The third function block 53 is connected. On the contrary, when the L-level second cutoff control signal PCTL2 is input, the first to nth N-channel MOS transistors T1 to Tn in the second power cutoff circuit 15a are turned off all at once, and the power line L1 and the third function block 53 are turned off. Shut off.

  That is, the second power supply cutoff circuit 14b connects the power supply line L1 and the third functional block 53, and a voltage lower than the power supply voltage VIN by the voltage drop of the second power supply cutoff circuit 14b (second control voltage VIN2b) is the third function. Supply to block 53. On the other hand, the second power shutoff circuit 14b shuts off the power supply line L1 and the third functional block 53 and stops supplying the power supply voltage VIN to the third functional block.

Further, the second power shutoff circuit 14b outputs the second logic determination signal Sg2 from the logic determination circuit 40 provided in the circuit 14a to the test dedicated circuit 15b.
The test dedicated circuit 15 b includes a comparison circuit 31 and a test selection circuit 54. The test selection circuit 54 selects either the first logic determination signal Sg1 input from the first power supply cutoff circuit 14a or the second logic determination signal Sg2 input from the second power supply cutoff circuit 14b from the switching signal Sc from the tester device. Based on the above, the result is output to the comparison circuit 31. The switching signal Sc is a signal output from the tester device in order to select which of the second or third functional blocks 12 and 53 is to be subjected to the power interruption test.

  As shown in FIG. 6, the test selection circuit 54 includes first and second AND circuits 55a and 55b, an inverter circuit 56, and an OR circuit 57. The first AND circuit 55a receives the first logic determination signal Sg1 from the first power cut-off circuit 14a and the switching signal Sc from the tester device.

  Here, the switching signal Sc is a signal for selecting one of the first logic determination signal Sg1 input from the first power supply cutoff circuit 14a and the second logic determination signal Sg2 input from the second power supply cutoff circuit 14b. Say. That is, the switching signal Sc selects which of the second or third functional blocks 12 and 53 is to be subjected to the power interruption test.

The first AND circuit 55a outputs a first logic signal Sr1 having an H level when both the input first logic determination signal Sg1 and the switching signal Sc are at an H level.
The inverter circuit 56 receives the switching signal Sc from the tester device. The inverter circuit 56 logically inverts the switching signal Sc and outputs the inverted signal BSc to the second AND circuit 55b.

  The second AND circuit 55b receives the second logic determination signal Sg2 from the second power cut-off circuit 14b and the inverted signal BSc from the inverter circuit 56. The second AND circuit 55b outputs the second logic signal Sr2 at the H level when both the input second logic determination signal Sg2 and the inverted signal BSc are at the H level.

  The OR circuit 57 receives the first logic signal Sr1 from the first AND circuit 55a and the second logic signal Sr2 from the second AND circuit 55b. The OR circuit 57 outputs an L level selection signal Ss when both the input first and second logic signals Sr1, Sr2 are at L level.

  In other words, when the L selection signal Sc is input, the test selection circuit 54 outputs the first logic determination signal Sg1 input from the first power shutoff circuit 14a to the comparison circuit 31 as the selection signal Ss. On the contrary, when the test selection circuit 54 receives the switching signal Sc at the H level, the test selection circuit 54 outputs the second logic determination signal Sg2 input from the second power supply cutoff circuit 14b to the comparison circuit 31 as the selection signal Ss.

  Therefore, when the test selection circuit 54 selects the first logic determination signal Sg1 and outputs it as the selection signal Ss to the comparison circuit 31, the tester device performs a power cutoff test of the first power cutoff circuit 14a. On the contrary, when the test selection circuit 54 selects the second logic determination signal Sg2 and outputs it to the comparison circuit 31 as the selection signal Ss, the tester device performs a power cutoff test of the second power cutoff circuit 14b.

As described above, according to the present embodiment, the following effects can be obtained.
Since the test dedicated circuit 15b includes the test selection circuit 54, it is possible to perform a power shutdown test on the first and second power shutdown circuits 14a and 14b.

In addition, you may implement the said embodiment in the following aspects.
In the above embodiment, the first and second power cutoff circuits 14a and 14b are configured by N-channel MOS transistors, but may be configured by P-channel MOS transistors.

In the first embodiment, the cutoff control signal PCTL, the input data D, and the clock CLK are input from the power supply control unit 13, but may be input from a tester device.
In the first embodiment, the test-dedicated circuit 15 inputs the scan-out signal So, but outputs an H level signal from the flip-flop circuit that does not constitute the scan chain formed in the second functional block. The signal may be input.

  In the second embodiment, the comparison circuit 31 has an offset on the plus input terminal and the minus input terminal. However, the comparison circuit 31 divides the power supply voltage VIN inputted to the plus side input terminal into a predetermined voltage. The pressed power supply voltage VIN may be input to the plus side input terminal.

In the second embodiment, the test dedicated circuit 15a is used, but the test dedicated circuit 15 may be used.
In the third embodiment, the test selection circuit 54 selects from the first and second logic determination signals Sg1 and Sg2, but may select three or more logic determination signals. The various embodiments described above can be summarized as follows.
(Appendix 1)
It has an active mode and a standby mode as operation modes, and a test mode for performing a test,
A plurality of functional blocks having a scan chain configured by connecting flip-flop circuits in series,
A power cutoff circuit that electrically connects and disconnects the functional block and the power source between at least one functional block of the plurality of functional blocks and a power source to supply and cut off a power source voltage to the functional block; Intervene,
In the active mode, the power cutoff circuit connects the power source and the functional block to supply a power supply voltage to the functional block. In the standby mode, the power cutoff circuit shuts off the power source and the functional block. And a semiconductor device configured to cut off the supply of power supply voltage to the functional block,
In the test mode, the scan chain output signal and the power supply voltage of the functional block connected to the power supply cutoff circuit are input, the output signal is compared with the power supply voltage, and the comparison result is output. A semiconductor device comprising a circuit.
(Appendix 2)
In the semiconductor device according to attachment 1,
The test-dedicated circuit cuts off the input of the output signal of the scan chain and the power supply voltage in the active mode and the standby mode.
(Appendix 3)
In the semiconductor device according to attachment 1 or 2,
The test dedicated circuit is:
The semiconductor device, further comprising a test selection circuit that selects one of the output signals of the plurality of scan chains when the power supply cutoff circuit and the plurality of functional blocks are provided.
(Appendix 4)
It has an active mode and a standby mode as operation modes, and a test mode for performing a test,
With multiple functional blocks,
A power cutoff circuit that electrically connects and disconnects the functional block and the power source between at least one functional block of the plurality of functional blocks and a power source to supply and cut off a power source voltage to the functional block; Intervene,
In the active mode, the power shutoff circuit connects the power supply and the functional block to supply a power supply voltage to the functional block. In the standby mode, the power shutoff circuit shuts off the power supply and the functional block. A semiconductor device configured to cut off the supply of power supply voltage to the functional block,
In the test mode, a test-dedicated circuit that inputs a voltage at the connection point between the power supply cutoff circuit and the functional block and the voltage, compares the voltage at the connection point with the power supply voltage, and outputs the comparison result is provided. A semiconductor device characterized by the above.
(Appendix 5)
In the semiconductor device according to attachment 4,
A delay circuit for delaying the rise and fall of the voltage at the connection point of the power supply cutoff circuit and the functional block is provided between the connection point of the power supply cutoff circuit and the functional block and the dedicated test circuit. A semiconductor device.
(Appendix 6)
In the semiconductor device according to attachment 4 or 5,
The test-dedicated circuit cuts off a voltage at a connection point between the power cutoff circuit and the functional block and an input of the power supply voltage in the active mode and the standby mode.
(Appendix 7)
In the semiconductor device according to any one of appendices 4 to 6,
The test dedicated circuit is:
When the semiconductor device includes a plurality of the power cutoff circuits, the semiconductor device further includes a test selection circuit that selects one of voltages at connection points between the plurality of power cutoff circuits and the functional block. .
(Appendix 8)
It has an active mode and a standby mode as operation modes, and a test mode for performing a test,
A plurality of functional blocks having a scan chain configured by connecting flip-flop circuits in series,
A power cutoff circuit that electrically connects and disconnects the functional block and the power source between at least one functional block of the plurality of functional blocks and a power source to supply and cut off a power source voltage to the functional block; Intervene,
In the active mode, the power shutoff circuit connects the power supply and the functional block to supply a power supply voltage to the functional block. In the standby mode, the power shutoff circuit shuts off the power supply and the functional block. A test method for a semiconductor device in which supply of power supply voltage to the functional block is cut off,
A test-dedicated circuit that inputs the output signal of the scan chain and the power supply voltage of the functional block connected to the power supply cutoff circuit, compares the output signal with the power supply voltage, and outputs the comparison result. ,
The input data input to the first stage of the scan chain is output from the last stage, and after the input data is output from the last stage, the power supply circuit and the functional block are A test method for a semiconductor device, wherein the quality of a power shut-off circuit is determined based on a shut-off state.
(Appendix 9)
It has an active mode and a standby mode as operation modes, and a test mode for performing a test,
With multiple functional blocks,
A power cutoff circuit that electrically connects and disconnects the functional block and the power source between at least one functional block of the plurality of functional blocks and a power source to supply and cut off a power source voltage to the functional block; Intervene,
In the active mode, the power shutoff circuit connects the power supply and the functional block to supply a power supply voltage to the functional block. In the standby mode, the power shutoff circuit shuts off the power supply and the functional block. A test method for a semiconductor device configured to cut off the supply of power supply voltage to the functional block,
A test-dedicated circuit that inputs the power supply voltage as a voltage at a connection point between the power supply cutoff circuit and the functional block, compares the voltage at the connection point with the power supply voltage, and outputs the comparison result,
Determining whether the power shutoff circuit is good or bad based on a state in which the power supply voltage is supplied to the functional block and a state in which the power supply and the functional block are shut off by the power shutoff circuit. Semiconductor device testing method.

1 is an electrical block diagram of a semiconductor device according to a first embodiment. (A)-(g) is a wave form diagram for demonstrating the test of the power cutoff circuit of 1st Embodiment. It is an electrical block diagram of the semiconductor device of 2nd Embodiment. (A)-(g) is a wave form diagram for demonstrating the test of the power cutoff circuit of 2nd Embodiment. It is an electrical block diagram of the semiconductor device of 3rd Embodiment. It is an electric circuit diagram of a test selection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11, 12 Function block 14 Power supply cutoff circuit 15 Test exclusive circuit 16 Scan chain 31 Comparison circuit 40 Logic decision circuit 54 Test decision circuit VIN Power supply voltage FF Flip-flop circuit

Claims (6)

And that function blocks have a scan chain including a plurality of flip-flop circuits connected in series,
Provided between the front Symbol Function block and power wiring, and a power supply cut-off circuit for controlling the supply of power supply voltage to the functional block,
A test circuit that receives the output signal of the scan chain and the power supply voltage included in the functional block, compares the output signal of the scan chain and the power supply voltage, and outputs a comparison result ;
In the test mode, the power supply cutoff circuit cuts off the supply of the power supply voltage to the functional block when the output signal of the scan chain is in a high potential logic state . Multiple functional blocks;
A first power cutoff circuit provided between a first functional block of the plurality of functional blocks and a power supply wiring and controlling supply of a power supply voltage to the first functional block ;
A test for inputting a voltage at a connection point between the first power supply cutoff circuit and the first functional block and the power supply voltage, comparing the voltage at the connection point with the power supply voltage, and outputting a comparison result. Circuit,
A delay circuit that delays the rise and fall of the voltage at the connection point between the first power shutoff circuit and the first functional block ;
In the test mode, the first power shutoff circuit shuts off the supply of the power supply voltage to the first functional block . The semiconductor device according to claim 2 ,
The test circuit, in the different operating modes and test modes, characterized by blocking the input of the first voltage at the connection point between the power-off circuit and the first functional block, and the power supply voltage Semiconductor device. The semiconductor device according to claim 2 or 3 ,
A second functional block that is different from the first functional block among the plurality of functional blocks and the power supply wiring, and controls supply of the power supply voltage to the second functional block; 2 further includes a power shutoff circuit,
The test circuit includes:
Wherein a first voltage at the connection point between the power-off circuit and the first functional block, the test selection circuit for selecting one of the connection point between said second power supply cut-off circuit and the second functional block A semiconductor device comprising: Provided between the that function block having a scan chain including a plurality of flip-flop circuits connected in series, the pre-Symbol function block and the power supply wiring, the power supply for controlling the supply of power supply voltage to the functional block A cutoff circuit; and a test circuit that receives the output signal of the scan chain and the power supply voltage included in the functional block, compares the output signal of the scan chain with the power supply voltage, and outputs a comparison result. A method for testing a semiconductor device, comprising:
Supply of the power supply voltage to the functional block by the power shutoff circuit when input data input to the first stage of the scan chain is output from the last stage and the output signal of the scan chain is in a high potential logic state Shut off
A test method for a semiconductor device, comprising: determining whether a power supply cutoff circuit is good or not based on a comparison result of the test circuit in a state where supply of the power supply voltage to the functional block is cut off . A plurality of functional blocks, and a first power cutoff circuit provided between a first functional block of the plurality of functional blocks and a power supply wiring and controlling supply of a power supply voltage to the first functional block And a voltage at a connection point between the first power cut-off circuit and the first functional block, and the power supply voltage are input, and the comparison result is output by comparing the voltage at the connection point with the power supply voltage. A test method for a semiconductor device comprising: a test circuit for delaying; and a delay circuit for delaying a rise and a fall of a voltage at a connection point between the first power cutoff circuit and the first functional block ,
Comparison result of the test circuit when the power supply voltage is supplied to the functional block , and comparison of the test circuit when the supply of the power supply voltage to the functional block is cut off by the power supply cutoff circuit A test method of a semiconductor device, wherein the quality of a power shut-off circuit is determined based on a result .