JP5202405B2 - High-speed computing device and computing method for dipole interaction - Google Patents

Description

  The present invention relates to a high-speed calculation technique of dipole interaction. For example, the present invention relates to a technique for realizing high-speed analysis processing of magnetization distribution and analysis processing of magnetization curve in an assembly of permanent magnets, magnetic sensors, magnetic recording media and other magnetic materials.

  Permanent magnets, magnetic sensors, magnetic recording media, and the like mainly contain a material having a property of being magnetized (magnetic material). In general, the magnetic properties of magnetic materials are quantitatively evaluated by numerical calculations based on micromagnetics. This analysis method based on micromagnetics uses the Brown's equation to search for the equilibrium state of magnetic energy, and the Landau-Lifshitz-Gilbert equation. There are two methods of obtaining the equilibrium state of the magnetized population from the dynamic process. In either method, the magnetic substance to be analyzed is divided into a large number of cells, a minute magnetization vector is given to each cell, and the state (direction) and magnetic energy of the magnetization vector are calculated.

JP-A-10-124479 JP-A-8-282745

  As described above, in the analysis of the magnetization distribution and the magnetization curve, it is necessary to calculate the magnetic energy corresponding to the states of the magnetization vectors arranged on many cells. The calculation of magnetic energy requires four types of calculations: dipole interaction energy between magnetizations, exchange interaction energy acting on magnetization, anisotropic energy of magnetization, and interaction energy with an externally applied magnetic field. is there.

  Of these calculations, the calculation of the dipole interaction between the magnetizations needs to be performed on pairs between all the magnetization vectors, and requires the largest amount of calculation. For this reason, when the number of cells is large, a very long calculation time is required even if a high-performance sequential processing type computer represented by a vector supercomputer is used.

  In response to the problem of speeding up the analysis of the magnetization distribution and the magnetization curve for this large-scale system, a method using fast Fourier transform, a method using magnetic potential, parallel processing of the whole equation (see Patent Document 1), etc. Several proposals have been made.

  However, the method using the fast Fourier transform has a drawback that it can be applied only to periodic and sufficiently smooth magnetization. In addition, the method using the magnetic potential needs to solve the Poisson equation or the Laplace equation in order to obtain the magnetic potential, and has a drawback that it cannot be used universally for any shape or shape change.

  Also, in the method of speeding up the analysis by parallel processing of the entire equation (see Patent Document 2), it is shown that the demagnetizing field that requires the most computation time is calculated by a direct method in a memory distributed multiprocessor computer system. However, there is no mention of the key to speeding up. The disclosure of Patent Document 1 is only related to the analysis of the Brownian equation, and does not describe information for analyzing the dynamic process of magnetization.

  Therefore, the inventor proposes a technique capable of calculating the interaction between dipoles at high speed. Specifically, a technique is proposed in which each of a plurality of arithmetic devices constituting a high-speed arithmetic device (computer system) operates based on an operation unit described so as to be able to execute operations independently and in parallel. The inventor also proposes a mechanism for notifying other operation units of the address range used by each operation unit for data reading and writing as an inaccessible area.

  The present invention realizes a parallel processing operation based on the operation unit, not the number of arithmetic devices. For this reason, the number of magnetization vectors to be analyzed can be freely given without being restricted by the parallel number of the arithmetic devices constituting the high-speed arithmetic device. In the case of the present invention, it is possible to minimize access between each arithmetic device and an external storage device by notifying each other as an inaccessible area of the address range in which each operation unit reads and writes data. That is, the waiting time on the bus can be minimized. As a result, the processing capability of the entire high-speed arithmetic device can be increased.

It is a figure which illustrates the whole structure of the arithmetic system which concerns on an example. It is a figure which shows the example of a form of an arithmetic unit. It is a figure explaining the relationship between a LLG analysis flow and the processing operation performed on a high-speed arithmetic device. It is a figure explaining the example of calculation operation of a vector sum.

Hereinafter, based on the drawings, a description will be given of an example of an apparatus for performing high-speed computation of dipole interaction.
(1) Exemplary Embodiment (1-1) Overall Configuration of Arithmetic System FIG. 1 shows an exemplary overall configuration of an arithmetic system according to an exemplary embodiment. The arithmetic system is composed of a high-speed arithmetic device 100 and an external computer 160, and a magnetic energy calculation operation is executed by these cooperative operations. That is, by the cooperative operation of the high-speed arithmetic device 100 and the external computer 160, (1) calculation of dipole interaction energy between magnetizations, (2) calculation of exchange interaction energy acting on magnetization, (3) anisotropic magnetization Calculation of sex energy, (4) Calculation of interaction energy with externally applied magnetic field is executed.

  Of these four calculations, calculation of the dipole interaction energy between the magnetizations (particularly calculation of the dipole interaction force) is executed by the high-speed arithmetic device 100, and the other three calculations are executed by the external computer 160.

  The high-speed arithmetic device 100 includes a plurality of arithmetic devices 200, a storage device 130 that stores a dipole-dipole matrix and a magnetization vector (hereinafter referred to as “memory G”), and a storage device that stores a calculation result. 140 (hereinafter referred to as “memory S”) and a bus 120 that connects them to each other. That is, the high-speed arithmetic device 100 has a parallel processor structure.

  Incidentally, the memory G corresponds to the first storage device in the claims. The memory S corresponds to the second storage device in the claims. One end of the bus 120 is connected to the external computer 160 via the connector 150.

  On the other hand, the external computer 160 includes a bus 162, a central processing unit 164, and a memory 166.

(1-2) Internal Configuration of Arithmetic Device 200 FIG. In this specification, the arithmetic device 200 is also referred to as an AUP (Action Unit Processor). The arithmetic device 200 according to the embodiment includes an arithmetic unit 210, a cache memory 220, and a list memory 230. The computing unit 210 is a part that actually performs computation of numerical data. The cache memory 220 is a storage area for storing data and addresses. The list memory 230 is a storage area for storing address information (address range) for specifying a readable / writable memory area.

  In the case of this embodiment, the list memory 230 stores two lists. One is an access permission list (hereinafter referred to as “allow list”) 240 for designating accessible areas on the memory G. The other one is an inaccessible list (hereinafter referred to as “deny list”) 250 that specifies an inaccessible area on the memory S. The allow list corresponds to the first list in the claims, and the deny list corresponds to the second list in the claims.

(1-3) Structure of Operation Unit Next, the content of an operation unit AU (Action Unit) that defines the operation of the arithmetic device 200 will be described. The operation unit AU is described as a combination of an arbitrary number of times each of reading numerical data from a specified memory, a specified calculation, and a calculation result writing to the specified memory. The contents of the operation unit AU are described in a program stored in the external computer 160 or the memory G. That is, the contents of a plurality of operation units AU are described in the program.

  The arithmetic device 200 reads this operation unit AU and executes it independently. For this reason, in the entire high-speed arithmetic device 100, the operation units AU are executed in parallel. In the case of this embodiment, each operation unit AU is given a unique number (recognition number). The arithmetic device 200 identifies the operation unit AU using this recognition number.

  Data transfer between the operation units AU is performed by each operation unit AU via the memory S. When the operation unit AU writes or reads data on the memory S, the operation unit AU notifies the operation unit AU operating on the other arithmetic unit 200 of the above-described identification number and memory address information. The other operation unit AU operating on the arithmetic device 200 stores the notified combination of the identification number and the memory address information in the deny list 250 of the list memory 230. The other operation unit AU that has received the notification cannot access the addresses existing in the deny list 250. In addition, when the writing operation or the reading operation with respect to the memory S by the operation unit AU is completed, its own identification number is notified to the other operation unit AU. The operation unit AU that has received the notification operates to delete all pairs of memory addresses related to the notified identification number from the deny list 250.

(1-4) LLG Analysis Operation FIG. 3 illustrates an example of calculation operation executed in the arithmetic system (FIG. 1) based on the LLG analysis method.

(Initial operation)
First, the initial operation 1000 of the LLG analysis flow is executed. In this initial operation, the dipole-dipole matrix Gij is calculated in the external computer 160. The data of the calculated dipole-dipole matrix Gij is written from the external computer 160 to the memory G in the high-speed arithmetic device 200 through the connector 150 and the bus 120.

  Here, when the number of magnetization vectors is N, the memory capacity necessary for writing the dipole-dipole matrix Gij is given by N × N × 3 × 3 × W bytes. Here, W is the number of bytes necessary to record one floating point real number. Preferred examples include single precision real numbers (W = 4 bytes) and double precision real numbers (W = 8 bytes).

  In this initial operation, the address range on the memory accessed by each operation unit AU is also determined. That is, in the initial operation, an operation unit AU necessary for a series of operations is generated. Here, the number of motion units AU is generated by the number N of magnetization vectors or an integer multiple thereof. The operation described later is executed according to the description of the operation unit AU.

(Calculation of force acting on magnetization)
Next, the calculation 1100 of the force acting on the magnetization is executed by the cooperative operation of the external computer 160 and the high-speed arithmetic device 200. The calculation is performed by the external computer 160 except for the calculation of the dipole interaction force. Below, the content of the processing operation performed by calculation of the force of a dipole interaction is demonstrated.

(A) Transfer of magnetization vector First, the magnetization vector transfer 2100 is executed. In this operation, the updated set of magnetization vectors is written into the memory G from the external computer 160 through the connector 150 and the bus 120. If the number of magnetization vectors is N, the memory capacity required to store a set of magnetization vectors is N × 3 × W bytes. Here, W is the number of bytes necessary to record one floating point real number. Preferred examples include single precision real numbers (W = 4 bytes) and double precision real numbers (W = 8 bytes).
At this time, the operation in which the data of the magnetization vector M used for calculation by each operation unit AU is stored in the cache memory 220 of the corresponding arithmetic device 200 is also executed.

(B) Vector Matrix Product Operation Next, a vector matrix product operation 2200 is executed. This operation corresponds to the operation of the first step in the claims. Here, two magnetizations are extracted from N magnetization sets, and the numbers of these two magnetizations are assumed to be i and j. It is assumed that the dipole-dipole matrix between the two magnetizations i and j is given by Gij. In this case, each operation unit AU executes a matrix operation expressed by Gij × Mj. Further, the three-dimensional vector Vij as a calculation result is written into the memory S through the bus 120.

  Hereinafter, the detailed contents of this operation will be described. In the case of this embodiment, each operation unit AU is described so that the calculation operation of the vector matrix product is executed in parallel and independently in the arithmetic device 200. For example, each operation unit AU is preliminarily designated with address information of numerical data used in the arithmetic operation. For example, address information of a dipole-dipole matrix Gij (existing on the memory G) includes two integer values i and j and a memory size W_33 (9 floating point numbers) required for one 3 × 3 matrix. (Real size) is described as follows.

Here, i and j are integers starting from zero. In that case, the start address Gij_start and the end address Gij_end of the dipole-dipole matrix Gij are given by the following equations.
Gij_start = i * (N-1) * W_33 + j * W_33 = {i * (N-1) + j} * W_33
Gij_end = Gij_start + W_33
Accordingly, the operation unit AU used in this step includes (i) an identification number, (ii) an integer value (i, j) for specifying magnetization, and (iii) an address range (Gij_start) of the dipole-dipole matrix Gij. , Gij_end), (iv) one of the address and vector value of the magnetization vector Mj, (v) an address for storing the three-dimensional vector Vij is set.

  Based on these pieces of information, each arithmetic device 200 reads the dipole-dipole matrix data and the magnetization vector independently and in parallel, and stores them in the cache memory 220. In addition, each arithmetic device 200 executes a product operation of the magnetization vector (three-dimensional) and the dipole-dipole matrix (3 × 3 dimensions) by the arithmetic unit 210, and the arithmetic result is secured in the memory S. Store in the address area for the vector Vij.

  When the execution of all the operation units AU corresponding to this step 1 is completed, the product operation between the dipole-dipole matrix and the magnetization vector for all the two magnetization combinations in the N magnetization sets is completed. Become.

(C) Vector Sum Operation Next, a vector sum operation 2300 is executed. This operation corresponds to the operation of the second step in the claims. When the calculated three-dimensional vector Vij is added only for a certain subscript j, a dipole interaction force Fi (= ΣVij) acting on the magnetization i is obtained. However, i ≠ j. Further, when the inner product of the dipole interaction force Fi and the magnetization Mi is obtained and the sum of all i is obtained, the dipole energy is obtained. Therefore, it is important for improving the calculation speed to efficiently calculate the vector sum for the subscript j. Below, the suitable calculation example is shown.

(C-1) Basic Operation Here, let N be the number of magnetization vectors in the set of magnetization vectors, and let L be the maximum power of 2 that does not exceed N. In this basic operation, a case where N = L is considered. Now, the integer set {1, 2, ..., P} that maximizes the integer P that satisfies L = 2 ^P is prepared. The elements p of this set are extracted in order from 1 to P, and the following processing operation is executed each time.

First, only the operation unit AU given by the identification number 2 ^{p * n} +2 ^(p-1) (where n = 0, 1, 2,...) Is operated. At this time, the operated operation unit AU reads the three-dimensional vector Vij written in the memory S by itself and the three-dimensional vector Vij written by the operation unit AU having the recognition number obtained by subtracting the integer 2 ^p from its own recognition number. The sum operation between these data is executed. At this time, two three-dimensional vectors (corresponding to “vector matrix product” or “vector matrix product sum” in the claims) used in this sum operation are exclusive with other operation units AU. The selected operation is performed. The operation unit writes the result obtained by the sum operation in a specific storage area secured on the memory S. For example, it is written in the storage area corresponding to the larger recognition number of the two recognition numbers to be subjected to the addition operation. This storage area is used again as a read area when the element p is moved up by one.

By repeating this processing operation, the sum (= ΣVij) of L (= N) three-dimensional vectors Vij is calculated as the processing result of the operation unit AU with the recognition number 2 ^P-1 . Then, the dipole interaction force Fi, which is the sum, is written in the memory S.

  In addition, if the above operation | movement is performed about all the subscripts i, the dipole interaction force Fi which acts on all the magnetization can be calculated.

(C-2) Deformation Operation In the above basic operation, the case where N = L has been described. However, such a condition is not always satisfied. In such a case, the following operation is executed. When N and L are not equal, first, a maximum power multiplier L not exceeding N is obtained. Then, the range given by this integer L is set to a subset to which the basic operation of the item (c-1) is applied.

  Next, an operation in which L in (c-1) is replaced with LL is applied to a subset of the three-dimensional vectors given by the maximum two power multiplier LL not exceeding the integer Q (= N−L). . In this case, the partial sum obtained for the set of three-dimensional vectors belonging to the range up to integer L and the part obtained for the set of three-dimensional vectors belonging to the range beyond integer L to integer LL By performing the sum operation with the sum, the sum (= ΣVij) of the three-dimensional vectors can be calculated.

  Further, if N and L + LL are not equal, a subset is set in the same manner, and the processing in (c-1) is applied to the range. For example, a sum operation of the three-dimensional vectors corresponding to the integer range is performed by the operation unit AU to which the identification number belongs to the integer subset R = {N−L−LL + 1, N−L−LL + 2,..., N}. The The above processing image is shown in FIG. FIG. 4 shows a state in which the basic operation of the item (c-1) is executed for each of three ranges given as powers of 2, and the calculation results are further added.

(D) Transfer of Dipole Interaction Force Next, transfer of the calculated dipole interaction force 2400 is executed. In this operation, a dipole interaction force Fi, which is N set data of a three-dimensional vector, is transferred to the external computer 160.

(Determination of the next magnetization state)
By the work so far, all the dipole interaction forces Fi acting on the magnetization are obtained on the external computer 160. In the next determination of magnetization state 1200, these dipole interaction forces Fi are applied to the method defined by the LLG equation to determine the magnetization state when advanced by the time step size.

(End judgment)
Thereafter, a determination is made as to whether the calculation has been performed up to a predetermined number of times (that is, end determination 1300).

(End processing)
When the calculation reaches the predetermined number of times, the end process 1400 (2500) is performed and the process ends.

(1-5) Summary As described above, according to this embodiment, the parallel division is performed not by the number of processors but by the unit of work (operation unit AU) that operates on the processors. The number of magnetization vectors to be analyzed can be changed without being limited by the parallel number. Therefore, even a huge number of magnetization vectors can be analyzed very easily.

  In the case of this configuration example, the dipole-dipole interaction part with the heaviest calculation load can be executed and other calculations can be entrusted to an external computer, so the analysis equations and methods can be expanded flexibly. Is possible.

  In addition, according to this embodiment, in the analysis of the dynamic process (spin reversal) of magnetization of a magnetic material, the magnetization distribution and the magnetization curve, the high- It is possible to analyze with high accuracy. Therefore, spin reversal characteristics on nano-sized magnetic materials, magnetization reversal characteristics on magnetic materials with complex interface shapes, magnetic properties of three-dimensional multilayered magnetic materials, as well as characteristics analysis of two-dimensional magnetic films, etc. It is effective for.

(2) Other Embodiments (2-1) In the above embodiment, in the vector sum operation 2300, the operation unit AU given the recognition number 2 ^{p * n} +2 ^(p-1) Also, the three-dimensional vectors calculated by the motion unit AU given by the recognition number minus 2 ^p are added together, and the addition result is the motion unit AU having the recognition number given by 2 ^{p * n} +2 ^(p-1). The case where data is written to the memory area has been described. However, it may be written in the memory area of the operation unit AU having an identification number obtained by subtracting 2 ^p from 2 ^{p * n} +2 ^(p−1) .
Further, if the result of adding all three-dimensional vectors without overlapping is obtained, the method of giving two three-dimensional vector pairs to be subjected to the addition operation is arbitrary.

(2-2) In the case of the embodiment described above, the case has been described where the storage area on the memory S used by each operation unit AU is notified to another operation unit AU as an inaccessible area. However, the storage area on the memory G used by each operation unit AU may be notified as an inaccessible area. For example, when the vector matrix product operation 2200 is executed, each operation unit AU calculates a vector matrix product for a completely arbitrary magnetization. In this case, it is also conceivable that any one of the integer values (i, j) specifying the two magnetization vectors to be calculated competes with another operation unit AU. That is, a plurality of operation units may read the same magnetization vector Mj. However, if the running operation unit AU notifies these addresses as inaccessible addresses, each operation unit AU can stop reading from the address before starting to access the memory G.

(2-3) In the case of the embodiment described above, the case has been described in which the high-speed arithmetic device 100 shares only the calculation of the dipole interaction force. However, the arithmetic device 200 may execute other arithmetic processing.

(2-4) In the case of the above-described embodiment, the case where the calculation system calculates the magnetic energy as a whole has been described. However, the technique described in the embodiment can be applied to other general-purpose operations. It is assumed that the configuration of the high-speed arithmetic device 100 is the same as that of the first embodiment. At this time, at least a part of the operation unit generated without specifying the arithmetic device 200, the numerical data address range to be read from the storage device as a processing target, the address range to which the arithmetic result is written, and the read numerical data The processing contents for specifying the arithmetic operation for the above and the address range for giving the reading or writing destination of the numerical data are notified to the other arithmetic device as an inaccessible area, and the end of the reading or writing is notified to the other arithmetic device. And the process to be deleted from the second list may be described.

100 ... High-speed arithmetic unit 120 ... Bus 130 ... Storage device (memory G)
140 ... Storage device (memory S)
150 ... Connector 160 ... External computer 162 ... Bus 164 ... Central processing unit 166 ... Memory 200 ... Processing unit 210 ... Processing unit 220 ... Cache memory (register)
230 ... List memory 240 ... allow list 250 ... deny list 260 ... internal bus

Claims (7)

A first storage device for holding a set of dipole-dipole matrix data and magnetization vector data;
A second storage device for storing a calculation result;
An arithmetic unit, a cache memory for storing numerical data and its address information, a first list for designating an accessible area of the first storage device, and a first list for designating an inaccessible area of the second storage device A plurality of arithmetic units each having a list memory for storing two lists;
A bus that interconnects the first storage device, the second storage device, and the plurality of arithmetic devices;
In a first step of performing a matrix product operation of dipole-dipole matrix data and magnetization vector data:
Each of the plurality of arithmetic devices is independent and in parallel,
Read one of a plurality of motion units generated in advance without specifying an arithmetic unit, and determine the address range of magnetization vector data and the address range of dipole-dipole matrix data described in the motion unit. In addition to adding to the first list, next, magnetization vector data and dipole-dipole matrix data as operation targets are read from the first storage device and written to the cache memory based on the two address ranges. The product operation of the next written magnetization vector data and dipole-dipole matrix data is executed by the computing unit, and the matrix product data as the result of the computation is stored in the second storage device designated by the operation unit. Execute the processing operation that writes to the address range,
In a second step of performing a sum operation of the calculated matrix product data,
Each of the plurality of arithmetic devices is independent and in parallel,
As the first process, based on the set of matrix product data calculated in the first step, as many as the number of matrix product data pairs so as to eliminate duplication of elements between all matrix product data pairs. Until one of the generated operation units is read and reading / writing of numerical data by the operation unit is completed, the address range for reading / writing numerical data is notified to all other operation unit devices as the inaccessible address. Next, each address range of two matrix product data constituting the matrix product data pair designated by the operation unit is added to the first list, and the matrix product constituting the matrix product data pair designated next is added. Data is read from each address range of the second storage device, written to the cache memory, and then the sum operation of the two written matrix product data The running in the computing unit performs the operation to write the address range of the calculation result a is the matrix product sum data and the second storage device designated by the operation units,
Subsequently, as the second process, as many matrix product-sum data pairs as the number of matrix product-sum data pairs are generated based on the calculated set of matrix product-sum data so as to eliminate duplication of elements between all matrix product-sum data pairs. One of the operation units is read, and each address range of the two matrix product-sum data constituting the matrix product-sum data pair designated by the operation unit is added to the first list, and the operation unit Until the operation result writing operation by is completed, one address range giving the operation result write destination is notified to all other operation units to be written to the second list, and then specified. The matrix product-sum data constituting the matrix product-sum data pair is read from each address range of the second storage device, written to the cache memory, and then the two written rows Running sum operation of accumulator data in the operation unit performs the operation to write the address range of the operation of the matrix product sum data is the result specified by the operating unit the second storage device,
Thereafter, the second processing is repeatedly executed until the calculation result is integrated into one matrix product-sum data. Each operation unit that describes the operation content to be executed by each arithmetic device is given a unique identification number, and each arithmetic device performs an operation to be executed by the other arithmetic device based on the recognition number. The high-speed arithmetic device according to claim 1, wherein the unit is identified. In each operation unit executed in the first process or the second process in the second step,
Two matrix product data or matrix product-sum data taken out in the order of the recognition number of each matrix product data or matrix product-sum data from the matrix product data or the set of matrix product-sum data as the target of the sum operation is summed The high-speed arithmetic device according to claim 2, wherein the high-speed arithmetic device is designated as an object of In the second step,
Each operation unit uses the address range from which one of the two matrix product data or matrix product-sum data specified as the target of the sum operation is read as the address range to which the operation result is written. The high-speed arithmetic device according to claim 3. When the total number of matrix product data to be summed in the first process in the second step does not match the power of 2,
The processing range of the set of matrix product data is divided into a subset corresponding to the maximum number of powers of 2 that does not exceed the total number, and then the total number of matrix product data sets is set for the remaining set of matrix product data. Repeating the process of dividing the processing range into a subset of the maximum number of powers of 2 not exceeding until all matrix product data is assigned to any subset,
Applying the first process and the second process to each generated subset,
5. The high-speed computing device according to claim 4, wherein when one matrix product-sum data is obtained for each subset, the second processing is executed on the data. 5. A first storage device for holding a set of numerical data;
A second storage device for storing a calculation result;
An arithmetic unit, a cache memory that stores numerical data and address information thereof, a first list that specifies an accessible area of the storage device, and a second list that specifies an inaccessible area of the storage device are stored. A plurality of arithmetic units each having a list memory;
A bus that interconnects the first storage device, the second storage device, and the plurality of arithmetic devices;
At least some of the operation units that are generated without specifying the computing device are:
An address range of numerical data to be read from the first storage device as a processing target;
Address range to write the calculation result,
Processing contents to specify the operation for the read numerical data,
A process of notifying other arithmetic devices of the address range giving the reading or writing destination of numerical data as the inaccessible area;
A dipole interaction high-speed arithmetic device comprising: a process of notifying the other arithmetic device of the end of reading or writing and deleting it from the second list. A first storage device that holds a set of dipole-dipole matrix data and magnetization vector data, a second storage device that stores operation results, an arithmetic unit, and a cache memory that stores numerical data and address information thereof And a plurality of list memories each storing a first list that designates an accessible area of the first storage device and a second list that designates an inaccessible area of the second storage device A dipole interaction high-speed calculation method executed in a high-speed calculation device having a bus that interconnects the calculation device, the first storage device, the second storage device, and the plurality of calculation devices There,
In a first step of performing a matrix product operation of dipole-dipole matrix data and magnetization vector data:
Each of the plurality of arithmetic devices is independent and in parallel,
Read one of a plurality of motion units generated in advance without specifying an arithmetic unit, and determine the address range of magnetization vector data and the address range of dipole-dipole matrix data described in the motion unit. In addition to adding to the first list, next, magnetization vector data and dipole-dipole matrix data as operation targets are read from the first storage device and written to the cache memory based on the two address ranges. The product operation of the next written magnetization vector data and dipole-dipole matrix data is executed by the computing unit, and the matrix product data as the result of the computation is stored in the second storage device designated by the operation unit. Execute the processing operation that writes to the address range,
In a second step of performing a sum operation of the calculated matrix product data,
Each of the plurality of arithmetic devices is independent and in parallel,
As the first process, based on the set of matrix product data calculated in the first step, as many as the number of matrix product data pairs so as to eliminate duplication of elements between all matrix product data pairs. Read one of the generated operation units, and notify all other operation units as the inaccessible address of the address range for reading and writing numerical data until the reading and writing of numerical data by the operation unit is completed, Next, each address range of two matrix product data constituting the matrix product data pair designated by the operation unit is added to the first list, and the matrix product data constituting the matrix product data pair designated next is added. Is read from each address range of the second storage device and written to the cache memory, and then the sum operation of the two matrix product data written is performed. Serial executed by the arithmetic unit, executes the operation to write the address range of the calculation result a is the matrix product sum data and the second storage device designated by the operation units,
Subsequently, as the second process, as many matrix product-sum data pairs as the number of matrix product-sum data pairs are generated based on the calculated set of matrix product-sum data so as to eliminate duplication of elements between all matrix product-sum data pairs. One of the operation units is read, and each address range of the two matrix product-sum data constituting the matrix product-sum data pair designated by the operation unit is added to the first list, and the operation unit Until the operation result writing operation by is completed, one address range giving the operation result write destination is notified to all other operation units to be written to the second list, and then specified. The matrix product-sum data constituting the matrix product-sum data pair is read from each address range of the second storage device, written to the cache memory, and then the two written rows Running sum operation of accumulator data in the operation unit performs the operation to write the address range of the operation of the matrix product sum data is the result specified by the operating unit the second storage device,
Thereafter, the second process is repeatedly executed until the calculation result is integrated into one matrix product-sum data.

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