JP5203602B2 - 銅でないメッキ可能層の上への銅の直接電気メッキのための方法 - Google Patents
銅でないメッキ可能層の上への銅の直接電気メッキのための方法 Download PDFInfo
- Publication number
- JP5203602B2 JP5203602B2 JP2006353015A JP2006353015A JP5203602B2 JP 5203602 B2 JP5203602 B2 JP 5203602B2 JP 2006353015 A JP2006353015 A JP 2006353015A JP 2006353015 A JP2006353015 A JP 2006353015A JP 5203602 B2 JP5203602 B2 JP 5203602B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- copper
- barrier layer
- ruthenium
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
- H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10P14/432—Chemical deposition, e.g. chemical vapour deposition [CVD] using selective deposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
- H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/052—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/052—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein
- H10W20/0523—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein by irradiating with ultraviolet or particle radiation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/952—Utilizing antireflective layer
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Chemical Vapour Deposition (AREA)
- Electroplating Methods And Accessories (AREA)
Description
基板の上に誘電体層を形成する工程と、
誘電体層の上に第一の障壁層を形成する工程と、
第一の障壁層の上に第二の障壁層を形成する工程であって、第二の障壁層は、ルテニウム、白金、パラジウム、ロジウムおよびイリジウムからなる群から選ばれ、第二の障壁層の形成は、第二の障壁層の中の酸素のバルク濃度が20原子パーセントまたはそれ未満となるように操作される工程と、
第二の障壁層の上に導電層を直接形成する工程と、
を含むプロセスが開示される。
基板の上に誘電体層を形成する工程と、
誘電体層の上に第一の障壁層を形成する工程と、
第一の障壁層の上に第二の障壁層を形成する工程であって、第二の障壁層は、ルテニウム、白金、パラジウム、ロジウムおよびイリジウムからなる群から選ばれ、第二の障壁層の形成は、第二の障壁層の中の酸素のバルク濃度が20原子パーセントまたはそれ未満となるように操作される工程と、
第二の障壁層を処理して第二の障壁層の表面上の酸化物の量を減少させる工程と、
第二の障壁層の上に導電層を直接形成する工程と、
を含むプロセスが開示される。
半導体構造物に相互配線を形成するプロセスであって、
基板の上に誘電体層を形成する工程と、
誘電体層の上に第一の障壁層を形成する工程と、
化学的蒸着法(CVD)および原子層堆積法(ALD即ちAtomic Layer Deposition)のうちの一つによって第一の障壁層の上に第二の障壁層を形成する工程であって、第二の障壁層は、ルテニウム、白金、パラジウム、ロジウムおよびイリジウムからなる群から選ばれ、第二の障壁層の形成は、第二の障壁層の中の酸素のバルク濃度が、次の工程で形成される導電層の外観が明るく、光沢を有するレベルに低下するように操作される工程と、
第二の障壁層の上に導電層を直接形成する工程であって、第二の障壁層の中の酸素のバルク濃度の上記のように低下したレベルに起因して導電層は明るく光沢を有する工程と、
を含むプロセスが開示される。
Claims (7)
- 半導体構造物中に相互配線を形成するプロセスであって、
基板の上に誘電体層を形成する工程と、
前記誘電体層の上に第一の障壁層を形成する工程と、
前記第一の障壁層の上に第二の障壁層を形成する工程であって、前記第二の障壁層は、ルテニウム、白金、パラジウム、ロジウムおよびイリジウムからなる群から選ばれ、前記第二の障壁層中の酸素のバルク濃度が20原子パーセントまたはそれ未満である工程と、
Cl − 、Br − またはI − を含むハロゲン化物イオン溶液に前記第二の障壁層の表面を曝露して前記第二の障壁層の表面の上の酸化物の量を減少させる工程と、
前記第二の障壁層の上に導電層を直接形成する工程と、
を含むプロセス。 - 前記導電層は銅または銅合金である、請求項1に記載のプロセス。
- 前記第二の障壁層はルテニウムである、請求項1に記載のプロセス。
- 半導体構造物中に相互配線を形成するプロセスであって、
基板の上に誘電体層を形成する工程と、
前記誘電体層の上に第一の障壁層を形成する工程と、
化学的蒸着(CVD)法又は原子層堆積(ALD)法によって前記第一の障壁層の上に第二の障壁層を形成する工程であって、前記第二の障壁層は、ルテニウム、白金、パラジウム、ロジウムおよびイリジウムからなる群から選ばれ、前記第二の障壁層中の酸素のバルク濃度が、続いて形成される導電層の外観を明るく光沢性にする値である工程と、
Cl − 、Br − またはI − を含むハロゲン化物イオン溶液に前記第二の障壁層の表面を曝露して前記第二の障壁層の表面の上の酸化物の量を減少させる工程と、
前記第二の障壁層の上に導電層を直接形成する工程であって、前記導電層の外観は、前記第二の障壁層中の酸素のバルク濃度の値によって、明るく光沢性である工程と、
を含むプロセス。 - 前記第二の障壁層中の酸素の前記バルク濃度は、20原子パーセントまたはそれ未満である、請求項4に記載のプロセス。
- 前記導電層は銅または銅合金である、請求項4に記載のプロセス。
- 前記第二の障壁層は、ルテニウムである、請求項4に記載のプロセス。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/306,932 US7405153B2 (en) | 2006-01-17 | 2006-01-17 | Method for direct electroplating of copper onto a non-copper plateable layer |
| US11/306932 | 2006-01-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007194624A JP2007194624A (ja) | 2007-08-02 |
| JP5203602B2 true JP5203602B2 (ja) | 2013-06-05 |
Family
ID=38263769
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006353015A Expired - Fee Related JP5203602B2 (ja) | 2006-01-17 | 2006-12-27 | 銅でないメッキ可能層の上への銅の直接電気メッキのための方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7405153B2 (ja) |
| JP (1) | JP5203602B2 (ja) |
| CN (1) | CN101016638A (ja) |
| TW (1) | TW200741965A (ja) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7405153B2 (en) * | 2006-01-17 | 2008-07-29 | International Business Machines Corporation | Method for direct electroplating of copper onto a non-copper plateable layer |
| JP2009147137A (ja) * | 2007-12-14 | 2009-07-02 | Toshiba Corp | 半導体装置およびその製造方法 |
| KR100924865B1 (ko) * | 2007-12-27 | 2009-11-02 | 주식회사 동부하이텍 | 반도체 소자의 금속배선 형성방법 |
| KR101180238B1 (ko) * | 2008-01-23 | 2012-09-05 | 닛코킨조쿠 가부시키가이샤 | 배리어층 상에 루테늄 전기 도금층을 가진 ulsi 미세 배선 부재 |
| JP2009266999A (ja) * | 2008-04-24 | 2009-11-12 | Renesas Technology Corp | 半導体装置、およびその製造方法 |
| US8679970B2 (en) * | 2008-05-21 | 2014-03-25 | International Business Machines Corporation | Structure and process for conductive contact integration |
| US8105937B2 (en) * | 2008-08-13 | 2012-01-31 | International Business Machines Corporation | Conformal adhesion promoter liner for metal interconnects |
| JP2010189693A (ja) * | 2009-02-17 | 2010-09-02 | Tokyo Electron Ltd | Cu膜の成膜方法および記憶媒体 |
| DE102009015718B4 (de) * | 2009-03-31 | 2012-03-29 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Testsystem und Verfahren zum Verringern der Schäden in Saatschichten in Metallisierungssystemen von Halbleiterbauelementen |
| TWI459507B (zh) * | 2009-06-18 | 2014-11-01 | United Microelectronics Corp | 一種製作矽貫通電極的方法 |
| JP5653743B2 (ja) * | 2009-12-25 | 2015-01-14 | 株式会社荏原製作所 | 金属膜形成方法および装置 |
| JP2011216867A (ja) * | 2010-03-17 | 2011-10-27 | Tokyo Electron Ltd | 薄膜の形成方法 |
| US8399353B2 (en) | 2011-01-27 | 2013-03-19 | Tokyo Electron Limited | Methods of forming copper wiring and copper film, and film forming system |
| US8859422B2 (en) | 2011-01-27 | 2014-10-14 | Tokyo Electron Limited | Method of forming copper wiring and method and system for forming copper film |
| WO2012133400A1 (ja) * | 2011-03-30 | 2012-10-04 | 東京エレクトロン株式会社 | Cu配線の形成方法 |
| US20130307153A1 (en) | 2012-05-18 | 2013-11-21 | International Business Machines Corporation | Interconnect with titanium-oxide diffusion barrier |
| JP6324800B2 (ja) | 2014-05-07 | 2018-05-16 | 東京エレクトロン株式会社 | 成膜方法および成膜装置 |
| US9704804B1 (en) | 2015-12-18 | 2017-07-11 | Texas Instruments Incorporated | Oxidation resistant barrier metal process for semiconductor devices |
| US10049980B1 (en) | 2017-02-10 | 2018-08-14 | International Business Machines Corporation | Low resistance seed enhancement spacers for voidless interconnect structures |
| US20240387379A1 (en) * | 2023-05-16 | 2024-11-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for copper plating in semiconductor devices |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3951843A (en) * | 1973-01-09 | 1976-04-20 | Lfe Corporation | Fluorocarbon composition for use in plasma removal of photoresist material from semiconductor devices |
| JPH04243134A (ja) * | 1991-01-18 | 1992-08-31 | Sony Corp | 銅系金属配線の形成方法 |
| US6709562B1 (en) | 1995-12-29 | 2004-03-23 | International Business Machines Corporation | Method of making electroplated interconnection structures on integrated circuit chips |
| KR100269326B1 (ko) | 1998-06-08 | 2000-10-16 | 윤종용 | 전기 도금으로 형성된 전극을 갖춘 커패시터및 그 제조방법 |
| US6417062B1 (en) | 2000-05-01 | 2002-07-09 | General Electric Company | Method of forming ruthenium oxide films |
| US6921712B2 (en) * | 2000-05-15 | 2005-07-26 | Asm International Nv | Process for producing integrated circuits including reduction using gaseous organic compounds |
| US6696363B2 (en) | 2000-06-06 | 2004-02-24 | Ekc Technology, Inc. | Method of and apparatus for substrate pre-treatment |
| US7074640B2 (en) | 2000-06-06 | 2006-07-11 | Simon Fraser University | Method of making barrier layers |
| JP2002201162A (ja) | 2000-06-08 | 2002-07-16 | Jsr Corp | ルテニウム膜および酸化ルテニウム膜、ならびにその形成方法 |
| WO2002032839A1 (fr) | 2000-10-18 | 2002-04-25 | Jsr Corporation | Film de ruthenium et film d"oxyde de ruthenium, et leur procede de formation |
| US6455414B1 (en) * | 2000-11-28 | 2002-09-24 | Tokyo Electron Limited | Method for improving the adhesion of sputtered copper films to CVD transition metal based underlayers |
| US6787912B2 (en) | 2002-04-26 | 2004-09-07 | International Business Machines Corporation | Barrier material for copper structures |
| US6812143B2 (en) | 2002-04-26 | 2004-11-02 | International Business Machines Corporation | Process of forming copper structures |
| US20040007473A1 (en) * | 2002-07-11 | 2004-01-15 | Applied Materials, Inc. | Electrolyte/organic additive separation in electroplating processes |
| US6974531B2 (en) | 2002-10-15 | 2005-12-13 | International Business Machines Corporation | Method for electroplating on resistive substrates |
| US6974768B1 (en) * | 2003-01-15 | 2005-12-13 | Novellus Systems, Inc. | Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films |
| US7229911B2 (en) * | 2004-04-19 | 2007-06-12 | Applied Materials, Inc. | Adhesion improvement for low k dielectrics to conductive materials |
| JP2005347510A (ja) * | 2004-06-03 | 2005-12-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| US7405153B2 (en) * | 2006-01-17 | 2008-07-29 | International Business Machines Corporation | Method for direct electroplating of copper onto a non-copper plateable layer |
-
2006
- 2006-01-17 US US11/306,932 patent/US7405153B2/en not_active Expired - Fee Related
- 2006-12-27 JP JP2006353015A patent/JP5203602B2/ja not_active Expired - Fee Related
-
2007
- 2007-01-12 TW TW096101220A patent/TW200741965A/zh unknown
- 2007-01-16 CN CN200710004205.7A patent/CN101016638A/zh active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CN101016638A (zh) | 2007-08-15 |
| US20070166995A1 (en) | 2007-07-19 |
| TW200741965A (en) | 2007-11-01 |
| US7405153B2 (en) | 2008-07-29 |
| JP2007194624A (ja) | 2007-08-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5203602B2 (ja) | 銅でないメッキ可能層の上への銅の直接電気メッキのための方法 | |
| US7405143B2 (en) | Method for fabricating a seed layer | |
| US7135404B2 (en) | Method for applying metal features onto barrier layers using electrochemical deposition | |
| US6740221B2 (en) | Method of forming copper interconnects | |
| US8513124B1 (en) | Copper electroplating process for uniform across wafer deposition and void free filling on semi-noble metal coated wafers | |
| US20110259750A1 (en) | Method of direct plating of copper on a ruthenium alloy | |
| US20030116439A1 (en) | Method for forming encapsulated metal interconnect structures in semiconductor integrated circuit devices | |
| US7799684B1 (en) | Two step process for uniform across wafer deposition and void free filling on ruthenium coated wafers | |
| US20030214010A1 (en) | Semiconductor device and method of manufacturing the same | |
| US7694413B2 (en) | Method of making a bottomless via | |
| US20070125657A1 (en) | Method of direct plating of copper on a substrate structure | |
| US8703615B1 (en) | Copper electroplating process for uniform across wafer deposition and void free filling on ruthenium coated wafers | |
| JP2001023989A (ja) | 化学気相堆積により堆積した銅の密着性を高める方法 | |
| US7405157B1 (en) | Methods for the electrochemical deposition of copper onto a barrier layer of a work piece | |
| US7442267B1 (en) | Anneal of ruthenium seed layer to improve copper plating | |
| EP3034655A1 (en) | Trench pattern wet chemical copper metal filling using a hard mask structure | |
| US20050274621A1 (en) | Method of barrier layer surface treatment to enable direct copper plating on barrier metal | |
| US20050199507A1 (en) | Chemical structures and compositions of ECP additives to reduce pit defects | |
| US20250125151A1 (en) | Electrolyte and Deposition of a Copper Barrier Layer in a Damascene Process | |
| JP3715975B2 (ja) | 多層配線構造の製造方法 | |
| US20030146102A1 (en) | Method for forming copper interconnects | |
| US7504335B2 (en) | Grafted seed layer for electrochemical plating | |
| JP4937437B2 (ja) | めっき浴から堆積される金属層の特性改善方法 | |
| CN1965110A (zh) | 能够在阻挡金属上直接镀铜的阻挡层表面处理的方法 | |
| WO2008134536A1 (en) | Method for electrochemically depositing metal onto a microelectronic workpiece |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20091026 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20121010 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121016 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130110 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130129 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130214 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160222 Year of fee payment: 3 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |