JP5210327B2 - Light emitting chip provided with at least one semiconductor substrate - Google Patents

Abstract

A chip includes at least one semiconductor body having a radiation-emitting region, and at least one first contact region which is provided for making electrical contact with the semiconductor body and is spaced apart laterally from the radiation-emitting region. An electrically conductive first contact layer which is transmissive to the emitted radiation and which connects a surface of the semiconductor body, is situated on the radiation exit side of the chip to the first contact region. The surface is free of the radiation-absorbing contact structures.

Description

  The present invention relates to a chip provided for emitting a beam. In particular, the tip has a non-wired contact on the beam exit surface.

  This application claims the priority of German Patent Application No. 102007008524.0, the disclosure of which is hereby incorporated by reference.

  The aforementioned optoelectronic device, for example a light emitting diode (LED), usually has two contact surfaces facing each other, one contact surface being provided on a conductive support, for example a metallization layer of a chip casing. It is often implemented on the area where

  The electrical contact on the other contact surface is conventionally manufactured by a bonding wire. In order to form a conductive connection between the bonding wire and the chip surface to be contacted, a metal layer, so-called bonding pad, is provided in the region of the chip surface. However, this metal layer is not optically transparent, which has the disadvantage that some of the light generated in the chip is absorbed. However, reducing the area of the bonding pad is technically very restrictive and increases manufacturing costs.

In order to avoid the problem that a part of the surface of the optoelectronic element provided to couple the beam out is shielded, JP 09283801 A discloses an electrode arranged on the surface of the semiconductor chip, It is known to make a contact connection with a conductive and permeable layer of indium tin oxide (ITO) without the use of wires. Side edges of the semiconductor chip is electrically insulated from the transparent layer with a conductive by an insulating layer made of SiO _2.

  The problem underlying the present invention is to provide a chip which is arranged on the beam exit side of the chip and which further alleviates the problems associated with shielding the surface of the semiconductor substrate.

  This problem is solved by the chip according to claim 1. Advantageous embodiments and configurations of the invention are described in the dependent claims.

  The chip according to the invention has at least one semiconductor substrate with a region for emitting a beam, and the chip is provided for electrical contact connection of the semiconductor substrate and the region for emitting a beam. And at least one first contact region spaced laterally from the substrate, the chip further comprising a conductive first contact layer that is transparent to the emitted beam. The first contact layer connects the surface of the semiconductor substrate on the beam emission side of the chip to the first contact region. Here, the aforementioned surface does not have a contact structure that absorbs the beam.

  Advantageously, the first contact layer on the beam exit side does not have a contact structure that absorbs the beam.

  In the context of the present application, a contact structure is understood in particular as a metallic contact region, for example a contact region in the form of a contact web or bonding pads. Therefore, the first contact layer is not a contact structure. The absence of contact structures for absorbing the beam on the beam exit side of the chip advantageously enhances the beam that can be emitted by this chip. Further advantageously, the bonding wire for connecting the bonding pad arranged on the surface on the beam emitting side to the terminal region can be omitted because it causes a shielding on the surface on the beam emitting side. This is achieved by replacing both the bonding pad and the bonding wire with the first contact layer. Of course, in the present invention, electrical connection of chips by wire connection is not excluded. The first contact region can be electrically connected to the voltage source by, for example, a bonding wire.

  The region that emits the beam has a pn junction that produces the beam. In the simplest case, the pn junction can be formed of a p-conductivity type semiconductor layer and an n-conductivity type semiconductor layer that are in direct contact with each other. Advantageously, the original beam generating layer is formed between the p-conducting active layer and the n-conducting active layer, for example in the form of a doped or undoped quantum layer. The quantum layer can be formed as a single quantum well structure (SQW, Single Quantum Well), a multiple quantum well structure (MQW, Multiple Quantum Well), or a quantum line or quantum point structure.

  In an advantageous embodiment of the chip, the first contact region is spatially separated from the region emitting the beam. In particular, neither the region emitting the beam nor any other semiconductor layer extends to the first contact region. If it extends to the first contact region, the semiconductor layer is preferably transitioned to the first contact region in order to prevent the generation of the beam directly under the beam-absorbing first semiconductor layer. In, for example, it is divided by a divided junction.

  Since the first contact region is arranged in the main radiation path of the chip, the first characteristic is not particularly considered in terms of optical characteristics, and therefore mainly in terms of relatively good conductivity or current distribution. The contact region can be formed. Advantageously, in the chip according to the invention, the radiation of the beam can be improved simultaneously with the improvement of the electrical contact.

  In an advantageous embodiment, the majority of the surface is covered by the first contact layer. This means that the surface is completely or almost completely covered by the first contact layer. If the surface is almost completely covered, it is possible in particular to provide one insulating layer, which is, for example, arranged at the edge at the surface and, if necessary, at all edges. Has been placed.

According to a particularly advantageous embodiment, the first contact layer forms a layer that borders the chip and the outside in the main radial direction. Advantageously, the first contact layer contains TCO (Transparent Conductive Oxide). TCO can be sputtered or deposited on a semiconductor substrate, for example. TCO is a transparent conductive material, usually a metal oxide such as zinc oxide, tin oxide, cadmium oxide, titanium oxide, indium oxide or indium tin oxide (ITO). In addition to two-component metal oxygen compounds such as ZnO, SnO ₂ or In ₂ O ₃ , Zn ₂ SnO ₄ , CdSnO ₃ , ZnSnO ₃ , MgIn ₂ O ₄ , GaInO ₃ , Zn ₂ In ₂ O ₅ or In ₄ Sn ₃ Three-component metal oxygen compounds such as O ₁₂ and mixtures of various permeable conductive oxides also belong to the TCO group of materials. Furthermore, the TCO does not necessarily correspond to the stoichiometric composition and can be doped p-type or n-type. This is especially the case when TCO is used for the first contact layer of the first conductivity type and for the second contact layer of the second conductivity type. For example, the TCO of the first contact layer can be doped p-type, while the TCO of the second contact layer can be doped n-type.

  According to an advantageous embodiment, the first contact region is a bonding pad or a contact finger. Particularly preferably, the first contact region contains a metal, for example Au. Advantageously, the first contact region has a relatively high reflectivity, in particular as high as 90%. Compared to a conventional chip in which light rays originating from the vicinity of the bonding pad are absorbed with a probability of about 50%, the beam loss originating from the first contact region is relatively small. Overall, a relatively high reflectivity can be achieved by the spacing between the first contact region and the semiconductor substrate, the proper choice of material and the shape of the first contact region, for example a prismatic shape.

  According to a particularly advantageous embodiment, the first contact region and the semiconductor substrate are arranged on a common support. By using a support, the stability of the chip is advantageously increased, which facilitates the processing of the chip, for example.

  In an advantageous variant, the chip has a second contact layer, which connects the semiconductor substrate to a second contact region for electrical contact connection of the semiconductor substrate. Similarly, the second contact layer realizes contact connection of the semiconductor substrate without using wires. The semiconductor substrate can be mechanically and electrically connected to the second contact region by a conductive adhesive.

  Advantageously, the second contact region is provided on the support. Particularly advantageously, the second contact region is formed on the support before the at least one semiconductor substrate is mounted on the support. Preferably, the second contact region is made of metal. In particular, the second contact region can contain Au, Al, Ag, AuZn. This type of material is particularly suitable for forming the second contact region as a reflective layer.

  According to an advantageous embodiment, the second contact area is a reflective layer suitable for emitting the emitted beam towards the main radiation direction. Therefore, the beam emitted from the chip can be enhanced.

  According to another advantageous embodiment, the first contact region is arranged behind the second contact region as viewed vertically from the support.

  In this specification, the main radiation direction and the vertical direction represent directions extending parallel to the growth direction, and the semiconductor layer of the semiconductor substrate is grown in that direction.

  Advantageously, the second contact layer is arranged between the semiconductor substrate and the second contact region and forms a mirror with the second contact region. In particular, the second contact layer is transparent to the emitted beam. The beam passing through the second contact layer can be reflected at the reflective layer. For example, the second contact layer can contain TCO. If the same material is used for the first contact layer and the second contact layer, the semiconductor substrate can be completely embedded in this material, in particular in the TCO.

  In order to prevent a short circuit, an insulating layer can be disposed between the first contact region and the second contact region. In addition, the insulating layer is advantageously arranged in such a way that a short circuit between the p-type and n-type regions of the semiconductor substrate is prevented. In this case, a part of the insulating layer can be provided on the side surface of the semiconductor substrate. Suitable materials for the insulating layer are, for example, silicon nitride or silicon oxide.

  In a first variation, the chip has at least one first semiconductor substrate and at least one second semiconductor substrate, the semiconductor substrates being spaced apart from one another in the lateral direction, Is provided with a first contact region. This arrangement is particularly advantageous for chips having edges longer than about 400 μm, especially when the chips are relatively large. This is because sufficient current distribution is realized by the first contact region arranged in the form of a contact grid.

  In the second variation, the chip has a semiconductor substrate having a through-hole at the center, and the first contact region is disposed in the through-hole. This arrangement is suitable for relatively small chips, preferably chips with edge lengths up to about 400 μm.

In an advantageous embodiment, the chip is a thin film light emitting diode chip. The thin film light emitting diode chip has in particular at least one of the following characteristics:
A reflecting layer is deposited or formed on the main surface of the support layer side of the epitaxy layer sequence forming the beam, and this reflective layer converts at least part of the electromagnetic beam formed in the epitaxy layer sequence Reflect back to
The epitaxy layer sequence has a thickness in the range of 20 μm or less, in particular in the range of 1 μm to 2 μm;
The epitaxy layer sequence comprises at least one semiconductor layer with at least one surface having a mixed structure, which in the ideal case results in a substantially ergodic light distribution in the epitaxy layer sequence. In other words, this light distribution has an ergodic probability dispersion characteristic as much as possible.

  The principle of the thin-film light-emitting diode chip is described, for example, in Appl. Phys. Lett. 63 (16), 18. Oktober 1993, 2174-2176 by I. Schnitzer et al., The disclosure of which is incorporated herein by reference. Let it be a literature.

  Thin film light emitting diode chips are Lambertian surface radiators in a good approximation and are therefore particularly well suited for use in projectors.

The semiconductor substrate can have a layer based on a phosphide compound semiconductor. In the context of the present invention, “based on a phosphide compound semiconductor” means that a component or part of a component having such characteristics is preferably Al _n Ga _m In _1-n-m P (provided that 0 ≦ n ≦ 1, 0 ≦ m ≦ 1, and n + m ≦ 1). The material does not necessarily have a mathematically exact composition according to the above formula. Rather, the material may contain one or more dopants and additional components that do not substantially change its physical properties. However, for the sake of clarity, the above formula shows the main structure of the crystal lattice (Al, Ga, In, P), even though a small amount of other material may be partially substituted. Contains only elements.

Alternatively, the semiconductor substrate can have a layer based on a nitride compound semiconductor. In the context of the present invention, “based on nitride compound semiconductor” means that the epitaxy layer sequence or at least one of the epitaxy layer sequence is a nitride III / V compound semiconductor material, preferably Al _n It is meant to contain Ga _m In _1- nmN (where 0 ≦ n ≦ 1, 0 ≦ m ≦ 1, and n + m ≦ 1). The material does not necessarily have a mathematically exact composition according to the above formula. Rather, this material may contain one or more dopants that do not substantially change the characteristic physical properties of the Al _n Ga _m In _1-nm N material, as well as additional components. However, for the sake of clarity, the above formula shows the main structure of the crystal lattice (Al, Ga, In, N), even though a small amount of other material may be partially substituted. Contains only elements.

  The epitaxy layer sequence of the thin-film light-emitting diode chip has a thickness of less than 1 μm, especially when using materials based on nitride compound semiconductors.

  Advantageously, the chip according to the invention does not require a current spreading layer in the semiconductor substrate. This is because sufficient current spreading is realized by the first contact layer. Therefore, an epitaxial layer sequence having a maximum thickness of 2 μm can be formed.

  A further improvement in the beam intensity of the chip is achieved by the fact that the surface arranged on the beam exit side of the semiconductor substrate has an output coupling element. For example, the surface can be roughened and can have microprisms or photonic crystals.

  In the following, the present invention will be described in detail on the basis of the five embodiments shown in FIGS.

1 shows a schematic cross-sectional view of a first embodiment of a chip according to the invention. Fig. 3 shows a schematic cross-sectional view of a second embodiment of a chip according to the invention. Figure 3 shows a schematic cross-sectional view of a third embodiment of a chip according to the invention. Figure 6 shows a schematic cross-sectional view of a fourth embodiment of a chip according to the invention. Figure 6 shows a schematic cross-sectional view of a fifth embodiment of a chip according to the present invention.

  Identical and similarly functioning components are given the same reference numbers in the drawings.

  The schematic diagram in FIG. 1 shows a cross section of the chip 100, and this cross section extends parallel to the side surface of the chip 100. The chip 100 has a plurality of separate semiconductor substrates 4, and these semiconductor substrates 4 are regularly arranged on a support 6. Advantageously, the semiconductor substrate 4 forms a matrix pattern, which here consists of three rows and three columns. Dividing into a plurality of semiconductor substrates is appropriate, especially when the chip is relatively large, preferably when the edge length is longer than about 400 μm. This is because, in this configuration, a plurality of first contact regions 5 are used, thereby advantageously realizing a uniform current distribution in the chip 100.

  Each semiconductor substrate 4 is arranged between two first contact regions 5. In particular, the first contact region 5 is a contact finger, which extends in a straight line along the aforementioned columns and rows, and the semiconductor body 4 is arranged between these rows. . That is, the first contact region 5 forms a contact grid, and an advantageous current distribution in the chip 100 is obtained by this contact grid. The first contact region 5 is preferably composed of a metal, where a metal having an advantageous conductivity and an advantageous reflectivity, for example Au, is suitable. The first contact region 5 is suitable not only for feeding but also for reflecting the emitted beam. In particular, the emitted beam is deflected in the main radiation direction, which is indicated by the arrows in FIG. Such a deflection can be achieved by the obliquely extending side surfaces of the first contact region 5. As shown in FIG. 1, the cross-sectional shape of the first contact region 5 may be a trapezoid.

  The semiconductor substrate 4 and the first contact region 5 are embedded in the first contact layer 1. The first contact layer 1 is conductive and transparent to the beam emitted from the active region of the semiconductor substrate 4. A suitable material for the first contact layer 1 is, for example, TCO. Since the first contact layer 1 completely covers the surface 9 of the semiconductor substrate 4 on the beam exit side 10 of the chip 100 and the beam absorbing contact structure is provided on the surface 9, the semiconductor substrate 4 Are electrically connected without being shielded. Although the side surface of the semiconductor substrate 4 is covered with the first contact layer 1, there is no possibility of short circuit because the quality of the side contact is not sufficient to function with respect to the operation of the semiconductor substrate 4.

  The first contact region 5 is disposed on the insulating layer 8, and the insulating layer 8 electrically insulates the first contact region 5 from the second contact region 3. Further, the first contact layer 1 is electrically insulated from the second contact layer 2 by the insulating layer 8. The insulating layer 8 contains, for example, silicon nitride or silicon oxide, and in this embodiment is structured such that there is substantially no insulating layer 8 in the region between the semiconductor substrate 4 and the second contact region 3. Has been. The second contact layer 2 is disposed in this region, and the semiconductor substrate 4 is electrically and mechanically connected to the second contact region 3 by the second contact layer 2. The second contact layer 2 is preferably transparent to the beam produced by the semiconductor substrate 4 and particularly preferably contains TCO. Due to this characteristic, the second contact layer 2 forms, in particular, one mirror with the second contact region 3, so that the emitted beam is reflected with high probability in the main radiation direction.

  The second contact region 3 completely covers the surface of the support 6 on the semiconductor substrate 4 side. Advantageously, the second contact region 3 contains a metal or metal compound, for example Au, Al, Ag or AuZn.

  In the embodiment shown, the chip 100 can be electrically connected by a back contact 7. The support 6 contains a conductive material such as metal or semiconductor.

  The semiconductor substrate 4 is a thin film semiconductor substrate, and the thin film semiconductor substrate can peel the growth substrate completely or slightly. Accordingly, the semiconductor substrate 4 has a beam emitting region and an n-conducting type coating layer and a p-conducting type coating layer, which are part of the epitaxial layer sequence 12 or form the epitaxial layer sequence 12. The thickness of the epitaxial layer sequence 12 is at most 2 μm. Since no current diffusion layer is provided in the semiconductor substrate 4 based on the first contact layer 1, the thickness can be kept so thin.

  In the chip 100 shown in FIG. 2, the semiconductor substrate 4 is embedded in the TCO. The first contact layer 1 and the second contact layer 2 that surround the semiconductor substrate 4 are electrically insulated from each other by an insulating layer 8.

  In this embodiment, the side surface of the semiconductor substrate 4 is covered with the insulating layer 8 instead of the contact layer 1. Advantageously, therefore, the lateral contact connection is interrupted.

  The semiconductor substrate 4 is disposed on a non-conductive support 6. For example, the support 6 can contain a ceramic material having a relatively high thermal conductivity in order to cool the chip 100. The electrical terminals on the support side are not realized by back contact, but preferably by electrically insulated contact fingers, which are arranged in the same plane as the second contact region 3; The second contact region 3 is electrically connected.

  One bonding wire can be bonded to each of the contact finger connected to the second contact region 3 and the first contact region 5, and these bonding wires are connected to different poles of the energy supply unit. .

  The second contact region 3 is a layer provided with a uniform thickness on the surface of the support 6 in the embodiment of FIGS. 1 and 2, but the second contact region 3 is a second layer of the chip 100 shown in FIG. The contact region 3 has a concave portion and a convex portion. The side surface of the convex part which also forms the side surface of the concave part extends obliquely. In particular, the projection is designed as a microprism, which advantageously improves the output coupling of the beam. The semiconductor substrate 4 is fitted in the recess, and direct contact between the semiconductor substrate 4 and the second contact region 3 is blocked by the insulating layer 8. The insulating layer 8 covers the convex part, but does not cover the bottom part of the concave part. As a result, the hollow portion formed between the semiconductor substrate 4 and the second contact region 3 is filled with the second contact layer 2.

  The first contact region 5 is arranged at the rear stage of the convex portion when viewed in the vertical direction. The first contact region 5 is embedded in the first contact layer 1. The first contact layer 1 is a layer that forms an external boundary with the chip 100.

  In the embodiment shown in FIG. 4, neither the second contact region 3 nor the second contact layer 2 is an unstructured layer. Therefore, unlike the embodiment shown in FIGS. 1 to 3, the mirror formed by the second contact region 3 and the second contact layer 2 is not similarly structured. In this embodiment, the manufacturing cost is advantageously reduced because the structuring step is omitted.

  The semiconductor substrate 4 is disposed on the second contact layer 2 having a uniform thickness. The insulating layer 8 covers the second contact layer 2 and the semiconductor substrate 4, but is blocked only at the surface 9 of the semiconductor substrate 4, so that the surface 9 is almost completely covered by the first contact layer 1. A first contact region 5 is attached to the first contact layer 1 at the grooves present between the semiconductor substrates 4 and also at the edges thereof. In this embodiment, although the first contact layer 1 does not form a cover layer, the chip 100 does not have a component projecting on the beam emission side 10. This is achieved by filling the first contact region 5 with a trench.

  FIG. 5 shows a variation of the chip 100, which is different in size from the chip of the embodiment shown in FIGS. This design is suitable for smaller chips, especially chips with an edge length of 400 μm or less. The chip 100 has a one-piece semiconductor substrate 4 with a through-hole 11. Since the penetrating part 11 is advantageously arranged in the center, isotropic energization of the semiconductor substrate 4 is realized by using the first contact region 5 arranged in the penetrating part 11. Below the first contact region 5, as in the previous embodiment, no semiconductor layer suitable for beam radiation is provided, so the first contact region 5 is disposed in the main radiation path of the chip 100. And therefore no shielding occurs. Furthermore, there is no need to worry that the first contact region 5 substantially reduces the beam. This is because, by using the contact region 5, the emitted light beam is deflected in the main radiation direction or returned to the semiconductor substrate 4, from which the light beam is output-coupled again.

  The penetrating part 11 is covered with an insulating layer 8, and the insulating layer 8 extends to the surface 9 of the semiconductor substrate 4. However, most of the surface 9 is covered by the first contact layer. Furthermore, the first contact layer 1 covers the insulating layer 8 and surrounds the lower part of the first contact region 5.

  The present invention is not limited to the description based on the examples. Rather, the invention includes any novel features and combinations of those features, particularly including each of the combinations of features recited in the claims, as such a combination itself. This applies even if not explicitly stated in the claims or the examples.

Claims (23)

In the chip (100),
Having at least one semiconductor substrate (4) with a region emitting the beam,
At least one first contact region (5) provided for electrical contact connection of the semiconductor substrate (4) and spaced laterally from the region emitting the beam. Have
A conductive first contact layer (1) that is transparent to the emitted beam, the first contact layer (1) on the beam exit side (10) of the chip (100); A surface (9) of the semiconductor substrate (4) is connected to the first contact region (5), and the surface (9) does not have a contact structure for absorbing the beam;
A second contact layer (2), the second contact layer (2) connecting the semiconductor substrate (4) to a second contact region for electrical contact connection of the semiconductor substrate (4); Connect to (3)
The second contact layer (2) has free a TCO,
Chip (100) has a semiconductor body having penetrating portions in the center (11) (4), that you said the through portion (11) in the first contact region (5) is arranged Feature chip (100).   The chip (100) according to claim 1, wherein the first contact layer (1) on the beam exit side (10) does not have a contact structure for absorbing the beam.   The chip (100) according to claim 1 or 2, wherein the first contact region (5) is spatially separated from the region emitting the beam.   The chip (100) according to any one of claims 1 to 3, wherein a majority of the surface (9) is covered by the first contact layer (1).   The tip (100) according to any one of claims 1 to 4, wherein the first contact layer (1) forms a layer that forms a boundary between the tip (100) and the outside in the main radial direction.   The chip (100) according to any one of claims 1 to 5, wherein the first contact layer (1) contains TCO.   The chip (100) according to any one of the preceding claims, wherein the first contact region (5) is a bonding pad or a contact finger.   The chip (100) according to any one of claims 1 to 7, wherein the first contact region (5) is made of metal.   The chip (100) according to any one of the preceding claims, wherein the first contact region (5) and the semiconductor substrate (4) are arranged on a common support (6).   The chip (100) according to claim 9, wherein the second contact region (3) is provided on the support (6).   The chip (100) according to claim 10, wherein the first contact region (5) is arranged behind the second contact region (3) when viewed in a vertical direction from the support (6).   The chip (100) according to any one of the preceding claims, wherein the second contact region (3) is made of metal.   The chip (100) according to claim 12, wherein the second contact region (3) is a reflective layer.   The second contact layer (2) is disposed between the semiconductor substrate (4) and the second contact region (3), and forms a mirror together with the second contact region (3); The chip (100) of claim 13.   The chip (100) according to any one of the preceding claims, wherein the second contact layer (2) is transparent to the emitted beam.   16. Chip (1) according to any one of the preceding claims, wherein an insulating layer (8) is arranged between the first contact region (5) and the second contact region (3). 100). Chip (100) is a thin-film light-emitting diode chips, according to any one of claims 1 to 16 chips (100). The chip (100) according to claim 17 , wherein the epitaxy layer sequence (12) of the thin-film light emitting diode chip has a thickness of at most 2 m . It said first contact region (5) has a side surface extending obliquely in any one of claims 1 to 18 chips (100). The chip (100) according to any one of the preceding claims, wherein the chip (100) has an edge with a length of 400 m or less. 21. Chip (100) according to any one of the preceding claims, wherein the chip (100) has a semiconductor substrate (4) which is constructed in one piece. The chip (100) according to any one of claims 1 to 21, wherein the penetrating part (11) is arranged in the center of the semiconductor substrate (4). 23. The through-hole (11) is covered by the insulating layer (8), and the insulating layer (8) extends to the surface (9) of the semiconductor substrate (4). The chip (100) according to any one of the preceding claims.

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