JP5219908B2 - タッチパネル装置 - Google Patents
タッチパネル装置 Download PDFInfo
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- JP5219908B2 JP5219908B2 JP2009098235A JP2009098235A JP5219908B2 JP 5219908 B2 JP5219908 B2 JP 5219908B2 JP 2009098235 A JP2009098235 A JP 2009098235A JP 2009098235 A JP2009098235 A JP 2009098235A JP 5219908 B2 JP5219908 B2 JP 5219908B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
- H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
- H10W70/635—Through-vias
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/823—Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
- H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W99/00—Subject matter not provided for in other groups of this subclass
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
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- Switches That Are Operated By Magnetic Or Electric Fields (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
ただし、式(1)で求めた値が負の値となった場合は、かわりに0を差分値43として格納する。差分値43は、各電極においてタッチによって増加した静電容量である。
重なり幅Y47=MAX(X軸の差分値43)*変換比率45 (3)
ここで関数MAXは、複数の値の中から最大のものを選択して返す関数である。図4においては、X軸では電極X1の差分値43、Y軸では電極Y3の差分値43がそれぞれ最大である。変換比率45は予め設定された値であり、差分値43の値をタッチパネル1上の長さに変換するための比率である。重なり幅X46および重なり幅Y47は、図5に示すように、それぞれ、タッチパネル1上のタッチされた領域(タッチ領域)と、電極が配置された領域(電極領域6)とが重なる領域のX方向の幅およびY方向の幅である。
タッチ位置(Y座標)=Σ(wi*yi)/Σ(wi) (5)
以上により、タッチ領域が電極領域6からはみ出していない場合のタッチ位置検出の1サイクルが完了し、ステップS2へ戻る。
図5におけるXがX座標、Rが重なり幅Y47/2にそれぞれ対応する。Y座標は、タッチ領域が電極領域6からはみ出していない場合の計算式(5)により求める。また、タッチ領域が電極領域6からY方向にはみ出している場合については、前記の算出方法において、XとYとを入れ替えることで同様にタッチ位置を求められる。
11 保護層
12 絶縁層
13 基板層
X,Y 電極層
X1〜5 電極(X軸)
Y1〜5 電極(Y軸)
2 静電容量検出部
3 制御部
4 記憶部
5 バス接続信号線
6 電極領域
Claims (4)
- 複数のセンサにおける測定値に基づいてタッチ位置を検出するタッチパネル装置において、X方向のタッチ位置およびY方向のタッチ位置を検出するためのセンサ測定値に基づいて、タッチ領域と電極領域とが重なる領域のX方向の幅およびY方向の幅を求め、前記X方向の幅およびY方向の幅から前記タッチ領域の中心の位置を求め、前記中心の位置をタッチ位置として算出するタッチパネル装置であって、第1の方向のタッチ位置を、前記タッチ領域と電極領域とが重なる領域の第1の方向の幅から前記タッチ領域と電極領域とが重なる領域の第2の方向の幅の2分の1を減算した値として算出することを特徴とする、タッチパネル装置。
- 前記タッチ領域の形状は、X方向の幅とY方向の幅の比率が一定であると仮定することを特徴とする、請求項1に記載のタッチパネル装置。
- 前記タッチ領域の形状は、円または楕円であると仮定することを特徴とする、請求項1に記載のタッチパネル装置。
- 前記タッチ領域と電極領域とが重なる領域のX方向の幅を、Y軸のセンサ測定値の最大値に予め設定された値を乗算して求め、前記タッチ領域と電極領域とが重なる領域のY方向の幅を、X軸のセンサ測定値の最大値に予め設定された値を乗算して求めることを特徴とする、請求項1に記載のタッチパネル装置。
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009098235A JP5219908B2 (ja) | 2009-04-14 | 2009-04-14 | タッチパネル装置 |
| KR20100033846A KR101138622B1 (ko) | 2009-04-14 | 2010-04-13 | 터치 패널 장치 |
| US12/759,045 US9024886B2 (en) | 2009-04-14 | 2010-04-13 | Touch-panel device |
| CN2010101642515A CN101866239B (zh) | 2009-04-14 | 2010-04-14 | 触摸面板装置 |
| EP10003950.2A EP2241959B1 (en) | 2009-04-14 | 2010-04-14 | Touch-panel device |
| US13/271,804 US20120031657A1 (en) | 2009-04-14 | 2011-10-12 | Electronic device mounting structure and electronic device mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009098235A JP5219908B2 (ja) | 2009-04-14 | 2009-04-14 | タッチパネル装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2010250493A JP2010250493A (ja) | 2010-11-04 |
| JP5219908B2 true JP5219908B2 (ja) | 2013-06-26 |
Family
ID=43312759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009098235A Active JP5219908B2 (ja) | 2009-04-14 | 2009-04-14 | タッチパネル装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20120031657A1 (ja) |
| JP (1) | JP5219908B2 (ja) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013051530A (ja) * | 2011-08-30 | 2013-03-14 | Yamaha Corp | フェーダ操作子及びそれを備えた操作子装置 |
| US9257396B2 (en) | 2014-05-22 | 2016-02-09 | Invensas Corporation | Compact semiconductor package and related methods |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5036431A (en) * | 1988-03-03 | 1991-07-30 | Ibiden Co., Ltd. | Package for surface mounted components |
| JPH0828583B2 (ja) * | 1992-12-23 | 1996-03-21 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 多層プリント回路基板およびその製作方法、およびボール・ディスペンサ |
| JPH07230352A (ja) * | 1993-09-16 | 1995-08-29 | Hitachi Ltd | タッチ位置検出装置及びタッチ指示処理装置 |
| JP3861333B2 (ja) * | 1996-08-27 | 2006-12-20 | 松下電器産業株式会社 | 座標位置入力装置 |
| KR100435813B1 (ko) * | 2001-12-06 | 2004-06-12 | 삼성전자주식회사 | 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법 |
| SG111069A1 (en) * | 2002-06-18 | 2005-05-30 | Micron Technology Inc | Semiconductor devices including peripherally located bond pads, assemblies, packages, and methods |
| JP3908147B2 (ja) * | 2002-10-28 | 2007-04-25 | シャープ株式会社 | 積層型半導体装置及びその製造方法 |
| TWI231023B (en) * | 2003-05-27 | 2005-04-11 | Ind Tech Res Inst | Electronic packaging with three-dimensional stack and assembling method thereof |
| JP4074862B2 (ja) * | 2004-03-24 | 2008-04-16 | ローム株式会社 | 半導体装置の製造方法、半導体装置、および半導体チップ |
| JP3856150B2 (ja) * | 2005-01-13 | 2006-12-13 | 富士通株式会社 | タッチパネル装置 |
| JP4551255B2 (ja) * | 2005-03-31 | 2010-09-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP4551830B2 (ja) * | 2005-07-08 | 2010-09-29 | 任天堂株式会社 | ポインティングデバイスの入力調整プログラムおよび入力調整装置 |
| JP4758712B2 (ja) * | 2005-08-29 | 2011-08-31 | 新光電気工業株式会社 | 半導体装置の製造方法 |
| US7906846B2 (en) * | 2005-09-06 | 2011-03-15 | Nec Corporation | Semiconductor device for implementing signal transmission and/or power supply by means of the induction of a coil |
| US7429792B2 (en) * | 2006-06-29 | 2008-09-30 | Hynix Semiconductor Inc. | Stack package with vertically formed heat sink |
| JP5302522B2 (ja) * | 2007-07-02 | 2013-10-02 | スパンション エルエルシー | 半導体装置及びその製造方法 |
| JP2009071095A (ja) * | 2007-09-14 | 2009-04-02 | Spansion Llc | 半導体装置の製造方法 |
| JP5358077B2 (ja) * | 2007-09-28 | 2013-12-04 | スパンション エルエルシー | 半導体装置及びその製造方法 |
| US7838967B2 (en) * | 2008-04-24 | 2010-11-23 | Powertech Technology Inc. | Semiconductor chip having TSV (through silicon via) and stacked assembly including the chips |
-
2009
- 2009-04-14 JP JP2009098235A patent/JP5219908B2/ja active Active
-
2011
- 2011-10-12 US US13/271,804 patent/US20120031657A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| JP2010250493A (ja) | 2010-11-04 |
| US20120031657A1 (en) | 2012-02-09 |
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