JP5222464B2 - Display device and electronic device - Google Patents

Description

  The present invention relates to a display device in which a pixel is formed by a light emitting element and a driving method thereof.

  Development of a flat panel display device in which pixels are formed with an electroluminescence element (hereinafter also referred to as a “light emitting element”) is underway. This display device is said to have a wider viewing angle than a liquid crystal display device because the light emitting element of the pixel itself emits light even though the screen is flat. In addition, the advantage of being thinner and lighter than liquid crystal display devices has attracted attention.

In the case of forming a pixel with a light emitting element, an analog gradation method for controlling a current value or a voltage value flowing through the light emitting element is known as a method for controlling the luminance of the pixel (see, for example, Patent Document 1). Further, a time gray scale method for controlling the light emission time of the light emitting element is known (for example, see Patent Document 2). In addition, an area gradation method is known in which one pixel is divided into a plurality of regions and the light emission state of each divided pixel is controlled (see, for example, Patent Document 3).
JP 2003-288055 A JP 2002-123219 A JP 2001-184015 A

  However, the light emitting element has a problem that the luminance changes with the temperature change and the light emission time. Such a deterioration in luminance is a problem to be solved because it appears remarkably as a deterioration in image quality in a display device employing the area gradation method.

  Therefore, an object of the present invention is to improve and stabilize image quality in a display device that performs area gradation using a light emitting element.

  According to the present invention, a light-emitting element having the same configuration as a pixel is provided as a monitor light-emitting element in a part of a display device including a pixel including a light-emitting element, and supplied to the light-emitting element in consideration of variation of the monitor element The gist is to correct the voltage or current.

  The present invention provides a plurality of monitor light emitting elements, a monitor line for monitoring a change in potential of an electrode of the plurality of monitor light emitting elements, and when any of the plurality of monitor light emitting elements is short-circuited, And a means for electrically interrupting a current supplied to the short-circuited monitor light emitting element.

The present invention is a display device having a plurality of sub-pixels formed of light-emitting elements having substantially the same light emission color in one display pixel, and a monitor pixel having the same configuration as the display pixel. It is preferable that the light emitting element provided in the pixel and the light emitting element provided in the monitor pixel have the same structure and are manufactured at the same time in the manufacturing process. The light emitting elements in the monitor pixels are connected to different constant current sources for each sub pixel. In addition, the display device includes a differential amplifier circuit that changes the potential applied to the light emitting element of the display pixel for each sub-pixel in accordance with the change in the potential of the light emitting element in the monitor pixel.

  By providing the monitor light-emitting element having the same configuration as the light-emitting element provided in the pixel, variation in luminance due to change in environmental temperature or deterioration with time can be suppressed. As a result, the image quality can be improved or stabilized.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

  Note that in this specification, connection between elements indicates that they are electrically connected. For this reason, the elements having a connection relationship may be connected via a semiconductor element, a switching element, or the like.

  In this specification, the source electrode and the drain electrode of a transistor are names used to distinguish electrodes other than the gate electrode for the sake of convenience in terms of the structure of the transistor. In the present invention, in the case of a structure that is not limited to the polarity of the transistor, the names of the source electrode and the drain electrode change in consideration of the polarity. Therefore, the source electrode or the drain electrode may be described as one of the one electrode and the other electrode.

(Embodiment 1)
In this embodiment mode, a structure of a panel including a monitor light-emitting element is described with reference to drawings.

  FIG. 1 shows a configuration of a panel provided with a pixel portion 40, a signal line driving circuit 43, a first scanning line driving circuit 41, a second scanning line driving circuit 42, and a monitor circuit 64. This panel is formed using an insulating substrate 20.

  A plurality of pixels 10 are provided in the pixel portion 40, and each pixel is connected to the first light emitting element 13 and the first light emitting element 13 and has a function of controlling current supply. A transistor 12 is provided. The first light emitting element 13 is connected to a power source 18. Each pixel may be provided with a second drive transistor 114 and a second light-emitting element 14 that have the same connection relationship as the first drive transistor 12 and the first light-emitting element 13. The second driving transistor 114 and the second light emitting element 14 may share the power supply with the first driving transistor 12 and the first light emitting element 13 and may be connected in parallel. Here, as shown in FIG. 1, the second light emitting element 14 may have a configuration in which two light emitting elements having the same or substantially the same function as the first light emitting element are connected in parallel. However, the present invention is not limited to this, and one may be used as in the first light emitting element 13. Moreover, the structure which connected the 3 or more some light emitting element in parallel may be sufficient, and the function of these some light emitting elements does not need to be equivalent. For example, the light emitting area may be different from that of the first light emitting element 13. In other words, the second driving transistor 114 and the second light emitting element 14 may be connected in parallel to the first driving transistor 12 and the first light emitting element 13 in one pixel. A more specific configuration of the pixel 10 is exemplified in the following embodiment.

  The monitor circuit 64 includes a first monitor light emitting element 66, a first monitor control transistor 111 connected to the first monitor light emitting element 66, and a first inverter 112. The output terminal of the first inverter 112 is connected to the gate electrode of the first monitor control transistor 111. The input terminal of the first inverter 112 is connected to one of the source and drain electrodes of the first monitor control transistor 111 and the first monitor light emitting element 66. A constant current source 105 is connected to the first monitor control transistor 111 via a power line 113. Other monitor control transistors of the monitor circuit 64 have a function of controlling current supply from the power supply line 113 to each of the plurality of monitor light emitting elements. Since the power supply line 113 is connected to electrodes included in the plurality of monitoring light-emitting elements, the power supply line 113 can have a function of monitoring a change in potential of the electrodes. The constant current source 105 only needs to have a function of supplying a constant current to the power supply line 113. Also, the monitor circuit 64 shares the same power supply as the pixel 10, and a second monitor control connected in parallel with the first monitor control transistor 111, the first monitor light emitting element 66, and the first inverter 112. Transistor 115, second monitor light emitting element 166, and second inverter 116 may be included.

  The first monitor light emitting element 66 is manufactured in the same process under the same manufacturing conditions as the first light emitting element 13, and has the same configuration. Therefore, it has the same characteristics or almost the same characteristics with respect to changes in environmental temperature and deterioration over time. The first monitor light emitting element 66 is connected to a power source 18. Here, since the power source connected to the first light emitting element 13 and the power source connected to the first light emitting element for monitoring 66 have the same potential, they are indicated as the power source 18 using the same reference numerals. Note that although the polarity of the first monitor control transistor 111 is described as a p-channel type in this embodiment mode, the present invention is not limited to this, and an n-channel type may be used. In that case, the surrounding circuit configuration is changed as appropriate.

  The same applies to the second monitor light-emitting element 166, the second monitor control transistor 115, and the second inverter 116. The second monitor light-emitting element 166 has the same manufacturing conditions as the second light-emitting element 14. Thus, they are manufactured in the same process and have the same configuration. Therefore, it has the same characteristics or almost the same characteristics with respect to changes in environmental temperature and deterioration over time. The second monitor light emitting element 166 is connected to a power source 18. Here, the power source connected to the second light emitting element 14 and the power source connected to the second light emitting element for monitoring 166 have the same potential, and therefore, the same reference numeral is used to describe the power source 18. Note that although the polarity of the second monitor control transistor 115 is described as a p-channel type in this embodiment mode, the present invention is not limited to this, and an n-channel type may be used. In that case, the surrounding circuit configuration is changed as appropriate.

  The position where such a monitor circuit 64 is provided is not limited, and is provided between the signal line driver circuit 43 and the pixel unit 40 or between the first or second scanning line driver circuits 41 and 42 and the pixel unit 40. May be.

  A buffer amplifier circuit 110 is provided between the monitor circuit 64 and the pixel unit 40. The buffer amplifier circuit is a circuit having characteristics that an input and an output have the same potential, a high input impedance, and a high output current capacity. Therefore, the circuit configuration can be determined as appropriate as long as the circuit has such characteristics.

  In such a configuration, the buffer amplifier circuit includes the first light emitting element 13 included in the pixel portion 40 in accordance with a change in potential of one electrode of the first monitoring light emitting element 66 and the second monitoring light emitting element 166. And has a function of changing a voltage applied to the second light-emitting element 14.

  In such a configuration, the constant current source 105 and the buffer amplifier circuit 110 in the control circuit 100 may be provided on the same insulating substrate 20 or on different substrates.

  In the above configuration, a constant current is supplied from the constant current source 105 to the first monitor light emitting element 66 and the second monitor light emitting element 166. In this state, when environmental temperature changes or deterioration with time occurs, the resistance values of the first monitor light emitting element 66 and the second monitor light emitting element 166 change. For example, when deterioration with time occurs, the resistance values of the first monitor light emitting element 66 and the second monitor light emitting element 166 increase. Then, since the current value supplied to the first monitor light emitting element 66 and the second monitor light emitting element 166 is constant, both ends of the first monitor light emitting element 66 and the second monitor light emitting element 166 are used. The potential difference changes. Specifically, the potential difference between both electrodes of the first monitor light emitting element 66 and the second monitor light emitting element 166 changes. At this time, since the potential of the electrode connected to the power source 18 is fixed, the potential of the electrode connected to the constant current source 105 changes. This change in the potential of the electrode is supplied to the buffer amplifier circuit 110 through the power supply line 113.

  That is, the change in the potential of the electrode is input to the input terminal of the buffer amplifier circuit 110. The potential output from the output terminal of the buffer amplifier circuit 110 is supplied to the first light emitting element 13 and the second light emitting element 14 via the first driving transistor 12 and the second driving transistor 114. The Specifically, the output potential is supplied as one potential of the electrodes included in the first light-emitting element 13 and the second light-emitting element 14.

  In this way, changes in the first monitor light emitting element 66 and the second monitor light emitting element 166 in accordance with changes in the environmental temperature and changes with time are used as the first light emitting element 13 and the second light emitting element. 14 to feed back. As a result, the first light-emitting element 13 and the second light-emitting element 14 can be lit at a luminance corresponding to a change in environmental temperature or a change with time. Therefore, it is possible to provide a display device that can perform display independent of changes in environmental temperature and changes with time.

  Further, since the plurality of first monitoring light emitting elements 66 and the second monitoring light emitting elements 166 are provided, the first light emitting element 13 and the second light emitting element 14 are averaged by changing their potentials. Can be supplied to. That is, in the present invention, it is preferable to provide a plurality of the first monitor light emitting elements 66 and the second monitor light emitting elements 166 because the potential change can be averaged. Further, by providing a plurality of first monitor light emitting elements 66 and second monitor light emitting elements 166, an alternative to the monitor light emitting element in which a short circuit or the like has occurred can be prepared.

  In addition to the first monitor control transistor 111 and the second monitor control transistor 115 connected to the first monitor light emitting element 66 and the second monitor light emitting element 166, the first inverter 112 and It is preferable to provide the second inverter 116. This is provided in consideration of a malfunction of the monitor circuit 64 caused by a defect (including an initial defect and a aging defect) of the first monitor light emitting element 66 and the second monitor light emitting element 166. For example, when the constant current source 105 is connected to the first monitor control transistor 111 and the second monitor control transistor 115 without any other transistor, among the plurality of monitor light emitting elements, Consider a case in which the first and second monitoring light emitting elements 66 and 166 are short-circuited between the anode and the cathode of the monitoring light emitting element due to defects during the manufacturing process. Then, a large amount of current from the constant current source 105 is supplied to the short-circuited first monitor light emitting element 66 and second monitor light emitting element 166 through the power supply line 113. Since the plurality of monitor light emitting elements are connected in parallel to each other, when a large amount of current is supplied to the shorted first monitor light emitting element 66 and the second monitor light emitting element 166, the other monitor light emitting elements are used. A predetermined constant current is not supplied to the light emitting element. As a result, appropriate changes in the potentials of the first light-emitting element 66 and the second light-emitting element 166 cannot be supplied to the first light-emitting element 13 and the second light-emitting element 14. .

  Such a short-circuit of the monitoring light emitting element causes the anode potential and the cathode potential of the monitoring light emitting element to be the same. For example, a short circuit may occur due to dust or the like between the anode and the cathode during the manufacturing process. In addition to the short circuit between the anode and the cathode, the light emitting element for monitoring may be short circuited due to a short circuit between the scanning line and the anode.

  Thus, in this embodiment, in addition to the first monitor control transistor 111 and the second monitor control transistor 115, a first inverter 112 and a second inverter 116 are provided. The first monitor control transistor 111 and the second monitor control transistor 115 supply a large amount of current due to a short circuit of the first monitor light emitting element 66 and the second monitor light emitting element 166 as described above. In order to prevent this, supply of current to the short-circuited first monitor light-emitting element 66 and second monitor light-emitting element 166 is stopped. That is, the short-circuited monitor light emitting element and the monitor line are electrically cut off.

  The first inverter 112 and the second inverter 116 have a function of outputting a potential for turning off the monitor control transistor when any of the plurality of monitor light emitting elements is short-circuited. In addition, the first inverter 112 and the second inverter 116 have a function of outputting a potential for turning on the monitor control transistor when none of the plurality of monitor light emitting elements is short-circuited.

  The detailed operation of the monitor circuit 64 will be described with reference to FIG. As shown in FIG. 6A, in the electrode of the first monitor light emitting element 66, when the high potential side is the anode electrode 66a and the low potential side is the cathode electrode 66c, the anode electrode 66a is the first inverter 112. The cathode electrode 66c is connected to the power source 18 and has a fixed potential. Therefore, when the anode and cathode of the first monitor light emitting element 66 are short-circuited, the potential of the anode electrode 66a approaches the potential of the cathode electrode 66c. As a result, a low potential close to the potential of the cathode electrode 66c is supplied to the first inverter 112, so that the p-channel transistor 112p included in the first inverter 112 is turned on. Then, the high potential side potential (Va) is output from the first inverter 112 and becomes the gate potential of the first monitor control transistor 111. That is, the potential input to the gate of the first monitor control transistor 111 is Va, and the first monitor control transistor 111 is turned off.

  Similarly, in the electrode of the second monitor light emitting element 166, when the high potential side is the anode electrode 166a and the low potential side is the cathode electrode 166c, the anode electrode 166a is connected to the input terminal of the second inverter 116, The cathode electrode 166c is connected to the power source 18 and has a fixed potential. Therefore, when the anode and the cathode of the second monitor light emitting element 166 are short-circuited, the potential of the anode electrode 166a approaches the potential of the cathode electrode 166c. As a result, a low potential close to the potential of the cathode electrode 166c is supplied to the second inverter 116, so that the p-channel transistor 116p included in the second inverter 116 is turned on. Then, the high potential side potential (Va) is output from the second inverter 116 and becomes the gate potential of the second monitor control transistor 115. That is, the potential input to the gate of the second monitor control transistor 115 is Va, and the second monitor control transistor 115 is turned off.

  Note that the VDD that is a high potential (High) is set equal to or higher than the anode potential. Further, the low potential (Low) of the first inverter 112 and the second inverter 116, the potential of the power source 18, the low side potential of the power source line 113, and the low side potential applied to Va can all be made equal. In general, the low side potential is ground. However, the present invention is not limited to this, and the low-side potential may be determined so as to have a predetermined potential difference from the high-side potential. The predetermined potential difference can be determined by the current, voltage, luminance characteristics, or device specifications of the luminescent material.

  Here, attention is paid to the order in which a constant current is supplied to the first monitor light emitting element 66 and the second monitor light emitting element 166. It is necessary to start flowing a constant current through the power supply line 113 with the first monitor control transistor 111 and the second monitor control transistor 115 turned on. In this embodiment mode, current starts to flow through the power supply line 113 while Va is kept low as shown in FIG. Then, Va is set to VDD after the potential of the power supply line 113 is saturated. As a result, even when the first monitor control transistor 111 and the second monitor control transistor 115 are on, the capacitor and parasitic capacitance associated with the power supply line 113 can be charged.

  On the other hand, when the first monitor light emitting element 66 and the second monitor light emitting element 166 are not short-circuited, the potentials of the anode electrode 66a and the anode electrode 166a are supplied to the first inverter 112 and the second inverter 116. Therefore, the n-channel transistors 112n and 116n are turned on. Then, the potential on the low potential side is output from the first inverter 112 and the second inverter 116, and the first monitor control transistor 111 and the second monitor control transistor 115 are turned on.

  In this way, the current from the constant current source 105 can be prevented from being supplied to the short-circuited monitoring light emitting element. Therefore, in the case where there are a plurality of monitor light emitting elements, when the monitor light emitting element is short-circuited, a change in the potential of the power supply line 113 can be minimized by cutting off the current supply to the shorted monitor light emitting element. . As a result, appropriate changes in the potentials of the first light-emitting element 66 and the second light-emitting element 166 can be supplied to the first light-emitting element 13 and the second light-emitting element 14.

  Note that in this embodiment mode, the constant current source 105 may be any circuit that can supply a constant current and can be manufactured using a transistor, for example. In the present embodiment, the monitor circuit 64 is described as having a plurality of monitor light emitting elements, monitor control transistors, and inverters, but the present invention is not limited to this. For example, the inverter detects any short circuit of the monitor light emitting element, and any circuit can be used as long as it has a function of cutting off the current supplied to the shorted monitor light emitting element via the monitor line. May be used. Specifically, it is only necessary to have a function of turning off the monitor control transistor in order to cut off the current supplied to the shorted monitor light emitting element.

  In this embodiment mode, a plurality of light emitting elements for monitoring are used. In this case, even if one of the monitor elements causes an operation failure, the other monitor elements are operated, so that a change in the characteristics of the light-emitting element due to environmental temperature change or deterioration with time is monitored, and the light-emitting element in the pixel 10 Can be corrected.

  In this embodiment, the buffer amplifier circuit 110 is provided to prevent potential fluctuation. Accordingly, another circuit may be used instead of the buffer amplifier circuit 110 as long as it is a circuit that can prevent potential fluctuations, such as the buffer amplifier circuit 110. That is, when the potential of one electrode of the first monitor light emitting element 66 and the second monitor light emitting element 166 is transmitted to the first light emitting element 13 and the second light emitting element 14, the first monitor light emitting element is emitted. When a circuit for preventing potential fluctuation is provided between the element 66 and the second light emitting element 166 for monitoring and the first light emitting element 13 and the second light emitting element 14, as such a circuit, The circuit is not limited to the buffer amplifier circuit 110, and a circuit having any configuration such as an operational amplifier circuit may be used.

  Here, another circuit configuration in the present embodiment will be described below with reference to FIG. The circuit configuration of FIG. 2 is the same as that of FIG. 1 in the element arrangement in each pixel 10 and the monitor circuit 64, but the power supply connection method is different from that in FIG. In other words, not only the power supply line 113 that is common in FIG. 1 but also a power supply line 117 is added so that each subpixel can be driven by an independent power supply. Thus, in this embodiment mode, the power supply line may be connected independently for each sub-pixel. At that time, the constant current source 105 and the buffer amplifier circuit 110 may be arranged independently in each power source.

  As described above, the advantage of disposing the power supply line for each subpixel and the constant current source 105 and the buffer amplifier circuit 110 in the control circuit 200 connected to the subpixel is that the current value flowing through the monitor element is set for each subpixel. It can be mentioned that the accuracy of correction can be increased by setting. In the case of performing area gradation using the sub-pixel as in this embodiment mode, the characteristics of the first light-emitting element 13 and the second light-emitting element 14 can be different. For example, when the same voltage is applied to both sub-pixels, the driving voltage and the light emission duty are changed when the luminance of the light-emitting element of one sub-pixel is made twice that of the other sub-pixel. In other words, four gradations of 0, 1, 2, and 3 can be expressed by the luminance ratio. As described above, when the characteristics of the light emitting elements of the respective sub-pixels are different from each other, the deterioration and the change in the characteristics due to the temperature are not necessarily the same in both cases. Therefore, the change in characteristics due to the combination of elements having different characteristics becomes very complicated. In order to perform correction more accurately, it is effective to divide elements having similar characteristics. A power supply line, a constant current source 105 connected thereto, and a buffer amplifier circuit 110 are arranged for each subpixel, and the characteristics of the first monitor light emitting element 66 and the second monitor light emitting element 166 are the same as those of the pixel 10. If this is done, more accurate correction can be realized.

  In the present embodiment, the number of subpixels is shown only when it is two, but the number of subpixels is not limited to this. Any number is acceptable as long as they are connected in parallel.

(Embodiment 2)
In this embodiment mode, a circuit configuration for turning off the monitor control transistor when the monitor light emitting element is short-circuited and the operation thereof will be described, unlike the above embodiment mode. In the first embodiment, the pixel circuit including the sub-pixel is described. However, the present embodiment is described when the monitor light emitting element arranged in each sub-pixel is short-circuited. Since this relates to a circuit configuration in which the monitor control transistor is turned off, the description will be made for each sub-pixel circuit and will not be repeated.

  A monitor circuit 64 shown in FIG. 7A includes a p-channel first transistor 80, an n-channel second transistor 81 having a gate electrode common to the first transistor 80 and connected in parallel. An n-channel third transistor 82 connected in series to the second transistor 81 is included. The monitor light emitting element 66 is connected to the gate electrodes of the first and second transistors 80 and 81. The gate electrode of the monitor control transistor 111 is connected to the electrode to which the first and second transistors 80 and 81 are connected to each other. Other configurations are the same as those of the monitor circuit 64 shown in FIG. 6, but only the sub-pixel including the monitor control transistor 111 and the monitor light emitting element 66 is illustrated here.

  The potential on the high potential side of the first p-channel transistor 80 is Va, and the potential of the gate electrode of the third n-channel transistor 82 is Vb. Then, the potential of the power supply line 113 and the potentials of Va and Vb are operated as shown in FIG.

  First, the capacitive element and parasitic capacitance associated with the power supply line 113 are fully charged, and then the potential of Va is set to High. When the monitor light emitting element 66 is short-circuited, the potential of the anode of the monitor light emitting element 66, that is, the potential at the point D is lowered to the same level as the cathode of the monitor light emitting element 66. Then, a low potential, that is, Low is input to the gate electrodes of the first and second transistors 80 and 81, the n-channel second transistor 81 is turned off, and the p-channel first transistor is turned on. 80 turns on. Then, a high side potential, which is one potential of the first transistor 80, is input to the gate electrode of the monitor control transistor 111, and the monitor control transistor 111 is turned off. As a result, the current from the power supply line 113 is not supplied to the short-circuited monitor light emitting element 66.

  At this time, when the short-circuit state is slight and the potential of the anode slightly decreases, it may be difficult to control which of the first and second transistors 80 and 81 is turned on or off. . Therefore, as shown in FIG. 7, the potential of Vb is supplied to the gate electrode of the third transistor 82. That is, as shown in FIG. 7B, the potential of Vb is set to Low while Va is High. Then, the n-channel third transistor 82 is turned off. As a result, when the potential of the anode is lower than VDD by the threshold voltage of the first transistor, the first transistor 80 can be turned on and the monitor control transistor 111 can be turned off. .

  By controlling the potential of Vb in this way, the monitor control transistor 111 can be accurately turned off even when the potential of the anode is slightly lowered. When the monitor light emitting element is normal, the monitor control transistor 111 is controlled to be turned on. That is, since the potential of the anode is almost the same as the high potential of the power supply line 113, the second transistor 81 is turned on. As a result, since the low potential is applied to the gate electrode of the monitor control transistor 111, the transistor is turned on.

  As shown in FIG. 8A, a p-channel first transistor 83, a p-channel second transistor 84 connected in series to the first transistor 83, and a second transistor 84. And an n-channel third transistor 85 having a common gate electrode and an n-channel fourth transistor 86 having a common gate electrode and the first transistor and connected in parallel. The monitor light emitting element 66 is connected to the gate electrodes of the second and third transistors 84 and 85. The gate electrode of the monitor control transistor 111 is connected to the electrode to which the second and third transistors 84 and 85 are connected to each other. Further, the gate electrode of the monitor control transistor 111 is connected to one electrode of the fourth transistor 86. Other configurations are the same as those of the monitor circuit 64 shown in FIG.

  First, the capacitive element and parasitic capacitance associated with the power supply line 113 are fully charged, and then the potential of Ve is set to Low. When the monitor light emitting element 66 is short-circuited, the potential of the anode of the monitor light emitting element 66, that is, the potential at the point D is lowered to the same level as the cathode of the monitor light emitting element 66. Then, a low potential, that is, Low is input to the gate electrodes of the second and third transistors 84 and 85, the n-channel third transistor 85 is turned off, and the p-channel second transistor is turned on. 84 is turned on. When the potential of Ve is Low, the first transistor 83 is turned on and the fourth transistor 86 is turned off. Then, the high side potential of the first transistor is input to the gate electrode of the monitor control transistor 111 via the second transistor 84 and turned off. As a result, the current from the power supply line 113 is not supplied to the short-circuited monitor light emitting element 66. Thus, by controlling the voltage Ve of the gate electrode, the monitor control transistor 111 can be accurately turned off.

(Embodiment 3)
A reverse voltage can be applied to the light emitting element and the monitor light emitting element. Therefore, in this embodiment, a case where a reverse voltage is applied will be described.

  The reverse voltage is a voltage obtained by inverting a high-side potential and a low-side potential in a forward voltage when a voltage applied when the light-emitting element 13 or the monitor light-emitting element 66 emits light is a forward voltage. Is applied. Specifically, using the monitor light emitting element 66, the potential applied to the power supply line 113 is made lower than the potential of the power supply 18 in order to invert the potentials of the anode electrode 66a and the cathode electrode 66c.

  Specifically, as shown in FIG. 14, the potential of the anode electrode 66a (anode potential: Va) and the potential of the cathode electrode 66c (cathode potential: Vc) are set to a low potential. At the same time, the potential (V113) of the power supply line 113 is also inverted. A period in which the anode potential and the cathode potential are inverted is referred to as a reverse voltage application period. Then, after a predetermined reverse voltage application period elapses, the cathode potential is returned, and a constant current is supplied to the power supply line 113 to complete charging, that is, after the voltage is saturated, the potential is returned. At this time, the reason why the potential of the power supply line 113 returns to a curved line is that a plurality of monitor light emitting elements are charged with a constant current, and further parasitic capacitance is charged.

  Preferably, the anode potential is inverted and then the cathode potential is inverted. Then, after a predetermined reverse voltage period has elapsed, the anode potential is returned, and then the cathode potential is returned. Simultaneously with the inversion of the anode potential, the potential of the power supply line 113 is charged to High.

  In this reverse voltage application period, the driving transistor 12 and the monitor control transistor 111 must be on.

  As a result of applying the reverse voltage to the light emitting element, the defective state of the light emitting element 13 and the monitoring light emitting element 66 can be improved, and the reliability can be improved. In addition, the light emitting element 13 and the monitor light emitting element 66 have an initial failure in which the anode and the cathode are short-circuited due to adhesion of foreign matter, pinholes due to minute protrusions on the anode or the cathode, and unevenness of the light emitting layer. May occur. When such an initial failure occurs, lighting and non-lighting according to the signal are not performed, and most of the current flows through the shorted element. As a result, there arises a problem that the image is not displayed favorably. In addition, this defect may occur in any pixel.

  Therefore, as in the present embodiment, when a reverse voltage is applied to the light emitting element 13 and also to the monitor light emitting element 66, a local current flows through the shorted portion, and the shorted portion generates heat, which is oxidized or carbonized. Can be made. As a result, the shorted portion can be insulated, and a current flows in a region other than that portion, so that the light emitting element 13 or the monitoring light emitting element 66 can be operated normally. By applying the reverse voltage in this way, even if an initial failure occurs, the failure can be eliminated. Such insulation of the short-circuited portion is preferably performed before shipment.

  In addition to the initial failure, a short circuit between the anode and the cathode may occur as time passes. Such a defect is also called a progressive defect. Therefore, as in the present invention, by applying a reverse voltage to the light emitting element 13 and the monitoring light emitting element 66 periodically, even if a progressive defect occurs, the defect can be eliminated. 13 or the monitor light emitting element 66 can be operated normally.

  In addition, image burn-in can be prevented by applying a reverse voltage. Image burn-in occurs due to the deterioration state of the light emitting element 13, but the deterioration state can be reduced by applying a reverse voltage. As a result, image burn-in can be prevented.

  In general, the deterioration of the light emitting element 13 and the monitoring light emitting element 66 progresses greatly in the initial stage, and the degree of progress of the deterioration decreases with time. That is, in the pixel, the light-emitting element 13 and the monitor light-emitting element 66 once deteriorated are less likely to be further deteriorated. As a result, each light emitting element 13 varies. Therefore, before shipping or when no image is displayed, all the light-emitting elements 13 and further the monitor light-emitting elements 66 are turned on to cause deterioration of the non-deteriorated elements, thereby reducing the deterioration state of all the elements. Can be averaged. Such a structure for lighting all elements may be provided in the display device.

(Embodiment 4)
In this embodiment, an example of a pixel circuit and a structure is described. FIG. 3 shows a pixel circuit that can be used in the pixel portion of the present invention. In the pixel portion 40, data lines Sx, gate lines Gy, and power supply lines Vx are provided in a matrix, and pixels 10 are provided at intersections thereof. The pixel 10 includes a switching transistor 11, a driving transistor 12, a capacitor 16, and a light emitting element 13.

  A connection relationship in the pixel will be described. The switching transistor 11 is provided at the intersection of the data line Sx and the gate line Gy. One electrode of the switching transistor 11 is connected to the signal line Sx, and the gate electrode of the switching transistor 11 is connected to the gate line Gy. Yes. The driving transistor 12 has one electrode connected to the power supply line Vx and the gate electrode connected to the other electrode of the switching transistor 11. The capacitive element 16 is provided so as to hold a voltage between the gate and the source of the driving transistor 12. In the present embodiment, the capacitor 16 has one electrode connected to Vx and the other electrode connected to the gate electrode of the driving transistor 12. Note that the capacitor 16 need not be provided when the gate capacitance of the driving transistor 12 is large and the leakage current is small. The light emitting element 13 is connected to the other electrode of the driving transistor 12.

  A method for driving such a pixel will be described. First, when the switching transistor 11 is turned on, a video signal is input from the signal line Sx. Based on the video signal, charges are accumulated in the capacitor 16. When the charge accumulated in the capacitor 16 exceeds the voltage (Vgs) between the gate and the source of the driving transistor 12, the driving transistor 12 is turned on. Then, a current is supplied to the light emitting element 13 and it is lit. At this time, the driving transistor 12 can be operated in a linear region or a saturation region. When operating in the saturation region, a constant current can be supplied. Further, when operating in a linear region, it can be operated at a low voltage, and power consumption can be reduced.

  Hereinafter, a pixel driving method will be described with reference to a timing chart. FIG. 9A shows a timing chart of one frame period in which an image of 60 frames is rewritten per second. In the timing chart, the vertical axis indicates scanning lines (from the first line to the last line), and the horizontal axis indicates time.

  One frame period has m (m is a natural number of 2 or more) subframe periods SF1, SF2,..., SFm, and the m subframe periods SF1, SF2,. ,..., Tam, a display period (lighting period) Ts1, Ts2,..., Tsm, and a reverse voltage application period. In this embodiment mode, as shown in FIG. 9A, in one frame period, subframe periods SF1, SF2, and SF3 and a reverse voltage application period (RB) are provided. In each subframe period, the writing operation periods Ta1 to Ta3 are sequentially performed, and become display periods Ts1 to Ts3, respectively.

  The timing chart shown in FIG. 9B shows a writing operation period, a display period, and a reverse voltage application period when attention is paid to a certain row (i-th row). After the writing operation period and the display period appear alternately, a reverse voltage application period appears. The period having the writing operation period and the display period is a forward voltage application period.

  The write operation period Ta can be divided into a plurality of operation periods. In the present embodiment, the operation is divided into two operation periods, and an erase operation is performed on one side and a write operation is performed on the other side. In order to provide the erase operation and the write operation in this way, a WE (Write Erase) signal is input. Details of other erase operations, write operations, and signals will be described in the following embodiments. Further, immediately before the reverse voltage application period, a period in which the switching transistors of all the pixels are simultaneously turned on, that is, a period in which all the scanning lines are turned on (on period) is provided.

  Immediately after the reverse voltage application period, it is preferable to provide a period in which the switching transistors of all the pixels are simultaneously turned off, that is, a period in which all the scanning lines are turned off (off period). An erasing period (SE) is provided immediately before the reverse voltage application period. The erasing period can be performed by the same operation as the erasing operation. In the erasing period, an operation of sequentially erasing data written in SF3 in the immediately preceding subframe period, in this embodiment, is sequentially performed. This is because in the on period, the switching transistors are turned on all at once after the display period of the pixels in the last row ends, and thus the pixels in the first row and the like have an unnecessary display period.

  In this manner, control for providing the on period, the off period, and the erasing period is performed by a driving circuit such as a scanning line driving circuit or a signal line driving circuit. Note that the timing of applying the reverse voltage to the light emitting element 13, that is, the reverse voltage application period is not limited to FIGS. That is, it is not necessary to provide a reverse voltage application period for each frame. Further, it is not necessary to provide a reverse voltage application period in the second half of one frame. The on period may be at least immediately before the application period (RB), and the off period may be at least immediately after the application period (RB). Further, the order in which the anode voltage and the cathode voltage of the light-emitting element are reversed is not limited to that shown in FIGS. That is, the potential of the anode electrode may be lowered after the potential of the cathode electrode is raised.

  FIG. 4 shows a layout example of the pixel circuit shown in FIG. A semiconductor film constituting the switching transistor 11 and the driving transistor 12 is formed. After that, a first conductive film is formed through an insulating film functioning as a gate insulating film. The conductive film can be used as the gate electrode of the switching transistor 11 and the driving transistor 12 and can be used as the gate line Gy. At this time, the switching transistor 11 may have a double gate structure.

  After that, a second conductive film is formed through an insulating film functioning as an interlayer insulating film. The conductive film can be used as a drain wiring and a source wiring of the switching transistor 11 and the driving transistor 12, and can also be used as a signal line Sx and a power supply line Vx. At this time, the capacitor 16 can be formed by a stacked structure of a first conductive film, an insulating film functioning as an interlayer insulating film, and a second conductive film. The gate electrode of the driving transistor 12 and the other electrode of the switching transistor are connected via a contact hole.

  A first electrode 19 (pixel electrode) is formed in the opening provided in the pixel. The pixel electrode is connected to the other electrode of the driving transistor 12. At this time, when an insulating film or the like is provided between the second conductive film and the pixel electrode, it is necessary to connect through a contact hole. In the case where an insulating film or the like is not provided, the pixel electrode can be directly connected to the other electrode of the driving transistor 12.

  In the layout as shown in FIG. 4, the first conductive film and the pixel electrode may overlap in order to ensure a high aperture ratio. In such a region, a coupling capacitance may occur. This coupling capacity is an unnecessary capacity.

  FIG. 5 shows an example of a cross-sectional view taken along the lines AB and BC shown in FIG. A semiconductor film is formed on the insulating substrate 20 via a base film. As the insulating substrate 20, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a stainless steel substrate, or the like can be used. In addition, substrates made of plastics typified by PET (polyethylene terephthalate) and PEN (polyethylene naphthalate) and flexible synthetic resins such as acrylic are generally lower in heat resistant temperature than other substrates. Although there is a tendency, it can be used as long as it can withstand the processing temperature in the manufacturing process. As the base film, an insulating film such as silicon oxide, silicon nitride, or silicon nitride oxide can be used.

  An amorphous semiconductor film is formed over the base film. The thickness of the amorphous semiconductor film is 25 to 100 nm (preferably 30 to 60 nm). As the amorphous semiconductor, not only silicon but also silicon germanium can be used.

  Next, the amorphous semiconductor film is crystallized as necessary to form a crystalline semiconductor film. As a method for crystallization, a heating furnace, laser irradiation, irradiation with light emitted from a lamp (hereinafter referred to as lamp annealing), or a combination thereof can be used. For example, a crystalline semiconductor film is formed by adding a metal element to an amorphous semiconductor film and performing heat treatment using a heating furnace. Thus, it is preferable to add a metal element because crystallization can be performed at a low temperature. The crystalline semiconductor film thus formed is processed into a predetermined shape. The predetermined shape is a shape that becomes the switching transistor 11 and the driving transistor 12 as shown in FIG.

  Next, an insulating film functioning as a gate insulating film is formed. The insulating film is formed to have a thickness of 10 nm to 150 nm, preferably 20 nm to 40 nm so as to cover the semiconductor film. For example, a silicon oxynitride film, a silicon oxide film, or the like can be used, and a single layer structure or a stacked structure may be used.

  Then, a first conductive film functioning as a gate electrode is formed through the gate insulating film. The gate electrode may be a single layer or a stacked layer, but in this embodiment mode, a stacked structure of conductive films 22a and 22b is used. Each of the conductive films 22a and 22b may be formed of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. In this embodiment, a tantalum nitride film with a thickness of 10 nm to 50 nm, for example, 30 nm is formed as the conductive film 22a, and a tungsten film with a thickness of 200 nm to 400 nm, for example, 370 nm is sequentially formed as the conductive film 22b.

  An impurity element is added using the gate electrode as a mask. At this time, a low concentration impurity region may be formed in addition to the high concentration impurity region. This is referred to as an LDD (Lightly Doped Drain) structure. In particular, a structure in which a low-concentration impurity region overlaps with a gate electrode is referred to as a GOLD (Gate-drain Overlapped LDD) structure. In particular, the n-channel transistor preferably has a structure having a low concentration impurity region.

  Thereafter, insulating films 28 and 29 functioning as the interlayer insulating film 30 are formed. The insulating film 28 may be an insulating film containing nitrogen, and in this embodiment mode, is formed using a 100 nm silicon nitride film by a plasma CVD method.

  The insulating film 29 can be formed using an organic material or an inorganic material. As the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used. Siloxane has a skeletal structure composed of a bond of silicon (Si) and oxygen (O) and contains at least hydrogen as a substituent, or at least one of fluorine, an alkyl group, and aromatic hydrocarbon as a substituent. A polymeric material having a starting material. Polysilazane is a polymer material having a bond of silicon (Si) and nitrogen (N). As the inorganic material, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y) (x, y = 1, 2,... An insulating film containing oxygen or nitrogen such as ()) can be used. Further, as the insulating film 29, a laminated structure of these insulating films may be used. In particular, when the insulating film 29 is formed using an organic material, the flatness is improved, but moisture and oxygen are absorbed by the organic material. In order to prevent this, an insulating film containing an inorganic material is preferably formed over the organic material. When an insulating film containing nitrogen is used as the inorganic material, entry of alkali ions such as Na can be prevented, which is preferable. When an organic material is used for the insulating film 29, flatness can be improved, which is preferable.

  Contact holes are formed in the interlayer insulating film 30. Then, a second conductive film which functions as the switching transistor 11, the source wiring and drain wiring 24 of the driving transistor 12, the signal line Sx, and the power supply line Vx is formed. As the second conductive film, a film made of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si) or an alloy film using these elements can be used. . In this embodiment mode, the second conductive film is formed by stacking a titanium film to 60 nm, a titanium nitride film to 40 nm, a titanium and aluminum alloy film to 300 nm, and a titanium film to 100 nm. Thereafter, an insulating film 31 is formed so as to cover the second conductive film. The material shown for the interlayer insulating film 30 can be used for the insulating film 31. By providing the insulating film 31 in this way, the aperture ratio can be increased.

Then, the first electrode 19 (pixel electrode) is formed in the opening provided in the insulating film 31. In order to enhance the step coverage of the pixel electrode in the opening, it is preferable to round the end surface of the opening so as to have a plurality of radii of curvature. For the first electrode 19, as a light-transmitting material, indium tin oxide (ITO), IZO (indium zinc oxide) in which indium oxide is mixed with 2 to 20% zinc oxide (ZnO), are used. It is also possible to use ITO-SiOx, organic indium, organic tin, or the like in which 2 to 20% silicon oxide (SiO ₂ ) is mixed with indium oxide. In addition to silver (Ag), an element selected from tantalum, tungsten, titanium, molybdenum, aluminum, and copper, or an alloy material or a compound material containing the element as a main component is used as the non-light-transmitting material. it can. At this time, when the insulating film 31 is formed using an organic material and the flatness is increased, the flatness of the pixel electrode formation surface is improved, so that a uniform voltage can be applied and further a short circuit can be prevented.

  In a region 430 where the first conductive film overlaps with the pixel electrode, a coupling capacitance may be generated. This coupling capacity is an unnecessary capacity.

  Thereafter, the partition wall 32 is formed, and the light emitting layer 33 is formed by a vapor deposition method or an ink jet method. The light emitting layer 33 includes an organic material or an inorganic material, and includes an electron injection layer (EIL), an electron transport layer (ETL), a light emitting layer (EML), a hole transport layer (HTL), and a hole injection layer (HIL). Etc. are appropriately combined. Note that the boundaries between the layers are not necessarily clear, and there are cases where the materials constituting the layers are partially mixed and the interface is unclear. The light emitting layer is not limited to the above laminated structure.

An inorganic material can be used as a base material for forming the light emitting layer 33. As the inorganic material, a sulfide, oxide, or nitride of a metal material such as zinc, cadmium, or gallium is preferably used. For example, as sulfides, zinc sulfide (ZnS), cadmium sulfide (CdS), calcium sulfide (CaS), yttrium sulfide (Y ₂ S ₃ ), gallium sulfide (Ga ₂ S ₃ ), strontium sulfide (SrS), barium sulfide (BaS) or the like can be used. As the oxide, zinc oxide (ZnO), yttrium oxide (Y ₂ O ₃ ), or the like can be used. As the nitride, aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or the like can be used. Furthermore, zinc selenide (ZnSe), zinc telluride (ZnTe), and the like can also be used, such as calcium sulfide-gallium sulfide (CaGa ₂ S ₄ ), strontium sulfide-gallium (SrGa ₂ S ₄ ), barium sulfide-gallium (BaGa). Ternary mixed crystals such as ₂ S ₄ ).

  As an impurity element, manganese (Mn), copper (Cu), samarium (Sm), terbium (Tb), erbium (Er), thulium (as a light emitting center utilizing inner-shell electronic transition of a metal ion) Metal elements such as Tm), europium (Eu), cerium (Ce), and praseodymium (Pr) can be used. Note that a halogen element such as fluorine (F) or chlorine (Cl) may be added as charge compensation.

  In addition, a light-emitting material including a first impurity element and a second impurity element can be used as a light-emission center using donor-acceptor recombination. As the first impurity element, for example, a metal element such as copper (Cu), silver (Ag), gold (Au), platinum (Pt), silicon (Si), or the like can be used. Examples of the second impurity element include fluorine (F), chlorine (Cl), bromine (Br), iodine (I), boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium. (Tl) or the like can be used.

  The luminescent material is a solid phase reaction, that is, a base material and an impurity element are weighed, mixed in a mortar, heated in an electric furnace, and reacted to cause the base material to contain the impurity element. For example, the base material, the first impurity element or the compound containing the first impurity element, and the second impurity element or the compound containing the second impurity element are weighed and mixed in a mortar, Heat and fire. The firing temperature is preferably 700 to 1500 ° C. This is because the solid reaction does not proceed when the temperature is too low, and the base material is decomposed when the temperature is too high. In addition, although baking may be performed in a powder state, it is preferable to perform baking in a pellet state.

In addition, as an impurity element in the case of using a solid phase reaction, a compound composed of a first impurity element and a second impurity element may be used in combination. In this case, since the impurity element is easily diffused and the solid-phase reaction easily proceeds, a uniform light emitting material can be obtained. Further, since no extra impurity element is contained, a light-emitting material with high purity can be obtained. Examples of the compound composed of the first impurity element and the second impurity element include copper fluoride (CuF ₂ ), copper chloride (CuCl), copper iodide (CuI), copper bromide (CuBr), and nitride Copper (Cu ₃ N), copper phosphide (Cu ₃ P), silver fluoride (CuF), silver chloride (CuCl), silver iodide (CuI), silver bromide (CuBr), gold chloride (AuCl ₃ ), Gold bromide (AuBr ₃ ), platinum chloride (PtCl ₂ ), or the like can be used. Alternatively, a light emitting material containing a third impurity element may be used instead of the second impurity element.

  Examples of the third impurity element include lithium (Li), sodium (Na), potassium (K), rubidium (Rb), cesium (Cs), nitrogen (N), phosphorus (P), arsenic (As), and antimony. (Sb), bismuth (Bi), or the like can be used. The concentration of these impurity elements may be 0.01 to 10 mol%, preferably 0.1 to 5 mol%, based on the base material.

  As a light-emitting material having high electrical conductivity, a light-emitting material in which the above-described material is used as a base material and a light-emitting material containing the first impurity element, the second impurity element, and the third impurity element is added. Can be used. The concentration of these impurity elements may be 0.01 to 10 mol%, preferably 0.1 to 5 mol% with respect to the base material.

  Examples of the compound composed of the second impurity element and the third impurity element include lithium fluoride (LiF), lithium chloride (LiCl), lithium iodide (LiI), copper bromide (LiBr), and sodium chloride. Alkali halides such as (NaCl), boron nitride (BN), aluminum nitride (AlN), aluminum antimony (AlSb), gallium phosphide (GaP), gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs) Indium antimony (InSb) or the like can be used.

  A light-emitting layer using the above-described material as a base material and using the above-described light-emitting material including the first impurity element, the second impurity element, and the third impurity element requires hot electrons accelerated by a high electric field. Without emitting light. That is, since it is not necessary to apply a high voltage to the light emitting element, a light emitting element that can operate with a low driving voltage can be obtained. In addition, since light can be emitted with a low driving voltage, a light-emitting element with reduced power consumption can be obtained. Further, an element that becomes another light emission center may be included.

  Alternatively, the above-described material can be used as a base material, and a light-emitting material including a light-emitting center using the second impurity element, the third impurity element, and the above-described inner-shell electron transition of a metal ion can be used. In this case, the metal ion serving as the emission center is preferably 0.05 to 5 atomic% with respect to the base material. Moreover, it is preferable that the density | concentration of a 2nd impurity element is 0.05-5 atomic% with respect to a base material. Moreover, it is preferable that the density | concentration of a 3rd impurity element is 0.05-5 atomic% with respect to a base material. The light emitting material having such a structure can emit light at a low voltage. Accordingly, a light-emitting element that can emit light at a low driving voltage can be obtained, and thus a light-emitting element with reduced power consumption can be obtained. Further, an element that becomes another light emission center may be included. By using such a light emitting material, luminance deterioration of the light emitting element can be suppressed. Further, the transistor can be driven at a low voltage.

  Then, the second electrode 35 is formed by a vapor deposition method. The first electrode 19 (pixel electrode) and the second electrode 35 of the light emitting element serve as an anode or a cathode depending on the pixel configuration. As the anode material, it is preferable to use a metal, an alloy, an electrically conductive compound, a mixture thereof, or the like having a high work function (work function of 4.0 eV or more). Specific examples of the anode material include ITO, IZO mixed with 2 to 20% zinc oxide (ZnO) in indium oxide, gold (Au), platinum (Pt), nickel (Ni), tungsten (W), Chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), nitride of metal material (TiN), or the like can be used.

On the other hand, as the cathode material, it is preferable to use a metal, an alloy, an electrically conductive compound, a mixture thereof, or the like having a low work function (work function of 3.8 eV or less). Specific examples of the cathode material include elements belonging to Group 1 or Group 2 of the element periodic rule, that is, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, and alloys containing these (Mg : Ag, Al: Li) and compounds (LiF, CsF, CaF ₂ ), as well as transition metals including rare earth metals. However, since the cathode needs to have translucency, these metals or an alloy containing these metals are formed very thinly, and are formed by lamination with a metal (including an alloy) such as ITO.

  Thereafter, a protective film may be formed to cover the second electrode 35. As the protective film, a silicon nitride film or a DLC film can be used. In this manner, a pixel of the display device can be formed.

(Embodiment 5)
A structure of a pixel and a driver circuit in the display device of the present invention will be described with reference to FIGS.

  FIG. 29 shows a configuration of a display panel according to the present invention. This display panel has a pixel portion 121 in which a plurality of subpixels 130 are arranged on a substrate 120, a scanning line driving circuit 122 that controls a signal of the scanning line 133, and a data line driving circuit 123 that controls a signal of the data line 131. doing. In addition, a monitor circuit 124 for correcting a luminance change of the light emitting element 137 included in the sub-pixel 130 may be provided. The light emitting elements 137 and the light emitting elements included in the monitor circuit 124 have the same structure. The light-emitting element 137 has a structure in which a layer containing a material that exhibits electroluminescence is sandwiched between a pair of electrodes.

  In the periphery of the substrate 120, an input terminal 125 for inputting a signal from an external circuit to the scanning line driving circuit 122, an input terminal 126 for inputting a signal from the external circuit to the data line driving circuit 123, and a signal to the monitor circuit 124. An input terminal 129 is provided.

  The sub-pixel 130 includes a transistor 134 connected to the data line 131 and a transistor 135 inserted and connected in series between the power supply line 132 and the light emitting element 137. The gate of the transistor 134 is connected to the scanning line 133, and the signal of the data line 131 is input to the sub-pixel 130 when selected by the scanning signal. The input signal is supplied to the gate of the transistor 135 and charges the storage capacitor portion 136. In response to this signal, the power supply line 132 and the light emitting element 137 become conductive, and the light emitting element 137 emits light.

  In order to cause the light emitting element 137 provided in the sub-pixel 130 to emit light, it is necessary to supply power from an external circuit. A power supply line 132 provided in the pixel portion 121 is connected to an external circuit at an input terminal 127. Since the power supply line 132 has a resistance loss due to the length of the wiring to be routed, it is preferable to provide a plurality of input terminals 127 at the periphery of the substrate 120. The input terminals 127 are provided at both ends of the substrate 120 and are arranged so that luminance unevenness is not noticeable in the plane of the pixel portion 121. That is, it prevents the one side from being bright and the other side from being dark in the screen. In addition, a light-emitting element 137 having a pair of electrodes, the electrode opposite to the electrode connected to the power supply line 132 is formed as a common electrode shared by the plurality of sub-pixels 130. In order to reduce the loss, a plurality of terminals 128 are provided.

  Next, an example of the sub-pixel 130 will be described in detail with reference to FIGS. 30 and 31. FIG. 30 shows a top view of the sub-pixel 130, and FIG. 31 shows a longitudinal sectional view corresponding to the cutting lines AB, CD, and EF shown in the figure.

  The scanning line 133 and the data line 131 are formed of different layers and intersect with each other with the insulating layers 155 and 156 interposed therebetween. The scan line 133 functions as a gate electrode of the transistor at a portion intersecting the semiconductor layer 141 with the gate insulating layer 157 interposed therebetween. In this case, when the transistor 134 is branched to the semiconductor layer 141 in accordance with the arrangement of the semiconductor layer 141 and the semiconductor layer 141 is provided at a plurality of locations, a plurality of channel formation regions are formed between the pair of the source and the drain. A so-called multi-gate transistor arranged in series can be used.

  Since the power supply line 132 connected to the transistor 135 is desired to have low resistance, it is particularly preferable to use Al, Cu, or the like with low resistivity. When forming Cu wiring, it can form in an insulating layer combining with a barrier layer. FIG. 31 illustrates an example in which the semiconductor layer 141 is formed below the semiconductor layer 141 on the substrate 120. A barrier layer 150 is formed on the surface of the substrate 120 to prevent seepage of impurities such as alkali metal contained in the substrate 120. The power supply line 132 is formed by a barrier layer 152 and a Cu layer 159 in an opening formed in the insulating layer 151. The barrier layer 152 is formed of tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), or the like. The Cu layer 159 is formed by sputtering a seed layer, deposited to a thickness of 1 μm to 5 μm by plating, and planarized by chemical mechanical polishing. That is, a shape embedded in the insulating layer 151 can be obtained by using a damascene process.

  A base insulating layer for the semiconductor layers 140 and 141 is formed on the insulating layer 151. There is no limitation on the structure of the base insulating layer, but the base insulating layer is preferably formed using a silicon nitride layer 153 and a silicon oxide layer 154. In addition, as a structure of the insulating layer, an insulating layer 156 is formed of silicon oxide or silicon nitride in addition to the gate insulating layer 157 above the semiconductor layers 140 and 141, and is used as a protective film.

  The power supply line 132 and the transistor 135 are connected by a wiring 145 by opening a contact hole that penetrates the insulating layer. Further, the gate electrode 142 is connected to the transistor 134 through a wiring 144. The gate electrodes of the transistors 134 and 135 may be formed by stacking a plurality of layers. For example, the combination of the first conductive layer and the second conductive layer may be combined in consideration of the adhesion and resistivity with the gate insulating layer, or by changing the shape of the upper and lower layers (for example, eaves A structure in which source and drain regions and low-concentration impurity (LDD) regions can be formed in a semiconductor layer in a self-aligning manner (as a hat-shaped shape attached) may be employed.

  In addition, the capacitor electrode 143 of the storage capacitor portion 136 provided by extending the gate electrode 142 uses a combination of the first conductive layer and the second conductive layer to form a thin film portion using the first conductive layer. It is preferable to reduce the resistance by adding an impurity of one conductivity type to the underlying semiconductor layer. In other words, the storage capacitor portion 136 includes a capacitor electrode 143 of the storage capacitor portion 136 provided by extending the gate electrode 142, a semiconductor layer 160 to which the semiconductor layer 141 of the transistor 135 is extended, and a gate insulation sandwiched therebetween. Although it is formed by the layer 157, it can function effectively by adding an impurity of one conductivity type to the semiconductor layer 160 to reduce the resistance.

  The pixel electrode of the light-emitting element may be in direct contact with the semiconductor layer 141 of the transistor 135, but can be connected through a wiring 146 as illustrated in FIG. In this case, it is preferable to provide a plurality of steps at the end of the wiring 146 because the contact area with the pixel electrode 147 can be increased. Such a step shape can be formed by using a photomask using a light reducing means such as a slit or a semi-transmissive film. The peripheral edge of the pixel electrode 147 is covered with a partition layer 158.

  In the display panel described in this embodiment mode, the power supply line is formed using a low-resistance material such as Cu. Therefore, the display panel is particularly effective when the screen size is increased. For example, when the screen size is the 13-inch class, the length of the diagonal line is 340 mm, but when the screen size is the 60-inch class, the length is 1500 mm or more. In such a case, since the wiring resistance cannot be ignored, it is preferable to use a wiring made of a low resistance material such as Cu. In consideration of wiring delay, data lines and scanning lines may be formed in the same manner.

  Note that the contents described in this embodiment can be implemented by being freely combined with the contents described in Embodiments 1 to 4.

(Embodiment 6)
In this example, a vapor deposition apparatus used when manufacturing a display panel will be described with reference to the drawings.

  A display panel is manufactured by forming an EL layer on an element substrate on which a pixel circuit and / or a drive circuit are formed using transistors. The EL layer is formed including at least a part of a material that exhibits electroluminescence. The EL layer may be composed of a plurality of layers having different functions. In that case, the EL layer may be configured by combining layers having different functions, which are also called a hole injection transport layer, a light emitting layer, an electron injection transport layer, and the like.

  FIG. 32 shows a configuration of a vapor deposition apparatus for forming an EL layer on an element substrate over which a transistor is formed. In this vapor deposition apparatus, a plurality of processing chambers are connected to transfer chambers 160 and 161. The processing chamber includes a load chamber 162 for supplying a substrate, an unload chamber 163 for recovering the substrate, a heat processing chamber 168, a plasma processing chamber 172, film formation processing chambers 169 to 175 for depositing an EL material, and a light emitting element. One electrode includes a film formation treatment chamber 176 in which aluminum or a conductive film containing aluminum as a main component is formed. In addition, gate valves 177a to 177l are provided between the transfer chamber and each processing chamber, and the pressure in each processing chamber can be controlled independently, thereby preventing cross-contamination between the processing chambers.

  The substrate introduced into the transfer chamber 161 from the load chamber 162 is carried into a predetermined processing chamber by an arm type transfer means 193 provided rotatably. Further, the substrate is transferred from one processing chamber to another processing chamber by the transfer means 193. The transfer chamber 160 and the transfer chamber 161 are connected by a film formation processing chamber 170, and the substrate is transferred by the transfer means 193 and the transfer means 194 here.

  Each processing chamber connected to the transfer chamber 160 and the transfer chamber 161 is maintained in a reduced pressure state. Therefore, in this vapor deposition apparatus, the substrate is continuously subjected to film formation of the EL layer without being exposed to the atmosphere. Since the display panel after the EL layer deposition process may be deteriorated by water vapor or the like, in this vapor deposition apparatus, a sealing process for performing a sealing process before exposure to the atmosphere in order to maintain the quality. A chamber 165 is connected to the transfer chamber 161. Since the sealing process chamber 165 is placed under atmospheric pressure or a reduced pressure close thereto, an intermediate chamber 164 is also provided between the transfer chamber 161 and the sealing process chamber 165. The intermediate chamber 164 is provided for transferring the substrate and buffering the pressure between the chambers.

  The load chamber 162, the unload chamber 163, the transfer chamber, and the film formation processing chamber are provided with exhaust means for keeping the interior of the chamber under reduced pressure. As the exhaust means, various vacuum pumps such as a dry pump, a turbo molecular pump, and a diffusion pump can be used.

  In the vapor deposition apparatus in FIG. 32, the number of processing chambers connected to the transfer chamber 160 and the transfer chamber 161 and the configuration thereof can be appropriately combined depending on the stacked structure of the light-emitting elements. An example of the combination is shown below.

  In the heat treatment chamber 168, degassing treatment is performed by first heating the substrate on which the lower electrode, the insulating partition wall, and the like are formed. The plasma processing chamber 172 performs rare gas or oxygen plasma processing on the surface of the base electrode. This plasma treatment is performed to clean the surface, stabilize the surface state, and stabilize the physical or chemical state (eg, work function) of the surface.

The film formation treatment chamber 169 is a treatment chamber for forming an electrode buffer layer that is in contact with one electrode of the light emitting element. The electrode buffer layer has carrier injection properties (hole injection or electron injection), and is a layer that suppresses the occurrence of short circuits and dark spot defects in the light emitting element. Typically, the electrode buffer layer is an organic-inorganic mixed material, has a resistivity of 5 × 10 ⁴ to 1 × 10 ⁶ Ωcm, and is formed to a thickness of 30 nm to 300 nm. The film formation chamber 171 is a processing chamber for forming a hole transport layer.

  The structure of the light emitting layer in the light emitting element is different depending on whether monochromatic light emission or white light emission is performed. In the vapor deposition apparatus, it is preferable to arrange the film forming treatment chamber accordingly. For example, when three types of light emitting elements having different emission colors are formed on the display panel, it is necessary to form a light emitting layer corresponding to each emission color. In this case, the film formation processing chamber 170 is used for forming the first light emitting layer, the film forming processing chamber 173 is used for forming the second light emitting layer, and the film forming processing chamber 174 is formed of the third light emitting layer. It can be used for membranes. By separating the film formation chamber for each light emitting layer, cross-contamination due to different light emitting materials can be prevented, and the throughput of the film formation process can be improved.

  Alternatively, three types of EL materials having different emission colors may be sequentially deposited in the film formation chamber 170, the film formation chamber 173, and the film formation chamber 174, respectively. In this case, a shadow mask is used, and vapor deposition is performed by shifting the mask in accordance with the region to be vapor deposited.

  In the case of forming a light emitting element that emits white light, light emitting layers having different light emission colors are stacked vertically. Also in that case, the element substrate can be sequentially moved through the film formation chamber to form a film for each light emitting layer. In addition, different light emitting layers can be successively formed in the same film formation chamber.

  In the film formation chamber 176, an electrode is formed over the EL layer. The electrode can be formed by electron beam evaporation or sputtering, but resistance heating evaporation is preferably used.

  The element substrate that has been completed up to the formation of the electrode is carried into the sealing treatment chamber 165 through the intermediate chamber 164. The sealing treatment chamber 165 is filled with an inert gas such as helium, argon, neon, or nitrogen, and a sealing plate is attached to the element substrate on the side where the EL layer is formed and sealed. Stop. In a sealed state, an inert gas may be filled between the element substrate and the sealing plate, or a resin material may be filled. The sealing process chamber 165 includes a dispenser for drawing a sealing material, a mechanical element such as a fixed stage and an arm for fixing a sealing plate facing the element substrate, a dispenser for filling a resin material, or a spin coater. It has been.

  FIG. 33 shows the internal configuration of the film forming chamber. The film formation chamber is kept under reduced pressure. In FIG. 33, the inside between the top plate 191 and the bottom plate 192 is a room, and a room kept under a reduced pressure is shown.

  One or a plurality of evaporation sources are provided in the processing chamber. This is because it is preferable to provide a plurality of evaporation sources when a plurality of layers having different compositions are formed or when different materials are co-evaporated. In FIG. 33, the evaporation sources 181 a, 181 b, and 181 c are attached to the evaporation source holder 180. The evaporation source holder 180 is held by the articulated arm 183. The articulated arm 183 can freely move the position of the evaporation source holder 180 within the movable range by expansion and contraction of the joint. In addition, a distance sensor 182 may be provided in the evaporation source holder 180, and the distance between the evaporation sources 181a to 181c and the substrate 189 may be monitored to control the optimum distance during vapor deposition. In that case, it is good also as an articulated arm which displaces to an articulated arm also in the up-down direction (Z direction).

  The substrate stage 186 and the substrate chuck 187 are paired to fix the substrate 189. The substrate stage 186 may be configured to heat the substrate 189 by incorporating a heater. The substrate 189 is fixed to the substrate stage 186 and carried in / out by the forcible relaxation of the substrate chuck 187. In vapor deposition, a shadow mask 190 having an opening corresponding to the pattern to be vapor deposited can be used as necessary. In that case, the shadow mask 190 is disposed between the substrate 189 and the evaporation sources 181a to 181c. The shadow mask 190 is fixed to the substrate 189 in close contact with the mask chuck 188 or at a fixed interval. When the shadow mask 190 needs to be aligned, the camera is arranged in the processing chamber, and the mask chuck 188 is provided with positioning means that finely moves in the X-Y-θ direction, thereby performing the alignment.

  The evaporation source 181 is provided with a deposition material supply means for continuously supplying the deposition material to the evaporation source. The vapor deposition material supply means includes vapor deposition material supply sources 185a, 185b, and 185c arranged at positions distant from the evaporation source 181 and a material supply pipe 184 connecting the two. Typically, the material supply sources 185 a, 185 b, and 185 c are provided corresponding to the evaporation source 181. In the case of FIG. 33, the material supply source 185a corresponds to the evaporation source 181a. The same applies to the material supply source 185b and the evaporation source 181b, and the material supply source 185c and the evaporation source 181c.

  As an evaporation material supply method, an air current conveyance method, an aerosol method, or the like can be applied. In the air current conveyance method, fine powder of vapor deposition material is carried on an air current and is conveyed to the evaporation source 181 using an inert gas or the like. The aerosol method is vapor deposition performed by conveying a raw material solution in which a vapor deposition material is dissolved or dispersed in a solvent, aerosolizing it with a sprayer, and vaporizing the solvent in the aerosol. In any case, the evaporation source 181 is provided with a heating unit, and the transported vapor deposition material is evaporated to form a film on the substrate 189. In the case of FIG. 33, the material supply pipe 184 can be flexibly bent, and is composed of a thin pipe having rigidity that does not deform even under reduced pressure.

  In the case of applying an air current conveyance method or an aerosol method, the film formation may be performed under a reduced pressure of 133 Pa to 13300 Pa in the film formation treatment chamber at atmospheric pressure or lower. The film formation chamber can be filled with an inert gas such as helium, argon, neon, krypton, xenon, or nitrogen, or the pressure can be adjusted while supplying the gas (while exhausting simultaneously). Further, in the film formation treatment chamber in which an oxide film is formed, a gas such as oxygen or nitrous oxide may be introduced to form an oxidizing atmosphere. Alternatively, a reducing atmosphere may be formed by introducing a gas such as hydrogen into a film formation chamber in which an organic material is deposited.

  As another vapor deposition material supply method, a screw may be provided in the material supply pipe 184 to continuously extrude the vapor deposition material toward the evaporation source.

  According to the vapor deposition apparatus of this embodiment, even a large display panel can be continuously formed with good uniformity. Further, it is not necessary to replenish the vapor deposition material each time the vapor deposition material runs out of the evaporation source, so that the throughput can be improved.

  Note that the contents described in this embodiment mode can be implemented by being freely combined with the contents described in Embodiment Modes 1 to 5.

(Embodiment 7)
In this embodiment, a method for manufacturing a display device to which the present invention can be applied will be described. A display device to which the present invention can be applied may be combined with a high-density plasma method excited by microwaves. An example is shown in FIG. Note that in FIG. 17, FIG. 17B corresponds to a cross-sectional view taken along the line ab in FIG. 17A, and FIG. 17C corresponds to a cross-sectional view taken along the line cd in FIG. To do.

  The display device illustrated in FIG. 17 includes semiconductor films 1703a and 1703b provided over a substrate 1701 with an insulating film 1702 interposed therebetween, and a gate electrode 1705 provided over the semiconductor films 1703a and 1703b with a gate insulating film 1704 interposed therebetween. And insulating films 1706 and 1707 provided so as to cover the gate electrode and conductive films 1708 electrically connected to the source region or the drain region of the semiconductor films 1703a and 1703b and provided over the insulating film 1707. Yes. Note that FIG. 17 shows the case where an n-type thin film transistor 1710a using a part of the semiconductor film 1703a as a channel region and a p-type thin film transistor 1710b using a part of the semiconductor film 1703b as a channel region are shown. However, it is not limited to this configuration. For example, in FIG. 17, an n-type thin film transistor 1710 a is provided with an LDD region, and a p-type thin film transistor 1710 b is not provided with an LDD region, but may be provided in both or may be provided in neither. Is possible.

  As the substrate 1701, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, a metal substrate including stainless steel, or the like can be used. In addition, it is also possible to use a substrate made of a plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES), or a flexible synthetic resin such as acrylic. is there. By using a flexible substrate, a display device that can be bent can be manufactured. In addition, since there is no significant limitation on the area and shape of such a substrate, if the substrate 1701 is, for example, a rectangle having one side of 1 meter or more and a rectangular shape, productivity is remarkably increased. Can be improved. Such an advantage is a great advantage compared to the case of using a circular silicon substrate.

  The insulating film 1702 functions as a base film and is provided to prevent alkali metal such as Na or alkaline earth metal from the substrate 1701 from diffusing into the semiconductor films 1703a and 1703b and adversely affecting the characteristics of the semiconductor element. As the insulating film 1702, an insulating film containing oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like It is possible to provide a single layer structure or a stacked structure of these. For example, in the case where the insulating film 1702 is provided with a two-layer structure, a silicon nitride oxide film may be provided as a first insulating film and a silicon oxynitride film may be provided as a second insulating film. In the case where the insulating film 1702 is provided with a three-layer structure, a silicon oxynitride film is provided as a first insulating film, a silicon nitride oxide film is provided as a second insulating film, and an oxynitriding film is used as a third insulating film. A silicon film is preferably provided.

  The semiconductor films 1703a and 1703b are formed by forming an amorphous semiconductor film using a material containing silicon (Si) as a main component by using an amorphous semiconductor by sputtering, LPCVD, plasma CVD, or the like. The crystalline semiconductor film is crystallized by a crystallization method such as a laser crystallization method, a thermal crystallization method using an RTA or furnace annealing furnace, or a thermal crystallization method using a metal element that promotes crystallization.

  The gate insulating film 1704 is an insulating film containing oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy, x> y), or silicon nitride oxide (SiNxOy) (x> y). A single layer structure or a stacked structure thereof can be used.

  The insulating film 1706 is formed by oxygen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy, x> y), silicon nitride oxide (SiNxOy, x> y) by sputtering, plasma CVD, or the like. Alternatively, a single-layer structure of a nitrogen-containing insulating film or a film containing carbon such as DLC (diamond-like carbon), or a stacked structure thereof can be used.

  The insulating film 1707 includes an insulating film containing oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy, x> y), silicon nitride oxide (SiNxOy, x> y), or DLC ( In addition to a film containing carbon such as diamond-like carbon), a single layer or a laminated structure made of an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane resin can be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, as a substituent, an organic group containing at least hydrogen and a fluoro group may be used. Note that in the display device in FIG. 17, the insulating film 1707 can be provided directly so as to cover the gate electrode 1705 without providing the insulating film 1706.

  As the conductive film 1708, a single layer or a stacked structure including one kind of element selected from Al, Ni, C, W, Mo, Ti, Pt, Cu, Ta, Au, and Mn or an alloy containing a plurality of such elements is used. be able to. For example, as a conductive film made of an alloy containing a plurality of the elements, for example, an Al alloy containing C and Ti, an Al alloy containing Ni, an Al alloy containing C and Ni, an Al alloy containing C and Mn, etc. Can be used. Moreover, when providing with a laminated structure, it can provide by laminating | stacking Al and Ti.

  In FIG. 17, an n-type thin film transistor 1710a has a sidewall in contact with the sidewall of the gate electrode 1705, and a source region and a drain in which an impurity imparting n-type conductivity is selectively added to the semiconductor film 1703a. An LDD region provided below the region and the sidewall is formed. The p-type thin film transistor 1710b has a sidewall in contact with the sidewall of the gate electrode 1705, and a source region and a drain region to which an impurity imparting p-type conductivity is selectively added are formed in the semiconductor film 1703b. ing.

  Note that in the display device of the present invention, at least one of the substrate 1701, the insulating film 1702, the semiconductor films 1703a and 1703b, the gate insulating film 1704, the insulating film 1706, and the insulating film 1707 is oxidized or oxidized using plasma treatment. The semiconductor film or the insulating film is oxidized or nitrided by performing nitriding. In this manner, by oxidizing or nitriding the semiconductor film or the insulating film using plasma treatment, the surface of the semiconductor film or the insulating film is modified, and compared with an insulating film formed by a CVD method or a sputtering method. Since a dense insulating film can be formed, defects such as pinholes can be suppressed and characteristics of the display device can be improved.

The plasma treatment is performed at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less and an electron temperature of plasma of 0.5 ev or more and 1.5 eV or less. Since the electron density of plasma is high and the electron temperature in the vicinity of an object to be processed (here, semiconductor films 1703a and 1703b) formed on the substrate 1701 is low, damage to the object to be processed is prevented. Can do. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or more, an oxide or a nitride film formed by oxidizing or nitriding an irradiation object using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1 eV or less, oxidation or nitridation treatment can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if plasma treatment is performed at a temperature that is 100 degrees or more lower than the strain point temperature of the glass substrate, sufficient oxidation or nitridation treatment can be performed. Note that a high frequency such as a microwave (2.45 GHz) can be used as a frequency for forming plasma.

  Next, the case where an amorphous silicon (a-Si: H) film is used for the semiconductor layer of the transistor will be described. 18 shows a case of a top gate transistor, and FIGS. 19 and 20 show a case of a bottom gate transistor.

FIG. 18A shows a cross section of a top-gate transistor using amorphous silicon as a semiconductor layer. As shown, a base film 1802 is formed on the substrate 1801. Further, a pixel electrode 1803 is formed on the base film 1802. A first electrode 1804 made of the same material is formed in the same layer as the pixel electrode 1803. As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. The base film 1802 can be a single layer of aluminum nitride (AlN), silicon oxide (SiO ₂ ), silicon oxynitride (SiOxNy), or a stacked layer thereof.

  Further, a wiring 1805 and a wiring 1806 are formed over the base film 1802, and an end portion of the pixel electrode 1803 is covered with the wiring 1805. An N-type semiconductor layer 1807 and an N-type semiconductor layer 1808 having N-type conductivity are formed over the wirings 1805 and 1806. A semiconductor layer 1809 is formed between the wiring 1805 and the wiring 1806 and over the base film 1802. A part of the semiconductor layer 1809 extends to the N-type semiconductor layer 1807 and the N-type semiconductor layer 1808. Note that this semiconductor layer is formed of a non-crystalline semiconductor film such as amorphous silicon (a-Si: H) or microcrystalline semiconductor (μc-Si: H). In addition, a gate insulating film 1810 is formed over the semiconductor layer 1809. An insulating film 1811 made of the same material and in the same layer as the gate insulating film 1810 is also formed over the first electrode 1804. Note that as the gate insulating film 1810, a silicon oxide film, a silicon nitride film, or the like is used.

  A gate electrode 1812 is formed over the gate insulating film 1810. A second electrode 1813 made of the same material and in the same layer as the gate electrode is formed over the first electrode 1804 with an insulating film 1811 interposed therebetween. A capacitor element 1819 in which an insulating film 1811 is sandwiched between a first electrode 1804 and a second electrode 1813 is formed. Further, an interlayer insulating film 1814 is formed so as to cover an end portion of the pixel electrode 1803, the driving transistor 1818, and the capacitor 1819.

  A layer 1815 containing an organic compound and a counter electrode 1816 are formed over the interlayer insulating film 1814 and the pixel electrode 1803 located in the opening, and the pixel electrode 1803 and the counter electrode 1816 sandwich the layer 1815 containing an organic compound. Then, a light emitting element 1817 is formed.

  Alternatively, the first electrode 1804 illustrated in FIG. 18A may be formed using the first electrode 1820 as illustrated in FIG. 18B. The first electrode 1820 is formed of the same material as that of the wirings 1805 and 1806. FIG. 19 shows a partial cross section of a panel of a display device using a bottom-gate transistor using amorphous silicon as a semiconductor layer.

  A gate electrode 1903 is formed over the substrate 1901. A first electrode 1904 made of the same material is formed in the same layer as the gate electrode. As a material for the gate electrode 1903, polycrystalline silicon to which phosphorus is added can be used. In addition to polycrystalline silicon, silicide which is a compound of metal and silicon may be used.

  A gate insulating film 1905 is formed so as to cover the gate electrode 1903 and the first electrode 1904. As the gate insulating film 1905, a silicon oxide film, a silicon nitride film, or the like is used. A semiconductor layer 1906 is formed over the gate insulating film 1905. In addition, a semiconductor layer 1907 made of the same material is formed in the same layer as the semiconductor layer 1906.

  N-type semiconductor layers 1908 and 1909 having N-type conductivity are formed over the semiconductor layer 1906, and an N-type semiconductor layer 1910 is formed over the semiconductor layer 1907. Wirings 1911 and 1912 are formed on the N-type semiconductor layers 1908 and 1909, respectively, and a conductive layer 1913 made of the same material as the wirings 1911 and 1912 is formed on the N-type semiconductor layer 1910. A second electrode including the semiconductor layer 1907, the N-type semiconductor layer 1910, and the conductive layer 1913 is formed. Note that a capacitor 1920 having a structure in which the gate insulating film 1902 is sandwiched between the second electrode and the first electrode 1904 is formed.

  One end of the wiring 1911 extends, and a pixel electrode 1914 is formed in contact with the upper portion of the extended wiring 1911. An insulating layer 1915 is formed so as to cover the end portion of the pixel electrode 1914, the driving transistor 1919, and the capacitor 1920.

  A light emitting layer 1916 and a counter electrode 1917 are formed over the pixel electrode 1914 and the insulating layer 1915, and a light emitting element 1918 is formed in a region where the light emitting layer 1916 is sandwiched between the pixel electrode 1914 and the counter electrode 1917.

  The semiconductor layer 1907 and the N-type semiconductor layer 1910 which are part of the second electrode of the capacitor may not be provided. That is, the second electrode may be the conductive layer 1913 and the capacitor may have a structure in which the gate insulating film is sandwiched between the first electrode 1904 and the conductive layer 1913.

  In FIG. 19A, by forming the pixel electrode 1914 before forming the wiring 1911, the gate insulating film 1905 is sandwiched between the second electrode 1921 and the first electrode 1904 each including the pixel electrode 1914 as illustrated in FIG. 19B. A capacitor 1922 having the above structure can be formed. Note that although an inverted staggered channel-etched transistor is shown in FIG. 19, a channel-protective transistor may of course be used. The case of a channel protective transistor will be described with reference to FIGS.

  In the channel protection type transistor shown in FIG. 20A, an insulator 2001 serving as an etching mask is provided over a region where the channel of the semiconductor layer 1906 of the driving transistor 1919 in the channel etch structure shown in FIG. 19A is formed. Are different, and other common parts use common symbols. Similarly, the transistor with the channel protection structure illustrated in FIG. 20B includes an insulator 2001 serving as an etching mask over a region where the channel of the semiconductor layer 1906 of the driving transistor 1919 with the channel etch structure illustrated in FIG. 19B is formed. Different points are provided, and other common parts use common reference numerals.

  When an amorphous semiconductor film is used for a semiconductor layer (a channel formation region, a source region, a drain region, or the like) of a transistor included in a pixel, manufacturing cost can be reduced. Note that the structure of the transistor to which the pixel structure of the present invention can be applied and the structure of the capacitor are not limited to those described above, and transistors having various structures and structures of capacitors can be used. .

  When manufacturing this display device, a photomask (halftone mask) having an inclined transmittance may be used in the photolithography process. A method for manufacturing a display device to which the present invention is applied when a halftone mask is used will be described below.

  The transistor can be a thin film transistor (TFT) in addition to a MOS transistor formed on a single crystal substrate. FIG. 21 is a diagram showing a cross-sectional structure of a transistor constituting a circuit. FIG. 21 shows an n-channel transistor 2101, an n-channel transistor 2102, a capacitor 2104, a resistor 2105, and a p-channel transistor 2103. Each transistor includes a semiconductor layer 2205, a gate insulating layer 2208, and a gate electrode 2209. The gate electrode 2209 is formed with a stacked structure of a first conductive layer 2203 and a second conductive layer 2202. 22A to 22D are top views corresponding to the transistor, the capacitor, and the resistor shown in FIG. 21, and can be referred to.

  In FIG. 21, an n-channel transistor 2101 is also referred to as a low concentration drain (LDD) on both sides of a gate electrode in a channel length direction (carrier flow direction), and forms a source and drain region that forms a contact with a wiring 2204. An impurity region 2207 doped at a lower concentration than the impurity concentration of the impurity region 2206 is formed in the semiconductor layer 2205. In the case where the n-channel transistor 2101 is formed, phosphorus or the like is added to the impurity region 2206 and the impurity region 2207 as an impurity imparting n-type conductivity. LDD is formed as a means for suppressing hot electron degradation and short channel effect.

  As shown in FIG. 22A, in the gate electrode 2209 of the n-channel transistor 2101, the first conductive layer 2203 is formed so as to spread on both sides of the second conductive layer 2202. In this case, the first conductive layer 2203 is formed thinner than the second conductive layer. The first conductive layer 2203 is formed to a thickness that allows the ion species accelerated by an electric field of 10 to 100 kV to pass therethrough. The impurity region 2207 is formed so as to overlap with the first conductive layer 2203 of the gate electrode 2209. That is, an LDD region overlapping with the gate electrode 2209 is formed. In this structure, an impurity region 2207 is formed in a self-aligned manner in the gate electrode 2209 by adding one conductivity type impurity through the first conductive layer 2203 using the second conductive layer 2202 as a mask. That is, the LDD overlapping with the gate electrode is formed in a self-aligning manner.

  In FIG. 21, an n-channel transistor 2102 has an impurity region 2207 doped in a lower concentration than the impurity concentration of the impurity region 2206 in a semiconductor layer 2205 on one side of a gate electrode. As shown in FIG. 22B, in the gate electrode 2209 of the n-channel transistor 2102, the first conductive layer 2203 is formed so as to spread on one side of the second conductive layer 2202. In this case as well, LDD can be formed in a self-aligned manner by adding an impurity of one conductivity type through the first conductive layer 2203 using the second conductive layer 2202 as a mask.

  A transistor having an LDD on one side may be applied to a transistor to which only a positive voltage or only a negative voltage is applied between the source and drain electrodes. Specifically, it may be applied to a transistor constituting a logic gate such as an inverter circuit, a NAND circuit, a NOR circuit, or a latch circuit, or a transistor constituting an analog circuit such as a sense amplifier, a constant voltage generation circuit, or a VCO.

  In FIG. 21, the capacitor 2104 is formed with a gate insulating layer 2208 sandwiched between a first conductive layer 2203 and a semiconductor layer 2205. A semiconductor layer 2205 which forms the capacitor 2104 includes an impurity region 2206 and an impurity region 2207. The impurity region 2207 is formed in the semiconductor layer 2205 so as to overlap with the first conductive layer 2203. The impurity region 2206 forms a contact with the wiring 2204. Since the impurity region 2207 can be doped with one conductivity type impurity through the first conductive layer 2203, the impurity concentration in the impurity region 310 and the impurity region 311 can be the same or can be different. It is. In any case, since the semiconductor layer 2205 functions as an electrode in the capacitor 2104, it is preferable to reduce the resistance by adding an impurity of one conductivity type. In addition, as shown in FIG. 22C, the first conductive layer 2203 can function sufficiently as an electrode by using the second conductive layer 2202 as an auxiliary electrode. As described above, by using a composite electrode structure in which the first conductive layer 2203 and the second conductive layer 2202 are combined, the capacitor 2104 can be formed in a self-aligning manner.

  In FIG. 21, the resistance element 2105 is formed of a first conductive layer 2203. Since the first conductive layer 2203 is formed to a thickness of about 30 nm to 150 nm, a resistance element can be configured by appropriately setting the width and length thereof.

  In FIG. 21, a p-channel transistor 2103 includes an impurity region 2212 in a semiconductor layer 2205. The impurity region 2212 forms source and drain regions that form a contact with the wiring 2204. The structure of the gate electrode 2209 is a structure in which the first conductive layer 2203 and the second conductive layer 2202 overlap each other. The p-channel transistor 2103 is a single drain transistor without an LDD. When the p-channel transistor 2103 is formed, boron or the like is added to the impurity region 2212 as an impurity imparting p-type conductivity. On the other hand, when phosphorus is added to the impurity region 2212, an n-channel transistor having a single drain structure can be obtained.

One or both of the semiconductor layer 2205 and the gate insulating layer 2208 is excited by microwaves, has an electron temperature of 2 eV or less, an ion energy of 5 eV or less, and an electron density of about 10 ¹¹ to 10 ¹³ cm ^−3. Oxidation or nitridation may be performed by the treatment. At this time, the substrate temperature is set to 300 to 450 ° C., and the treatment is performed in an oxidizing atmosphere (O ₂ , N ₂ O, etc.) or a nitriding atmosphere (N ₂ , NH _3, etc.), whereby the interface between the semiconductor layer 2205 and the gate insulating layer 2208 The defect level of can be reduced. By performing this treatment on the gate insulating layer 2208, the insulating layer can be densified. That is, generation of charged defects can be suppressed and fluctuations in the threshold voltage of the transistor can be suppressed. In the case where the transistor is driven with a voltage lower than 3 V, an insulating layer oxidized or nitrided by this plasma treatment can be used as the gate insulating layer 2208. When the driving voltage of the transistor is 3 V or more, the gate is formed by combining an insulating layer formed on the surface of the semiconductor layer 2205 by this plasma treatment and an insulating layer deposited by a CVD method (plasma CVD method or thermal CVD method). An insulating layer 2208 can be formed. Similarly, this insulating layer can also be used as a dielectric layer of the capacitor 2104. In this case, since the insulating layer formed by this plasma treatment is formed with a thickness of 1 nm to 10 nm and is a dense film, a capacitor having a large charge capacity can be formed.

  As described with reference to FIGS. 21 and 22, elements having various structures can be formed by combining conductive layers having different thicknesses. The region where only the first conductive layer is formed and the region where the first conductive layer and the second conductive layer are laminated are a photo provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It can be formed using a mask or a reticle. That is, in the photolithography process, when the photoresist is exposed, the amount of light transmitted through the photomask is adjusted to vary the thickness of the resist mask to be developed. In this case, a resist having a complicated shape may be formed by providing a slit below the resolution limit in a photomask or reticle. Alternatively, the mask pattern formed of the photoresist material may be deformed by baking at about 200 ° C. after development.

  Further, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film, a region where only the first conductive layer is formed, the first conductive layer and the second conductive layer A region where the conductive layer is stacked can be formed continuously. As shown in FIG. 22A, a region where only the first conductive layer is formed can be selectively formed over the semiconductor layer. Such a region is effective on the semiconductor layer, but is not necessary in other regions (a wiring region continuous with the gate electrode). By using this photomask or reticle, it is not necessary to form a region of only the first conductive layer in the wiring portion, so that the wiring density can be substantially increased.

  In the case of FIGS. 21 and 22, the first conductive layer is a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN) or molybdenum (Mo), or a refractory metal. An alloy or compound having a main component of 30 to 50 nm is formed. The second conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. To a thickness of 300 to 600 nm. For example, different conductive materials are used for the first conductive layer and the second conductive layer, and a difference in etching rate is caused in an etching process performed later. As an example, TaN can be used as the first conductive layer, and a tungsten film can be used as the second conductive layer.

  In the present embodiment, a transistor, a capacitor element, and a resistor element having different electrode structures are formed by the same process using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film It shows that you can. Thus, elements having different forms can be formed and integrated without increasing the number of steps in accordance with circuit characteristics.

(Embodiment 8)
In this embodiment mode, pixel configurations applicable to the present invention are exemplified. In addition, the description which overlaps with the structure shown in FIG. 3 is abbreviate | omitted. FIG. 10 illustrates a pixel configuration in which third transistors 25 are provided at both ends of the capacitor 16 in addition to the pixel configuration illustrated in FIG. 3. The third transistor 25 has a function of discharging charges accumulated in the capacitor 16 in a predetermined period. The third transistor 25 is also referred to as an erasing transistor. The predetermined period is controlled by the erasing gate line Ry to which the gate electrode of the third transistor 25 is connected.

  For example, when a plurality of subframe periods are provided, the charge of the capacitor 16 is discharged by the third transistor 25 in a short subframe period. As a result, the duty ratio can be improved.

  FIG. 11A shows a pixel configuration in which a fourth transistor 36 is provided between the driving transistor 12 and the light-emitting element 13 in addition to the pixel configuration shown in FIG. . A second power supply line Vax having a fixed potential is connected to the gate electrode of the fourth transistor 36. Therefore, the current supplied to the light emitting element 13 can be constant regardless of the voltage between the gate and the source of the driving transistor 12 or the fourth transistor 36. The fourth transistor 36 is also referred to as a current control transistor. FIG. 11B shows a pixel structure in which a second power supply line Vax having a fixed potential is provided in parallel with the gate line Gy unlike FIG. 11A. In FIG. 11C, unlike FIGS. 11A and 11B, the gate electrode of the fourth transistor 36, which is at a fixed potential, is connected to the gate electrode of the driving transistor 12. This is a pixel configuration characterized by. In a pixel structure in which a new power supply line is not provided as in FIG. 11C, the aperture ratio can be maintained.

  FIG. 12 shows a pixel configuration characterized in that the erasing transistor 25 shown in FIG. 10 is provided in addition to the pixel configuration shown in FIG. The charge of the capacitor 16 can be discharged by the erasing transistor. Of course, in addition to the pixel structure shown in FIG. 11B or FIG. 11C, an erasing transistor can be provided.

  Here, a pixel circuit in the case where a plurality of subpixels are provided in one pixel will be described. Although not shown, when a plurality of sub-pixels are provided in one pixel and driven independently of each other, as many data lines, scanning lines, and power lines as the number of sub-pixels are prepared, and an element for one pixel is arranged in each. good. However, data lines, scanning lines, and power supply lines that can be shared among sub-pixels may be shared. A circuit example when sharing is shown below.

  FIG. 23A shows a pixel circuit diagram in the case where a power supply line and a scanning line connected to one of a source region and a drain region of a driving transistor are shared by subpixels. FIG. 23B is a pixel circuit diagram in the case where only the scanning lines are shared. The first driving transistor 12, the first light emitting element 13, the second driving transistor 114, and the second light emitting element 14 in the drawing are equivalent to those shown in FIG. In FIG. 23A, in addition to these, the scan line 2301, the first data line 2302, the second data line 2303, the power supply line 2304, the first selection transistor 2305, the second selection transistor 2306, and the first capacitor An element 2307 and a second capacitor 2308 are included. In FIG. 23B, a second power supply line 2309 is added in addition to these.

  The first selection transistor 2305, the first capacitor 2307, the first driving transistor 12, and the first light-emitting element 13 form a first subpixel. Similarly, the second selection transistor 2306, the second capacitor 2308, the second driving transistor 114, and the second light-emitting element 14 form a second subpixel.

  Since the scanning timing may be the same between the sub-pixels, the scanning lines may be shared between the sub-pixels as shown in FIG. 23, and the data lines may be used separately. If the scanning lines are shared, the pixel circuit layout can be afforded and the pixel aperture ratio can be increased. It also leads to improved yield.

  In FIG. 24A, a power line connected to one of the source or drain regions of the driving transistor and a data line connected to one of the source or drain regions of the selection transistor are connected to each other by a data line 2403 in a sub pixel. The pixel circuit diagram in the case of sharing is shown. FIG. 24B shows a pixel circuit diagram in the case where only data lines are shared. Like the scanning lines 2401 and 2402 in FIG. 24, the data lines may be shared by changing the scanning timing between the sub-pixels by making the scanning lines separate. If the data lines are shared, the pixel circuit layout can be afforded and the pixel aperture ratio can be increased. It also leads to improved yield. Further, since the parasitic capacitance of the data line is small, power consumption associated with charging / discharging of the data line is reduced.

  By thus performing area gradation by sharing wiring between sub-pixels, it is possible to increase the number of gradations without lowering the pixel aperture ratio and the yield as compared with those without sub-pixels. Note that when the power supply line is not shared, as described in the first embodiment, the deterioration due to the monitor light emitting element and the temperature correction can be performed for each sub-pixel, or the voltage drops due to the current flowing through the power supply line. The power supply line is not shared because it has special effects such as reducing voltage fluctuations.

  Next, a pixel circuit of a display device capable of full color display using the present invention will be described. Since the deterioration of the light emitting element and the change in characteristics due to temperature in the display device having pixels color-coded by R, G, and B are different for each light emitting color of the light emitting element, as shown in FIG. The configuration of the present invention may be applied to each.

  FIG. 25A illustrates a structure in which the present invention is applied to a display device in which the light-emitting elements of the pixel 2300a illustrated in FIG. 23A are color-coded by R, G, and B colors. At this time, the monitor circuit 64 may be similarly color-coded, and correction of deterioration or characteristic change due to temperature may be performed for each RGB. Here, the structure of the pixel may be the same as that of the pixel 2400a in FIG. 24A instead of FIG.

  FIG. 25B illustrates a structure in which the present invention is applied to a display device in which the light-emitting element of the pixel 2300b illustrated in FIG. 23B is color-coded by R, G, and B. At this time, the monitor circuit 64 may be similarly color-coded, and correction of deterioration or characteristic change due to temperature may be performed for each RGB. Here, the structure of the pixel may be the same as that of the pixel 2400b in FIG. 24B instead of FIG. Further, as a pixel configuration for obtaining a full color, one pixel may be divided into three or more as shown in FIG. At this time, the monitor circuits 64 may be arranged in a divided number, and the deterioration of the light emitting elements or the change in characteristics due to temperature may be corrected.

  FIG. 26A shows a structure when the present invention is applied to a display device in which the light-emitting elements of the pixel shown in FIG. 23A are color-coded by W, R, G, and B. At this time, the monitor circuit 64 may also be color-coded in the same manner, and correction of deterioration or characteristic change due to temperature may be performed for each of W, R, G, and B. Here, the pixel configuration is not limited to FIG. 23A and may be the same as that in FIG.

  FIG. 26B illustrates a structure when the present invention is applied to a display device in which the light-emitting elements of the pixel illustrated in FIG. 23B are color-coded by W, R, G, and B. At this time, the monitor circuit 64 may also be color-coded in the same manner, and correction of deterioration or characteristic change due to temperature may be performed for each of W, R, G, and B. Here, the pixel configuration is not limited to FIG. 23B and may be the same as that in FIG.

  25 and 26 show the case where the number of power supply lines is the same for all the divided pixels, the present invention is not limited to this. For example, in FIG. 26, only W pixels are configured as shown in FIG. 23A, and the remaining three of R, G, and B may be those shown in FIG. In this way, the individual pixel circuits that have been color-coded may have different pixel configurations, and can be freely selected.

(Embodiment 9)
In this embodiment, a pixel structure and a method for writing luminance information to the pixel when the present invention is applied to a display device including a transistor using amorphous silicon will be described.

  In a semiconductor integrated device using amorphous silicon, it is difficult to form a so-called CMOS circuit in which transistors having different conductivity types are integrally formed in the manufacturing process. Even if possible, the manufacturing process is inevitably complicated compared to the case where only a single-conductivity type transistor is formed. Therefore, the simple manufacturing process is the biggest advantage when using amorphous silicon. Low cost is not utilized. Therefore, when designing a semiconductor integrated device using amorphous silicon, it is necessary to consider that a circuit is configured using only a single conductivity type transistor.

  In contrast to transistors using bulk silicon or polysilicon, a transistor using amorphous silicon is markedly deteriorated with time due to continued operation, particularly an increase in threshold value. The increase in the threshold is mainly due to the fact that the positive voltage is continuously applied to the gate electrode of the transistor, thereby increasing the amount of charge trapped in the gate insulating film and increasing the defect density of the channel portion. Responsible. As a method of suppressing the occurrence of these phenomena and suppressing the threshold shift of the transistor, for example, there is a method of providing a period during which a negative voltage is applied to the gate electrode.

  FIG. 27 shows a structure of a display device for suppressing deterioration with time of a transistor when amorphous silicon is used. 27 that have the same reference numerals as those in FIG. 2 have the same or substantially the same functions. Reference numeral 2700 denotes a pixel circuit, 2701 denotes a precharge circuit, and S1 to Sx denote data lines for transmitting a luminance signal to be written to the pixel. The data lines S1 to Sx are connected to the signal line driving circuit 43, the precharge circuit 2701, and a switch. Although there are two switches per data line, both of these switches are not turned on at the same time, and at least one of them is turned on. Further, the description will be made assuming that all the conductivity types of the transistors included in the pixel circuit 2700 are N-channel types.

  The precharge circuit 2701 operates before the signal line driver circuit 43 operates to write a predetermined voltage to the pixel. That is, after the switches on the precharge circuit 2701 side are turned on among the switches arranged on the data lines S1 to Sx, the voltage written to the pixel is once set to the voltage determined by the precharge circuit 2701. The switches arranged on the data lines S1 to Sx are switched, and a predetermined voltage determined by the signal line driver circuit 43 is written to the pixel.

  Here, the precharge voltage determined by the precharge circuit 2701 is preferably the same as or lower than the voltage at which the driving transistors 12 and 114 are turned off, and preferably the same as or higher than the potential of the power supply 18. As a reason for this, as described above, a transistor using amorphous silicon is effective to provide a period for applying a negative voltage to the gate electrode in order to suppress a threshold voltage shift due to deterioration over time. If the voltage written to the pixel in the precharge period is lower than the voltage at which the driving transistors 12 and 114 are turned off, a period in which the gate voltages of all the driving transistors are in the negative direction can be provided. This is because the threshold voltage shift due to deterioration can be reduced. Moreover, even if the precharge voltage is too low, the power consumption is increased and the cost of the power supply circuit is increased. Therefore, the precharge voltage is equal to or higher than the potential of the power supply 18 on the counter electrode side. Is desirable.

  Note that the precharge circuit 2701 is intended to apply a constant voltage to the gate electrodes of all the drive transistors, so there is no need for an electrical element in the circuit, and an external input power source is connected to the data lines S1 to Sx. Wiring may also be used for communication.

  Next, a pixel configuration suitable for applying a negative voltage to the gate of the driving transistor will be described with reference to FIG. FIG. 28 is a circuit diagram of two pixels adjacent to each other in the data line direction. The pixel circuit shown in FIG. 3 has a configuration in which a transistor 2800 for applying a negative direction voltage is added. The gate electrode of the negative voltage application transistor 2800 is connected to the scanning line of the previous pixel, and one of the source or drain electrodes of the negative voltage application transistor 2800 is connected to the scanning line of the pixel. The other of the source and drain electrodes of the transistor 2800 connected for negative voltage application is connected to the gate electrode of the driving transistor 12.

  The pixel shown in FIG. 28 is driven by applying a negative voltage to the gate electrode of the driving transistor 12 only by driving in the same manner as in FIG. 3 without using any special driving method. Can be realized. The transistor 2800 of the pixel is turned on at a timing when the pixel immediately before the pixel is selected. Then, since the scanning line potential of the pixel at that time is low, the potential of the gate electrode of the driving transistor 12 becomes low through the transistor 2800. At this time, a negative voltage is applied to the gate electrode of the driving transistor 12. When the pixel is selected, the gate electrode of the transistor 2800 has a low potential and the source or drain electrode has a higher potential, so that the transistor 2800 is turned off. Therefore, data is written when the pixel is selected, and the transistor 2800 does not hinder the writing operation. In this manner, when the pixel shown in FIG. 28 is used, the reliability of the transistor is greatly increased without being restricted by the writing time and without adding a special peripheral driving circuit for applying a negative charge. be able to.

  Here, in order to surely turn on and off the transistor 2800, the low potential side potential of the scan line is the lowest among the potentials of the electrodes in the pixel, and the high potential side potential of the scan line is taken by the electrode in the pixel. The highest potential is preferable.

  Note that the gist of the pixel circuit shown in FIG. 28 is to apply a sufficiently low potential to the gate electrode of the driving transistor 12 before writing data to the pixel. Therefore, the electrode of the additional transistor is used without departing from the gist. You can connect to anywhere. For example, the connection destination of the gate electrode of the transistor 2800 may be a scanning line immediately before the pixel, or may be a scanning line provided exclusively for the pixel. One of the source and drain electrodes of the transistor 2800 may be connected to, for example, a counter electrode or may be connected to a power supply line. Of course, the original pixel to which the transistor 2800 is added may not be shown in FIG. For example, the pixel shown in FIG. 23 using sub-pixels may be used, or the pixel shown in FIG. 24 may be used. Furthermore, the pixel in FIG. 10 to which an erasing transistor is added may be used, or the pixel in FIGS. 11 and 12 to which a transistor having a fixed gate potential may be added. There is no limitation on the configuration of the addition source pixel as long as the low potential is written to the gate electrode of the driving transistor before data writing.

(Embodiment 10)
In this embodiment, a structure of the entire panel including the pixel circuit described in the above embodiment is described.

  As shown in FIG. 13, the display device of the present invention includes a pixel portion 40 in which a plurality of pixels 10 described above are arranged in a matrix, a first scanning line driving circuit 41, a second scanning line driving circuit 42, and the like. And a signal line driver circuit 43. The first scanning line driving circuit 41 and the second scanning line driving circuit 42 may be disposed so as to face each other with the pixel portion 40 interposed therebetween, or may be disposed in one of the upper, lower, left, and right sides of the pixel portion 40.

  The signal line driver circuit 43 includes a pulse output circuit 44, a latch 45, and a selection circuit 46. The latch 45 has a first latch 47 and a second latch 48. The selection circuit 46 includes a transistor 49 and an analog switch 50 as switching means. The transistor 49 and the analog switch 50 are provided in each column corresponding to the signal line. In addition, in this embodiment, an inverter 51 is provided in each column in order to generate an inverted signal of the WE signal. Note that the inverter 51 may not be provided when an inverted signal of the WE signal is supplied from the outside.

  The gate electrode of the transistor 49 is connected to the selection signal line 52, one electrode is connected to the signal line, and the other electrode is connected to the power supply 53. The analog switch 50 is provided between the second latch 48 and each signal line. That is, the input terminal of the analog switch 50 is connected to the second latch 48, and the output terminal is connected to the signal line. One of the two control terminals of the analog switch 50 is connected to the selection signal line 52, and the other is connected to the selection signal line 52 via the inverter 51. The potential of the power source 53 is a potential for turning off the driving transistor 12 included in the pixel. When the polarity of the driving transistor 12 is an n-channel type, the potential of the power source 53 is set to Low, and the driving transistor 12 is a p-channel type. In this case, the potential of the power supply 53 is set to High.

  The first scanning line driving circuit 41 includes a pulse output circuit 54 and a selection circuit 55. The second scanning line driving circuit 42 includes a pulse output circuit 56 and a selection circuit 57. Start pulses (G1SP, G2SP) are input to the pulse output circuits 54, 56, respectively. In addition, clock pulses (G1CK, G2CK) and inverted clock pulses (G1CKB, G2CKB) are input to the pulse output circuits 54, 56, respectively.

  The selection circuits 55 and 57 are connected to the selection signal line 52. However, the selection circuit 57 included in the second scanning line driving circuit 42 is connected to the selection signal line 52 via the inverter 58. That is, the WE signals input to the selection circuits 55 and 57 via the selection signal line 52 are in an inverted relationship with each other.

  Each of the selection circuits 55 and 57 has a tristate buffer. The tri-state buffer is in an operating state when a signal transmitted from the selection signal line 52 is at an H level, and is in a high impedance state when the signal is at an L level. The pulse output circuit 44 included in the signal line driving circuit 43, the pulse output circuit 54 included in the first scanning line driving circuit 41, and the pulse output circuit 56 included in the second scanning line driving circuit 42 are composed of a plurality of flip-flop circuits. A shift register and a decoder circuit are included. If a decoder circuit is applied as the pulse output circuits 44, 54 and 56, a signal line or a scanning line can be selected at random. If a signal line or a scanning line can be selected at random, it is possible to suppress the generation of a pseudo contour that occurs when the time gray scale method is applied.

  Note that the configuration of the signal line driver circuit 43 is not limited to the above description, and a level shifter or a buffer may be provided. Further, the configurations of the first scanning line driving circuit 41 and the second scanning line driving circuit 42 are not limited to the above description, and a level shifter or a buffer may be provided. In addition, each of the signal line driver circuit 43, the first scan line driver circuit 41, and the second scan line driver circuit 42 may include a protection circuit.

  In the present invention, a protection circuit may be provided. The protection circuit can be formed to have a plurality of resistance elements. For example, p-channel transistors can be used as the plurality of resistance elements. The protection circuit can be provided in each of the signal line driver circuit 43, the first scan line driver circuit 41, and the second scan line driver circuit 42. Preferably, the signal line driver circuit 43 and the first scan line driver are provided. It is preferable to provide between the circuit 41 or the second scan line driver circuit 42 and the pixel portion 40. Such a protection circuit can suppress deterioration and destruction of the element due to static electricity.

  In this embodiment mode, the display device includes a power supply control circuit 63. The power supply control circuit 63 includes a power supply circuit 61 that supplies power to the light emitting element 13 and a controller 62. The power supply circuit 61 includes a first power supply 17, and the first power supply 17 is connected to the pixel electrode of the light emitting element 13 through the driving transistor 12 and the power supply line Vx. In addition, the power supply circuit 61 includes a second power supply 18, and the second power supply 18 is connected to the light emitting element 13 through a power supply line connected to the counter electrode.

  In such a power supply circuit 61, when a forward voltage is applied to the light emitting element 13 and a current is caused to flow through the light emitting element 13, the potential of the first power supply 17 is higher than the potential of the second power supply 18. Set to be higher. On the other hand, when a reverse voltage is applied to the light emitting element 13, the potential of the first power supply 17 is set to be lower than the potential of the second power supply 18. Such setting of the power supply can be performed by supplying a predetermined signal from the controller 62 to the power supply circuit 61.

  In this embodiment mode, the display device includes a monitor circuit 64 and a control circuit 65. The control circuit 65 includes a constant current source 105 and a buffer amplifier circuit 110. The monitor circuit 64 includes a monitor light emitting element 66, a monitor control transistor 111, and an inverter 112.

  The control circuit 65 supplies a signal for correcting the power supply potential to the power supply control circuit 63 based on the output of the monitor circuit 64. The power supply control circuit 63 corrects the power supply potential supplied to the pixel unit 40 based on the signal supplied from the control circuit 65. The display device of the present invention having the above structure can improve the reliability by suppressing the fluctuation of the current value caused by the change of the environmental temperature or the deterioration with time. Further, the monitor control transistor 111 and the inverter 112 can prevent the current from the constant current source 105 from flowing through the shorted monitor light emitting element 66, and supply an accurate current value fluctuation to the light emitting element 13. .

(Embodiment 11)
In this embodiment mode, operation of the display device of the present invention having the above structure is described with reference to drawings.

  First, operation of the signal line driver circuit 43 is described with reference to FIG. The pulse output circuit 44 receives a clock signal (hereinafter referred to as SCK), a clock inversion signal (hereinafter referred to as SCKB), and a start pulse (hereinafter referred to as SSP), and the first latch 47 according to the timing of these signals. Outputs a sampling pulse. The first latch 47 to which data is input holds the video signal from the first column to the last column in accordance with the timing at which the sampling pulse is input. When the latch pulse is input, the second latch 48 transfers the video signals held in the first latch 47 to the second latch 48 all at once.

  Here, the operation of the selection circuit 46 in each period will be described with the period T1 when the WE signal transmitted from the selection signal line 52 is L level and the period T2 when the WE signal is H level. The periods T1 and T2 correspond to half of the horizontal scanning period, and the period T1 is referred to as a first sub-gate selection period, and the period T2 is referred to as a second sub-gate selection period.

  In the period T1 (first sub-gate selection period), the WE signal transmitted from the selection signal line 52 is at the L level, the transistor 49 is turned on, and the analog switch 50 is turned off. Then, the plurality of data lines S1 to Sn are electrically connected to the power source 53 via the transistors 49 arranged in each column. That is, the plurality of signal lines Sx have the same potential as the power supply 53. At this time, the switching transistor 11 included in the selected pixel 10 is turned on, and the potential of the power supply 53 is transmitted to the gate electrode of the driving transistor 12 through the switching transistor 11. Then, the driving transistor 12 is turned off, and no current flows between both electrodes of the light-emitting element 13 so that no light is emitted. In this manner, regardless of the state of the video signal input to the signal line Sx, the potential of the power supply 53 is transmitted to the gate electrode of the driving transistor 12, and the switching transistor 11 is turned off, so that the light emitting element 13 is turned on. The operation for forcibly causing no light emission is the erasing operation. At this time, if the potential of the power supply 53 is sufficiently increased in the direction in which the driving transistor of the pixel is turned off, a reverse bias is applied to the gate electrode of the driving transistor as compared with data writing, so that the reliability of the transistor is increased. ,preferable.

  In the period T2 (second sub-gate selection period), the WE signal transmitted from the selection signal line 52 is at the H level, the transistor 49 is turned off, and the analog switch 50 is turned on. As a result, the video signal held in the second latch 48 is simultaneously transmitted to each signal line Sx for one row. At this time, the switching transistor 11 included in the pixel 10 is turned on, and the video signal is transmitted to the gate electrode of the driving transistor 12 through the switching transistor 11. Then, according to the input video signal, the driving transistor 12 is turned on or off, and the first and second electrodes of the light-emitting element 13 have different potentials or the same potential. More specifically, when the driving transistor 12 is turned on, the first and second electrodes of the light emitting element 13 have different potentials, and a current flows through the light emitting element 13. Then, the light emitting element 13 is turned on. Note that the current flowing through the light emitting element 13 is the same as the current flowing between the source and drain of the driving transistor 12.

  On the other hand, when the driving transistor 12 is turned off, the first and second electrodes of the light emitting element 13 have the same potential, and no current flows through the light emitting element 13. That is, the light emitting element 13 does not emit light. In this manner, the writing transistor is an operation in which the driving transistor 12 is turned on or off in accordance with the video signal, and the potentials of the first and second electrodes of the light-emitting element 13 are different or the same. .

  Next, operations of the first scanning line driving circuit 41 and the second scanning line driving circuit 42 will be described. G1CK, G1CKB, and G1SP are input to the pulse output circuit 54, and pulses are sequentially output to the selection circuit 55 in accordance with the timing of these signals. G2CK, G2CKB, and G2SP are input to the pulse output circuit 56, and pulses are sequentially output to the selection circuit 57 in accordance with the timing of these signals. FIG. 15B shows each column of the i-th row, the j-th row, the k-th row, and the p-th row (i, j, k, p are natural numbers, 1 ≦ i, j, k, p ≦ n). The potential of the pulse supplied to the selection circuits 55 and 57 is shown.

  Here, similarly to the description of the operation of the signal line driver circuit 43, each period is defined as a period T1 when the WE signal transmitted from the selection signal line 52 is at L level and a period T2 when the WE signal is at H level. The operation of the selection circuit 55 included in the first scanning line driving circuit 41 and the selection circuit 57 included in the second scanning line driving circuit 42 will be described. Note that in the timing chart of FIG. 15B, the potential of the gate line Gy (y is a natural number, 1 ≦ y ≦ n) to which a signal is transmitted from the first scan line driver circuit 41 is expressed as VGy (41). The potential of the gate line to which the signal is transmitted from the second scanning line driving circuit 42 is denoted as VGy (42). VGy (41) and VGy (42) can be supplied by the same gate line Gy.

  In the period T1 (first sub-gate selection period), the WE signal transmitted from the selection signal line 52 is at the L level. Then, the L level WE signal is input to the selection circuit 55 included in the first scanning line driving circuit 41, and the selection circuit 55 becomes indefinite. On the other hand, an H level signal obtained by inverting the WE signal is input to the selection circuit 57 included in the second scanning line driving circuit 42, and the selection circuit 57 enters an operating state. That is, the selection circuit 57 transmits an H level signal (row selection signal) to the i-th gate line Gi, and the gate line Gi has the same potential as the H-level signal. That is, the second scanning line driving circuit 42 selects the i-th gate line Gi. As a result, the switching transistor 11 included in the pixel 10 is turned on. Then, the potential of the power supply 53 included in the signal line driver circuit 43 is transmitted to the gate electrode of the driving transistor 12, the driving transistor 12 is turned off, and the potentials of both electrodes of the light emitting element 13 are the same potential. That is, during this period, an erasing operation in which the light emitting element 13 does not emit light is performed.

  In the period T2 (second sub-gate selection period), the WE signal transmitted from the selection signal line 52 is at the H level. Then, an H-level WE signal is input to the selection circuit 55 included in the first scanning line driving circuit 41, and the selection circuit 55 enters an operating state. That is, the selection circuit 55 transmits the H level signal to the gate line Gi of the i-th row, and the gate line Gi has the same potential as the H level signal. That is, the first scanning line driving circuit 41 selects the i-th gate line Gi. As a result, the switching transistor 11 included in the pixel 10 is turned on. Then, a video signal is transmitted from the second latch 48 included in the signal line driver circuit 43 to the gate electrode of the driving transistor 12, and the driving transistor 12 is turned on or off, and the two electrodes included in the light emitting element 13 are connected. The potentials are different from each other or the same potential. That is, in this period, the writing operation in which the light emitting element 13 emits light or does not emit light is performed. On the other hand, an L level signal is input to the selection circuit 57 included in the second scanning line driving circuit 42, and an indefinite state is set.

  As described above, the gate line Gy is selected by the second scanning line driving circuit 42 in the period T1 (first sub-gate selection period), and the first scanning line driving circuit in the period T2 (second sub-gate selection period). 41 is selected. That is, the gate lines are complementarily controlled by the first scanning line driving circuit 41 and the second scanning line driving circuit 42. In the first and second sub-gate selection periods, the erase operation is performed on one side and the write operation is performed on the other side.

  Note that in a period in which the first scanning line driving circuit 41 selects the i-th gate line Gi, the second scanning line driving circuit 42 is not operating (the selection circuit 57 is in an indefinite state), or the i-th row. A row selection signal is transmitted to the gate lines of other rows except for. Similarly, during a period in which the second scanning line driving circuit 42 transmits a row selection signal to the i-th gate line Gi, the first scanning line driving circuit 41 is in an indefinite state or other rows except the i-th row. A row selection signal is transmitted to the gate line.

  In addition, since the light emitting element 13 can be forcibly turned off according to the present invention that performs the above operation, the duty ratio is improved. Further, although the light emitting element 13 can be forcibly turned off, it is not necessary to provide a TFT for discharging the charge of the capacitor 16, and thus a high aperture ratio is realized. When a high aperture ratio is realized, the luminance of the light-emitting element can be lowered with an increase in the area that emits light. That is, since the driving voltage can be lowered, power consumption can be reduced.

  Note that the present invention is not limited to the above-described form in which the gate selection period is divided into two. The gate selection period may be divided into three or more.

(Embodiment 12)
The present invention can also be applied to a display device that performs constant current driving. In this embodiment, the degree of change with time is detected using the monitor light emitting element 66, and the change with time of the light emitting element is corrected by correcting the video signal or the power supply potential based on the detection result. A case of compensation will be described.

  In this embodiment, first and second light emitting elements for monitoring are provided. A constant current is supplied from the first constant current source to the first monitoring light emitting element, and a constant current is supplied from the second constant current source to the second monitoring light emitting element. By changing the current value supplied from the first constant current source and the current value supplied from the second constant current source, the total amount of current flowing through the first and second monitor light emitting elements is different. Then, a difference in change with time occurs between the first and second monitor light emitting elements.

  The first and second monitoring light emitting elements are connected to an arithmetic circuit, and the arithmetic circuit calculates a difference in potential between the first monitoring light emitting element and the second monitoring light emitting element. The voltage value calculated by the arithmetic circuit is supplied to the video signal generation circuit. In the video signal generation circuit, the video signal supplied to each pixel is corrected based on the voltage value supplied from the arithmetic circuit. With the above structure, a change with time of the light-emitting element can be compensated. Note that a circuit such as a buffer amplifier circuit that prevents fluctuations in potential may be provided between each monitor light emitting element and the arithmetic circuit. In this embodiment, examples of a pixel having a configuration for performing constant current driving include a pixel using a current mirror circuit.

(Embodiment 13)
The present invention can be applied to a passive matrix display device. A passive matrix display device includes a pixel portion formed over a substrate, a column signal line driver circuit, a row signal line driver circuit, and a controller that control the driver circuit arranged around the pixel portion. The pixel portion includes column signal lines arranged in the column direction, row signal lines arranged in the row direction, and a plurality of light emitting elements arranged in a matrix. A monitor circuit 64 can be provided on the substrate on which the pixel portion is formed.

  In the display device of this embodiment, the monitor circuit 64 is used to correct the image data input to the column signal line driver circuit or the voltage generated from the constant voltage source according to the temperature change and the change over time. Therefore, it is possible to provide a display device in which the influence caused by both the temperature change and the change with time is reduced.

(Embodiment 14)
As electronic devices including a pixel portion including a light-emitting element, a television device (also simply referred to as a television or a television receiver), a digital camera, a digital video camera, a mobile phone device (also simply referred to as a mobile phone or a mobile phone), Examples thereof include portable information terminals such as PDAs, portable game machines, computer monitors, computers, sound reproduction apparatuses such as car audio, and image reproduction apparatuses equipped with recording media such as home game machines. A specific example will be described with reference to FIG.

  A portable information terminal device illustrated in FIG. 16A includes a main body 9201, a display portion 9202, and the like. The display device of the present invention can be applied to the display portion 9202. That is, a portable information terminal device in which the influence of fluctuations in the current value of a light emitting element due to changes in environmental temperature and changes over time is suppressed by the present invention in which the power supply potential applied to the light emitting element is corrected using a light emitting element for monitoring. Can be provided.

  A digital video camera shown in FIG. 16B includes a display portion 9701, a display portion 9702, and the like. The display device of the present invention can be applied to the display portion 9701. Provided is a digital video camera that suppresses the influence of fluctuations in the current value of a light-emitting element due to changes in environmental temperature and changes over time by the present invention that corrects the power supply potential applied to the light-emitting element using a light-emitting element for monitoring. Can do.

  A cellular phone shown in FIG. 16C includes a main body 9101, a display portion 9102, and the like. The display device of the present invention can be applied to the display portion 9102. According to the present invention in which a power supply potential applied to a light emitting element is corrected using a light emitting element for monitoring, a mobile phone in which an influence due to a change in current value of the light emitting element due to a change in environmental temperature and a change over time is suppressed can be provided. it can.

  A portable television device illustrated in FIG. 16D includes a main body 9301, a display portion 9302, and the like. The display device of the present invention can be applied to the display portion 9302. According to the present invention for correcting a power supply potential applied to a light emitting element by using a light emitting element for monitoring, a portable television device that suppresses the influence of a change in the current value of the light emitting element due to a change in environmental temperature and a change over time is provided. Can be provided. In addition, the present invention can be applied to a wide variety of television devices, from a small one mounted on a portable terminal such as a cellular phone to a medium-sized one that can be carried and a large one (for example, 40 inches or more). The display device can be applied.

  A portable computer illustrated in FIG. 16E includes a main body 9401, a display portion 9402, and the like. The display device of the present invention can be applied to the display portion 9402. According to the present invention for correcting a power supply potential applied to a light emitting element using a light emitting element for monitoring, a portable computer is provided in which the influence of fluctuations in the current value of the light emitting element due to changes in environmental temperature and changes over time is suppressed. be able to.

  A television device illustrated in FIG. 16F includes a main body 9501, a display portion 9502, and the like. The display device of the present invention can be applied to the display portion 9502. Provided is a television set in which the influence of fluctuations in the current value of a light emitting element due to changes in environmental temperature and changes over time is suppressed by the present invention in which a power supply potential applied to the light emitting element is corrected using a light emitting element for monitoring. Can do.

It is the figure which showed the display apparatus of this invention. It is the figure which showed the display apparatus of this invention. It is the figure which showed the equivalent circuit of the pixel of this invention. It is the figure which showed the layout of the pixel of this invention. It is the figure which showed the cross section of the pixel of this invention. It is the figure which showed the monitor circuit of this invention. It is the figure which showed the monitor circuit of this invention. It is the figure which showed the monitor circuit of this invention. It is the figure which showed the timing chart of this invention. It is the figure which showed the equivalent circuit of the pixel of this invention. It is the figure which showed the equivalent circuit of the pixel of this invention. It is the figure which showed the equivalent circuit of the pixel of this invention. It is the figure which showed the panel of this invention. It is the figure which showed the timing chart of this invention. It is the figure which showed the timing chart of this invention. It is the figure which showed the electronic device of this invention. It is a figure which showed an example of the display apparatus which can apply this invention. It is a figure which showed an example of the display apparatus which can apply this invention. It is a figure which showed an example of the display apparatus which can apply this invention. It is a figure which showed an example of the display apparatus which can apply this invention. It is a figure which showed an example of the display apparatus which can apply this invention. It is a figure which showed an example of the display apparatus which can apply this invention. It is the figure which showed the equivalent circuit of the pixel of this invention. It is the figure which showed the equivalent circuit of the pixel of this invention. It is the figure which showed the display apparatus of this invention. It is the figure which showed the display apparatus of this invention. It is the figure which showed the display apparatus of this invention. It is a figure explaining the pixel structure suitable for applying a negative direction voltage to the gate of a drive transistor. It is a figure explaining the structure of the display panel of this invention. It is a figure explaining the structure of the sub pixel of the display panel of this invention. It is a figure explaining the structure of the sub pixel of the display panel of this invention. It is a figure which shows the structure of the vapor deposition apparatus for forming EL layer. It is a figure which shows the structure of the vapor deposition apparatus for forming EL layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Pixel 11 Switching transistor 12 Drive transistor 13 Light emitting element 14 Light emitting element 16 Capacitance element 17 Power supply 18 Power supply 19 1st electrode 20 Insulating substrate 22a Conductive film 22b Conductive film 24 Drain wiring 25 Transistor 28 Insulating film 29 Insulating film 30 Interlayer Insulating film 31 Insulating film 32 Power supply line 33 Light emitting layer 35 Second electrode 36 Transistor 40 Pixel unit 41 Scan line driving circuit 42 Scan line driving circuit 43 Signal line driving circuit 44 Pulse output circuit 45 Latch 46 Selection circuit 47 Latch 48 Latch 49 Transistor 50 Analog switch 51 Inverter 52 Selection signal line 53 Power supply 54 Pulse output circuit 55 Selection circuit 56 Pulse output circuit 57 Selection circuit 58 Inverter 61 Power supply circuit 62 Controller 63 Power supply control circuit 64 Monitor circuit 65 Control circuit 6 6 Monitor Light-Emitting Element 66a Anode Electrode 66c Cathode Electrode 71 Film Formation Chamber 80 Transistor 81 Transistor 82 Transistor 83 Transistor 84 Transistor 85 Transistor 86 Transistor 105 Constant Current Source 107 Insulating Film 110 Buffer Amplifier Circuit 111 Monitor Control Transistor 112 Inverter 112n Transistor 112p Transistor 113 Power supply line 114 Drive transistor 115 Monitor control transistor 116 Inverter 116p Transistor 166a Anode electrode 166c Cathode electrode 117 Power supply line 120 Substrate 121 Pixel portion 122 Scan line drive circuit 123 Data line drive circuit 124 Monitor circuit 125 Input terminal 126 Input terminal 127 Input terminal 128 Terminal 129 Input terminal 130 Sub-pixel 131 Data line 132 Power supply line 133 Scan line 134 Transistor 135 Transistor 136 Holding capacitor portion 137 Light emitting element 140 Semiconductor layer 141 Semiconductor layer 142 Gate electrode 143 Capacitance electrode 144 Wiring 145 Wiring 146 Wiring 147 Pixel electrode 150 Barrier layer 151 Insulating layer 152 Barrier layer 153 Silicon nitride layer 154 Silicon oxide layer 155 Gate insulating layer 156 Insulating layer 157 Insulating layer 158 Partition layer 159 Cu layer 160 Semiconductor layer 161a Transfer chamber 161b Transfer chamber 162 Load chamber 163 Unload chamber 164 Intermediate chamber 165 Sealing chamber 166 Monitor Light-emitting element 168 Heat treatment chamber 169 Film formation chamber 170 Film formation chamber 172 Plasma treatment chamber 173 Film formation chamber 174 Film formation chamber 176 Film formation chamber 180 Evaporation source holder 181 Evaporation source 181a Evaporation source 181b Evaporation source 181c Evaporation source 182 Distance sensor 183 Articulated arm 184 Material supply pipe 185a Material supply source 185b Material supply source 185c Material supply source 186 Substrate stage 187 Substrate chuck 188 Mask chuck 189 Substrate 190 Shadow mask 191 Top plate 192 Bottom plate 193 Conveying means 194 Transport means 207 Semiconductor layer 310 Impurity region 311 Impurity region 430 region 1005 Each arithmetic circuit 1701 Substrate 1702 Insulating film 1703a Semiconductor film 1703b Semiconductor film 1704 Gate insulating film 1705 Gate electrode 1706 Insulating film 1707 Insulating film 1708 Conductive film 1710a Thin film transistor 1710b Thin film transistor 1801 Substrate 1802 Base film 1803 Pixel electrode 1804 First electrode 1805 Wiring 1806 Wiring 1807 N-type semiconductor layer 1808 N-type semiconductor layer 1809 Semiconductor layer 1810 Gate insulating film 1811 Insulating film 1812 Gate electrode 1813 Second electrode 1814 Interlayer insulating film 1815 Layer 1816 Counter electrode 1817 Light emitting element 1818 Drive transistor 1819 Capacitor element 1820 First electrode 1901 Substrate 1902 Gate insulating Film 1903 Gate electrode 1904 First electrode 1905 Gate insulating film 1906 Semiconductor layer 1907 Semiconductor layer 1908 N type semiconductor layer 1910 N type semiconductor layer 1911 Wiring 1913 Conductive layer 1914 Pixel electrode 1915 Insulating layer 1916 Light emitting layer 1917 Counter electrode 1918 Light emitting element 1919 Drive transistor 1920 Capacitor element 1921 Second electrode 1922 Capacitor element 2001 Insulator 2101 n-channel transistor 2102 n-channel transistor 2103 p Channel transistor 2104 Capacitance element 2105 Resistance element 2202 Conductive layer 2203 Conductive layer 2204 Wiring 2205 Semiconductor layer 2206 Impurity region 2207 Impurity region 2208 Gate insulating layer 2209 Gate electrode 2212 Impurity region 2300a Pixel 2300b Pixel 2301 Scan line 2302 Data line 2303 Data line 2304 Power supply line 2305 Selection transistor 2306 Selection transistor 2307 Capacitance element 2308 Capacitance element 2309 Power supply line 2400a Pixel 2400b Pixel 2700 Pixel circuit 2701 Precharge circuit 2702 Base film 2800 Transistor 9101 Main body 9102 Display portion 9201 Main body 9202 Display portion 9301 Main body 9302 Display portion 9401 Main body 9402 Display unit 9501 Main body 9502 Display unit 9701 Display unit 9702 Display Part Vx Power line Vax Power line Gy Gate line Ry Gate line S1 Data line

Claims (6)

The first transistor, the second transistor, the third transistor, the fourth transistor, the monitor light emitting element , the light emitting element , the first circuit, the second circuit, and the first wiring A display device having a second wiring and a third wiring,
A gate of the first transistor is electrically connected to one of a source or a drain of the second transistor and one of a source or a drain of the third transistor;
One of a source and a drain of the first transistor is electrically connected to an input terminal of the first circuit and the second circuit;
The other of the source and the drain of the first transistor is electrically connected to the anode electrode of the monitoring light emitting element , the gate of the second transistor, and the gate of the third transistor,
The cathode electrode of the monitoring light emitting element is a cathode electrode electrically connected to the light emitting element,
The other of the source and the drain of the second transistor is electrically connected to the first wiring;
The other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fourth transistor;
A gate of the fourth transistor is electrically connected to the second wiring;
The other of the source and the drain of the fourth transistor is electrically connected to the third wiring;
An output terminal of the first circuit is electrically connected to an anode electrode of the light emitting element ;
The first circuit is a circuit having a function as a buffer amplifier ,
The display device, wherein the second circuit is a circuit having a function of supplying a constant current. The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the light emitting element for monitoring, the light emitting element , the first circuit, and the second circuit And a display device having a first wiring, a second wiring, a third wiring, and a fourth wiring,
The gate of the first transistor is electrically connected to one of a source or a drain of the second transistor, one of a source or a drain of the third transistor, and one of a source or a drain of the fourth transistor. And
One of a source and a drain of the first transistor is electrically connected to an input terminal of the first circuit and the second circuit;
The other of the source and the drain of the first transistor is electrically connected to the anode electrode of the monitoring light emitting element , the gate of the second transistor, and the gate of the third transistor,
The cathode electrode of the monitoring light emitting element is a cathode electrode electrically connected to the light emitting element,
The other of the source and the drain of the second transistor is electrically connected to the first wiring;
The other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fifth transistor;
A gate of the fourth transistor is electrically connected to the second wiring and the gate of the fifth transistor;
The other of the source and the drain of the fourth transistor is electrically connected to the third wiring;
The other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring;
An output terminal of the first circuit is electrically connected to an anode electrode of the light emitting element ;
The first circuit is a circuit having a function as a buffer amplifier ,
The display device, wherein the second circuit is a circuit having a function of supplying a constant current. In claim 1,
The first wiring has a function of transmitting a first potential,
The second wiring has a function of transmitting a second potential or a third potential,
The third wiring has a function of transmitting a fourth potential,
The second potential is a potential that can turn on the fourth transistor;
The third potential is a potential that can turn off the fourth transistor;
The display device, wherein the fourth potential is lower than the first potential. In claim 2,
The first wiring has a function of transmitting a first potential,
The second wiring has a function of transmitting a second potential or a third potential,
The third wiring has a function of transmitting a fourth potential,
The fourth wiring has a function of transmitting a fifth potential,
The second potential is a potential that can turn on the fourth transistor and turn off the fifth transistor;
The third potential is a potential that can turn off the fourth transistor and turn on the fifth transistor;
The display device, wherein the fifth potential is higher than the first potential and the fourth potential. In any one of Claims 1 thru | or 4,
The display device, wherein the first transistor is turned off when the monitoring light emitting element is short-circuited. An electronic apparatus, comprising a display device according to any one of claims 1 to 5.

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