JP5222867B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, with the aim of realizing a ubiquitous information-oriented society, various demands such as downsizing, high functionality, multi-function, or personalization have been increasing for various information communication devices and information terminals such as mobile phones. It's getting on. In parallel with this, demands on information communication devices and information terminals, such as higher information processing speed, diversification of information that can be handled and larger capacity, and lower power consumption, are increasing. Yes.

  In response to such demands, miniaturization of semiconductor elements and high integration of integrated circuits are the main guidance for so-called scaling in semiconductor manufacturing technology that uses silicon (Si) as the core material, called Si-LSI technology. It is realized as a principle. However, there is a limit to scaling, and a new teaching principle beyond scaling is required.

  For example, new materials having higher carrier mobility than Si, such as Ge, SiGe, strained Si, strained SiGe, and strained Ge, are attracting attention. Using these new materials, the operating speed of LSi is improved, or a Ge layer as a buffer layer is formed on the Si substrate, and a GaAs layer having an optical function is grown on the Si substrate through this Ge layer. Research has also been conducted (see, for example, Non-Patent Documents 1 to 4).

Furthermore, as a technique for growing a material having a lattice constant between Si and Ge on the Si substrate, Si _1-x Ge _x having the same lattice constant as the material to be grown as in Patent Document 1 is formed on the Si substrate. There is a method in which a desired material is epitaxially grown on the Si _1-x Ge _x after being formed. However, in order to form materials having different lattice constants, it is necessary to form Si _1-x Ge _x having different Ge concentrations. However, until now, there is no technique for forming Si _1-x Ge _x having different Ge concentrations in the same plane, and in order to form materials having different lattice constants, Ge concentrations that match the respective lattice constants The only way was to form Si _1-x Ge _x with

  A plurality of types of elements having different functions such as an electronic functional element typified by a field effect transistor, an optical functional element typified by a light emitting element or a light receiving element, or a spin functional element typified by a spin transistor, Research has also been conducted on a technique in which substrates are provided individually on a plurality of types of substrates made of materials that match the lattice constants of the respective forming materials, and then the substrates provided with these elements are bonded together. According to this technique, it is possible to realize a semiconductor device or an integrated circuit in which a plurality of types of elements having different functions and lattice constants of forming materials are substantially mixed on a single substrate. However, in this technology, devices having different functions such as an electronic functional element, an optical functional element, and a spin functional element must be formed on different planes (layers). Alternatively, it is practically impossible to achieve high integration.

  Therefore, in order to improve the performance of the semiconductor integrated circuit innovatively and enable high integration, a plurality of types of semiconductor elements having different functions and lattice constants of forming materials are used on the same substrate, particularly on the same substrate. Development of a technique that can be mixedly mounted on a plane (layer) is desired.

JP 2009-224727 A

“Si heterostructure and its device application”: Masanobu Miyao, Kiyokazu Nakagawa, Applied Physics Vol. 61, No. 11, p. 1104, 1992 "Si-based high mobility MOS transistor technology": Shinichi Takagi, Applied Physics Vol. 74, No. 9, p. 1158-1170, 2005 “Gallium Aresenide Layers Grown by Molecular Beam Epitaxy on Single Crystalline Germanium Island on Insulator”: M. Takai, T. Tanigawa, T. Minamisono, K. Gamo, and S. Namba, Jpn. J. Appl. Phys. 23, L308 , (1984) “Low-dislocation-density GaAs epilayers grown on Ge-coated Si substrates by means of lateral epitaxial overgrowth”: Appl. Phys. Lett. 41, 347, (1982)

  An object of the present invention is to provide a method of manufacturing a semiconductor device in which a plurality of types of semiconductor elements and spin functional elements having different lattice constants can be mixedly mounted on the same layer on the same substrate.

Producing how the semiconductor device according to the embodiment, a step of forming an insulating film on a silicon substrate, an opening is formed in the insulating film, thereby exposing a portion of the silicon substrate, a silicon substrate having the exposed And a step of forming an amorphous first semiconductor layer containing Ge on the insulating film, and a step of processing the first semiconductor layer into a structure extending in a first direction parallel to a substrate plane of the silicon substrate. The first semiconductor layer extended in the first direction is subjected to heat treatment, and the first Si _1-x Ge _x (0 ≦ x ≦ 1) in which the Si concentration decreases as the distance from the opening is increased. forming a layer, the including.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device which can mount multiple types of semiconductor elements and spin functional elements from which a lattice constant differs on the same layer on the same board | substrate can be provided.

1 is a diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. It is the figure which showed the relationship between the mixed crystal ratio of a SiGe layer, and a lattice constant. FIG. 3A is a top view showing a method of forming the SiGe layer on the insulating film, and FIG. 3B is a cross-sectional view taken along the second direction of FIG. FIG. 4A is a top view showing a method of forming the SiGe layer on the insulating film, and FIG. 4B is a cross-sectional view taken along the second direction of FIG. FIG. 5A is a top view showing a method of forming the SiGe layer on the insulating film, and FIG. 5B is a cross-sectional view taken along the second direction of FIG. FIG. 6A is a top view showing a method of forming a SiGe layer on an insulating film, and FIG. 6B is a cross-sectional view taken along the second direction of FIG. FIG. 7A is a top view showing a method of forming a SiGe layer on an insulating film, and FIG. 7B is a cross-sectional view taken along the second direction of FIG. It is the figure which showed the relationship between the heat processing conditions of recrystallization of a SiGe layer, and the density | concentration of Si in a SiGe layer. FIG. 9A is a top view showing a method of forming the SiGe layer on the insulating film, and FIG. 9B is a cross-sectional view taken along the second direction of FIG. 9A. FIG. 10A is a top view showing a method of forming a SiGe layer on an insulating film, and FIG. 10B is a cross-sectional view taken along the second direction of FIG. FIG. 11A is a top view showing a method of forming a SiGe layer on an insulating film, and FIG. 11B is a cross-sectional view taken along the second direction of FIG. 11 (c) is a cross-sectional view taken along the first direction of FIG. 11 (a). FIG. 12A is a top view showing a method of forming the SiGe layer on the insulating film, and FIG. 12B is a cross-sectional view taken along the second direction of FIG. FIGS. 13A, 13B, and 13C are cross-sectional views along the first direction of FIG. 8A, showing a method of forming a SiGe layer on an insulating film. FIG. 14A is a top view showing a method of forming a SiGe layer on an insulating film, and FIG. 14B is a cross-sectional view taken along the second direction of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  First, the configuration of the semiconductor device according to the embodiment of the present invention will be described.

(First embodiment)
FIG. 1 shows a schematic configuration of a semiconductor device according to the first embodiment of the present invention. FIG. 1 shows a case where an electronic functional element, an optical functional element, and a spin functional element are formed monolithically on one layer on one silicon substrate.

The electronic functional element is, for example, a transistor using Ge or SiGe, the optical functional element is, for example, a light emitting element or a light receiving element using GaAs or FeSi ₂ , and the spin functional element is, for example, a spin using Fe ₃ Si. It is a transistor. However, each functional element is not limited to these.

In FIG. 1, a first region A of a silicon substrate 10 is a well-known formation region of a CMOS transistor 11, and a memory cell, a logical operation circuit, a liquid crystal display unit, and the like are formed by the CMOS transistor 11 and the like. . The second region B of the silicon substrate 10 is a region where a plurality of functional elements are formed. In the second region B, an insulating film 13 is formed on the silicon substrate 10 by, for example, a silicon oxide film. A universal buffer layer 14 (hereinafter referred to as a buffer layer) is formed on the insulating film 13. The buffer layer 14 is composed of, for example, SiGe layers 14a, 14b, and 14c having different lattice constants. That is, the lattice constants of these SiGe layers 14a, 14b and 14c are, for example, the SiGe layer or Ge layer 15 constituting the electronic functional element formed thereon, and the GaAs layer or FeSi ₂ layer 16 constituting the optical functional element. And the lattice constant of, for example, the Fe ₃ Si layer 17 constituting the spin function element, is set equal to each other. The SiGe layers 14a, 14b, and 14c, the SiGe layer or Ge layer 15, the GaAs layer or FeSi ₂ layer 16, and the Fe ₃ Si layer 17 are separated by an insulating film (not shown).

FIG. 2 shows the relationship between the mixed crystal ratio of the SiGe layer and the lattice constant. As shown in FIG. 2, the lattice constants of a material group having new functions such as light and spin are, for example, GaAs: 0.565 nm, FeSi ₂ : 0.554 nm, and Fe ₃ Si: 0.564 nm. The constant is greatly different from 0.543 nm. For this reason, when these materials are mixedly mounted on a silicon substrate, a template for crystal growth is required. The Si _1-x Ge _x (0 ≦ x ≦ 1) mixed crystal is a solid solution semiconductor, and the lattice constant ranges from 0.543 nm to 0.565 nm by changing the mixed crystal ratio (x). Can be changed freely. Since the lattice constant of the material group having the new function is within the range of the lattice constant of Si _1-x Ge _x , as shown in FIG. 1, Si _1-x Ge _x layers 14a, 14b having different mixed crystal ratios are used. , 14c and is crystal-grown on the insulating film 13, the _{Si 1-x} Ge _x layers 14a, 14b, the material group of 14c as a buffer layer _(template), the _{Si 1-x} Ge _x layer 14a, 14b, on 14c By crystal growth, a high-quality film with few lattice defects with controlled strain can be formed. Using the SiGe layer or Ge layer 15, the GaAs layer or FeSi ₂ layer 16, and the Fe ₃ Si layer 17 thus formed, a desired element having an electronic function, an optical function, and a spin function is formed.

  The formation of SiGe having a different Ge concentration on the insulating film 13 will be described in a method of manufacturing a SiGe layer, which will be described later. For example, an epitaxial growth method by melting and solidifying Ge or SiGe is conceivable.

According to the embodiment, on the insulating film 13 formed on the silicon substrate 10, _{Si 1-x} Ge x layer 14a as a buffer layer mixed crystal ratios are different, 14b, and 14c provided, the _{Si 1- x} Ge _x layer 14a, 14b, the SiGe or Ge layer 15, GaAs layer or FeSi ₂ layer 16, _Fe 3 Si layer 17 is provided with 14c as a template. Therefore, a plurality of semiconductor layers having a lattice constant different from that of the silicon substrate 10 can be provided on one substrate. Therefore, a highly functional semiconductor device can be formed while suppressing an increase in chip area.

Next, a method for manufacturing a Si _1-x Ge _x layer as a buffer layer applied to the above embodiment will be described.

(First manufacturing method of SiGe layer)
3 to 14 show a method of forming a SiGe layer on an insulating film. 3A to FIG. 7A, FIG. 9A to FIG. 12A, and FIG. 14A are top views, and FIG. 3B to FIG. 7B and FIG. b) to FIG. 12 (b) and FIG. 14 (b) are cross sections along the second direction of FIG. 3 (a) to FIG. 7 (a) and FIG. 9 (a) to FIG. 12 and FIG. FIG. 11C is a cross-sectional view taken along the first direction of FIG. FIG. 8 is a diagram showing the relationship between the heat treatment conditions when forming the SiGe layer 19 and the concentration of Si in the SiGe layer 19. FIGS. 13A, 13B, and 13C are cross-sectional views along the first direction of FIG.

  First, as shown in FIG. 3, a silicon oxide film having a thickness of about 30 nm to be the insulating film 13 is formed on the silicon substrate 10 by using, for example, a thermal CVD method or the like.

  Next, as shown in FIG. 4, for example, a groove (opening) is formed in a part of the insulating film 13 to expose a part of the silicon substrate 10. The opening may be a hole. Further, when the opening is a groove, the opening extends along the first direction. If the opening is a hole, a plurality of holes are formed along the first direction. Alternatively, depending on the pattern to be formed in a later process, it is not necessarily on the same straight line. Further, a plurality of openings may be arranged at a desired interval in the second direction.

Next, as shown in FIG. 5, a semiconductor layer 18 made of amorphous Ge having a thickness of about 100 nm is formed on the insulating film 13 and the silicon substrate 10. The semiconductor layer 18 is in contact with the silicon substrate 10 through the groove. A portion where the semiconductor layer 18 and the silicon substrate 10 are in contact is referred to as a seed portion. The semiconductor layer 18 is Si _1-y Ge _y (0 <y ≦ 1), and the mixed crystal ratio of the semiconductor layer 18 is determined so as to become a SiGe layer having a desired mixed crystal ratio after a process described later. The

  Next, as shown in FIG. 6, a resist pattern (not shown) is formed on the semiconductor layer 18 and anisotropic etching or the like is used to leave the semiconductor layer 18 on the insulating film while leaving the semiconductor layer 18 immediately above the seed portion. Is processed into a thin line shape. More specifically, the fine line shape extends from the region (seed portion) where the silicon substrate 10 and the semiconductor layer 18 are in contact with each other in the lateral direction (second direction), for example, by about 400 μm. A plurality of structures) are formed in parallel. The width of the line structure is about 30 nm to 3.0 μm.

As shown in FIG. 7, a cap layer 30 is formed on the semiconductor layer 18 and the insulating film 13. By this cap layer 30, when the Si _1-y Ge _y layer 18 is melted, the shape can be maintained before and after melting, and a process with good controllability can be realized.

Next, as shown in FIG. 8, heat treatment is performed on the processed semiconductor layer 18. This heat treatment is RTA (Rapid Thermal Anneal) having a temperature of, for example, 940 ° C. or higher. The temperature of RTA varies depending on the mixed crystal ratio of Si _1-y Ge _{y in} the semiconductor layer 18 and is equal to or higher than the temperature at which the semiconductor layer 18 melts. For example, when the semiconductor layer 18 is Ge, since the melting point is 940 ° C., the temperature of the semiconductor layer 18 needs to exceed 940 ° C., or the semiconductor layer 18 is made of Ge of Si _0.2 Ge _0.8 In this case, since the melting point is about 1035 ° C., the temperature of the semiconductor layer 18 needs to exceed 1035 ° C.

In RTA, when the temperature of the semiconductor layer 18 reaches or exceeds the melting point determined by the Ge concentration of Si _1-y Ge _y , the semiconductor layer 18 starts to melt. During the melting, in a region where the semiconductor layer 18 and the silicon substrate 10 are in contact with each other, interdiffusion of Si atoms and Ge atoms occurs between the Si _1-y Ge _y region and the Si substrate region. That is, in the semiconductor layer 18, Si atoms diffuse from the silicon substrate 10 and Ge diffuses to the silicon substrate 10 side. As a result, the amount of Si that enters the semiconductor layer 18 from the silicon substrate 10 decreases as the distance from the seed portion increases. For this reason, the Si concentration distribution in the semiconductor layer 18 decreases monotonously in the second direction. In addition, by using a thin line shape, a substantially equivalent distribution can be obtained with a plurality of thin lines.

Since the melting point of the semiconductor layer 18 increases as the Si concentration increases, crystallization starts from the substrate Si side having a high Si concentration during melting by RTA or at the time of cooling, and the crystallization gradually proceeds in the film thickness direction. Thereafter, crystallization proceeds in the lateral direction. The lateral crystallization distance is defined by the RTA processing temperature and time. The diagram shown in the lower part of FIG. 8 is an example showing that the concentration distribution of Si changes depending on the temperature of RTA. It can be seen that the higher the RTA temperature is, the more Si is diffused from the seed to the farther distance. When the RTA is completed, the crystallized semiconductor layer 18 becomes a Si _1-x Ge _x (0 ≦ x ≦ 1) layer 19. As a result, the Si _1-y Ge _y layer 18 becomes a SiGe layer 19 having a Si and Ge concentration distribution in which the Si concentration decreases as the distance from the seed portion increases. For this reason, the mixed crystal ratio of the SiGe layer 19 varies depending on the distance from the seed portion. Here, when the width of the thin line is 100 nm, if the width is 3 μm or less, it has good crystallinity and can form a distribution of Si concentration with good reproducibility. When the thickness is 200 nm, the width may be 6 μm or less. This is because if the width becomes too wide with respect to the thickness, a large change in film thickness occurs during melting, the cap layer 30 is greatly deformed, and the initial shape cannot be retained after melting and solidifying.

  Note that the heat treatment is not limited to RTA, and a method of heating by irradiating a laser beam to a region where the SiGe layer is formed and scanning may be used.

Next, as shown in FIG. 9, the cap layer 30 is removed, and the SiGe layer 19 is divided into two or more regions depending on the mixed crystal ratio of Si and Ge. The SiGe layer 19 is divided into, for example, Si _1-x Ge _x layers 19a, 19b, and 19c that serve as buffer layers. For _{example, Si 1-x} Ge x layer 19a is approximately x = 0.45, Ge concentration of about 45% lattice constant 0.552nm~0.553nm about close to the lattice constant of the FeSi ₂ layer 16, _{Si 1- The x} Ge _x layer 19b is approximately x = 0.90, the Ge concentration is about 90%, and the lattice constant is about 0.562 nm to 0.564 nm close to Fe ₃ Si, and the Si _1-x Ge _x layer 19c is x = 1. In the region where the Ge concentration remains 100%, the lattice constant is about 0.565 nm, which is close to the lattice constant of GaAs.

Thereafter, the heat treatment is performed again at a temperature that does not melt any of 19a to 19c. Thereby, in each of the compartments 19a, 19b, and 19c, mutual diffusion of Si and Ge occurs, and the Si / Ge concentration that differs depending on the distance from the seed becomes uniform before the heat treatment. . As a result, the density of dislocations existing inside can be reduced by changing the concentration continuously. As a result, when, for example, an FeSi ₂ layer, an Fe ₃ Si layer, or a GaAs layer is grown on each of the regions 19a to 19c, a film having good crystallinity can be obtained.

  According to the above-described SiGe layer manufacturing method, the Ge-containing semiconductor layer 18 is brought into contact with the silicon substrate 10 and stretched in a thin line shape in the lateral direction, and then an epitaxial growth method by melting and solidifying is performed. Thereby, Si in the silicon substrate 10 enters the semiconductor layer 18 with high accuracy. Specifically, the concentration distribution of Si in the semiconductor layer 18 monotonously decreases from the seed portion toward the other end. And by using the thin line shape mentioned above, it is possible to obtain a substantially equivalent distribution with a plurality of thin lines. Therefore, a desired SiGe layer with a changed lattice constant can be formed. As a result, a plurality of semiconductor layers having a lattice constant different from that of the silicon substrate 10 can be provided on the same layer on one substrate. Therefore, it is effective for manufacturing various devices.

  Further, according to the SiGe layer manufacturing method described above, the Ge-containing semiconductor layer 18 is 100% Ge. However, for example, if only a layer having a Ge concentration of 85% or less is required, the Ge concentration of the semiconductor layer 18 By setting the ratio to 85%, it is possible to form a region having a Si concentration in the range of 100% to 15%.

(Second manufacturing method of SiGe layer)
Next, a method for increasing the area of the SiGe layer 19 using the fine wire structure described with reference to FIG. 6 will be described. In addition, the manufacturing method to FIGS. 3-6 is the same as the manufacturing method mentioned above.

  After the process of FIG. 6 described above, an amorphous SiGe (semiconductor) layer 20 is deposited on the entire surface as shown in FIG. Here, it is desirable that the Ge concentration in the SiGe layer 20 is located between the highest and lowest concentrations in each SiGe region formed separately. For example, the Ge concentration is 45% or more and 100% or less.

Next, as shown in FIG. 11, RTA is performed to perform solid phase epitaxial growth of the SiGe layer 19. The RTA conditions at this time are the same as the conditions described in FIG. In this RTA, when the temperature of the semiconductor layer 18 reaches or exceeds the melting point determined by the Ge concentration of Si _1-y Ge _y , the semiconductor layer 18 and the semiconductor layer 20 start to melt. During the melting, in a region where the semiconductor layer 18 and the silicon substrate 10 are in contact with each other, interdiffusion of Si atoms and Ge atoms occurs between the Si _1-y Ge _y region and the Si substrate region. That is, in the semiconductor layer 18, Si atoms diffuse from the silicon substrate 10 and Ge diffuses to the silicon substrate 10 side. Further, even in a region where the semiconductor layer 18 and the semiconductor layer 20 are in contact with each other, mutual diffusion of Si atoms and Ge atoms occurs. For this reason, the Si _1-y Ge _y layer 18 becomes a SiGe layer 19 having a Si and Ge concentration distribution in which the Si concentration decreases as the distance from the seed portion increases, and the semiconductor layer 20 similarly forms Si as the distance from the seed portion increases. The Si _1-x Ge _x (0 ≦ x ≦ 1) layer 21 having a concentration distribution of Si and Ge that decreases in concentration is obtained.

Next, as shown in FIG. 12, the stacked film of the SiGe layers 19 and 21 is divided into two or more regions depending on the mixed crystal ratio of Si and Ge. For example, it is divided into Si _1-x Ge _x layers 21a, 21b, 21c. Note that the lattice constants of the Si _1-x Ge _x layers 21a, 21b, and 21c are substantially the same as the lattice constants of the Si _1-x Ge _x layers 19a, 19b, and 19c described above.

Thereafter, the heat treatment is performed again at a temperature in a range where none of the Si _1-x Ge _x layers 19a to 19c is melted. Thereby, in each of the partitioned Si _1-x Ge _x layers 19a, 19b, and 19c, interdiffusion of Si and Ge occurs between the inside and the upper SiGe layer 21. Depending on the distance and the Si / Ge concentration that was different between the Si _1-x Ge _x layer 19 and the Si _1-x Ge _x layer 21 becomes uniform. As a result, the density of dislocations existing inside due to the continuous change of the concentration, or the dislocations existing between the Si _1-x Ge _x layer 19 and the Si _1-x Ge _x layer 21 Both density and reduction can be realized. As a result, when, for example, a FeSi ₂ layer, a Fe ₃ Si layer, or a GaAs layer is grown on each region of the Si _1-x Ge _x layers 21a to 21c, the films have good crystallinity. Can be obtained.

  Thereby, the SiGe layer is also formed on the SiGe layer 19 and between the line structures of the SiGe layers 19 adjacent in the first direction, and the SiGe layer 21 having a larger area than the SiGe layer 19 is formed. The Si and Ge concentration distribution along the second direction of the SiGe layer 21 is substantially the same as the Si and Ge concentration distribution along the second direction of the SiGe layer 19. The SiGe layer 21 is planarized using, for example, etch back or CMP.

According to the manufacturing method of the SiGe layer described above, the upper SiGe layer 20 is grown as a SiGe layer 19 seed by solid phase epitaxial growth, and Si and Ge are further interdiffused, so that the SiGe layer 19 extends along the second direction. A SiGe layer 21 having a concentration distribution similar to the Si and Ge concentration distribution and having a larger area than the SiGe layer 19 is formed. Therefore, the lattice constants of the Si _1-x Ge _x layers 21a, 21b, and 21c are the same as the lattice constants of the Si _1-x Ge _x layers 19a, 19b, and 19c described above, and the Si _1-x Ge _x layer 21a. , 21b, 21c are larger than the Si _1-x Ge _x layers 19a, 19b, 19c.

(Third manufacturing method of SiGe layer)
Next, a method for increasing the area of the SiGe layer 19 using the fine wire structure described above will be described. In addition, the manufacturing method of FIGS. 3-8 is the same as the manufacturing method mentioned above. However, the thickness, width, and interval of the thin lines are, for example, 200 nm, 100 nm, and 50 nm, respectively.

As shown in FIG. 13, after the process of FIG. 8 described above, the cap film is removed, and an atmosphere having a reducing property, for example, an atmosphere in which Si _1-x Ge _x easily flows, such as in a hydrogen atmosphere. Then, heat treatment is performed at a temperature below the melting point. When this heat treatment is performed, the thin line that is long in the thickness direction as shown in FIG. 13 (a) reduces the film thickness and widens as shown in FIG. 13 (b), as shown in FIG. 13 (c). In this way, they are combined with adjacent thin wires and integrated. Thereby, the area of the SiGe layer 19 can be increased. As shown in FIG. 14, the method of dividing the SiGe layer 19 into a plurality of regions is the same as the above-described process.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed constituent elements. For example, even if several constituent requirements are deleted from the disclosed constituent requirements, the invention can be extracted as long as a predetermined effect can be obtained.

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 11 ... CMOS transistor 13 ... Insulating film 14 ... Universal buffer layer 14a, 14b, 14c ... SiGe layer 18 ... Semiconductor layer 19 ... SiGe layer 19a, 19b, 19c ... SiGe layer 20 ... Semiconductor layer 21 ... SiGe layer 21a , 21b, 21c ... SiGe layer 30 ... cap layer

Claims (10)

Forming an insulating film on the silicon substrate;
Providing an opening in the insulating film to expose a portion of the silicon substrate;
Forming an amorphous first semiconductor layer containing Ge on the exposed silicon substrate and the insulating film;
Processing the first semiconductor layer into a structure extending in a first direction parallel to a substrate plane of the silicon substrate ;
The first semiconductor layer extended in the first direction is subjected to a heat treatment, and a first Si _1-x Ge _x (0 ≦ x ≦ 1) layer in which the concentration of Si decreases as the distance from the opening is increased. Forming, and
A method for manufacturing a semiconductor device, comprising: After processing the first semiconductor layer into a structure extending in the first direction, an amorphous second semiconductor layer containing Ge is formed on the first semiconductor layer and between the adjacent first semiconductor layers. Further comprising a step,
By forming a heat treatment on the second semiconductor layer when forming the first Si _1-x Ge _x (0 ≦ x ≦ 1) layer, the concentration of Si decreases as the distance from the opening portion increases. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising forming two Si _1-x Ge _x (0 ≦ x ≦ 1) layers. The first Si _1-x Ge _x (0 ≦ x ≦ 1) layer is subjected to a heat treatment to cause the first Si _1-x Ge _x (0 ≦ x ≦ 1) layer to flow, and the adjacent first 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of bonding Si _1-x Ge _x (0 ≦ x ≦ 1) layers. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of separating the first Si _1-x Ge _x (0 ≦ x ≦ 1) layer into two or more regions. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of separating the first and second Si _1-x Ge _x (0 ≦ x ≦ 1) layers into two or more regions. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of separating the combined first Si _1-x Ge _x (0 ≦ x ≦ 1) layer into two or more regions.   The method for manufacturing a semiconductor device according to claim 4, wherein the separation is performed according to a mixed crystal ratio of Si and Ge of the semiconductor layer or the other semiconductor layer.   7. The method of manufacturing a semiconductor device according to claim 4, wherein a material layer having a lattice constant that matches a lattice constant of each region is formed on the separated region.   The method for manufacturing a semiconductor device according to claim 8, wherein the material layer is a material including at least one of an optical function and a spin function. The method for manufacturing a semiconductor device according to claim 9, wherein the material layer includes at least one of strained silicon, SiGe, GaAs, FeSi _2, and Fe ₃ Si.

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