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JP5223398B2 - Resistor circuit and resistance value adjusting method for the resistor circuit - Google Patents
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JP5223398B2 - Resistor circuit and resistance value adjusting method for the resistor circuit - Google Patents

Resistor circuit and resistance value adjusting method for the resistor circuit Download PDF

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JP5223398B2
JP5223398B2 JP2008070283A JP2008070283A JP5223398B2 JP 5223398 B2 JP5223398 B2 JP 5223398B2 JP 2008070283 A JP2008070283 A JP 2008070283A JP 2008070283 A JP2008070283 A JP 2008070283A JP 5223398 B2 JP5223398 B2 JP 5223398B2
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英記 加藤
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この発明は、並列接続された抵抗の一方の抵抗をレーザー又は電気的ストレスにより切断することによりその直列抵抗値を変化させることができる抵抗回路の抵抗値調整方法に関するものである。この方法により抵抗値を調整した抵抗回路は定電圧発生回路や電圧検出回路に用いられ、これら回路は、例えばアナログ電子回路を備えた半導体集積回路に搭載される。   The present invention relates to a resistance value adjusting method for a resistance circuit that can change the series resistance value by cutting one of the resistors connected in parallel by laser or electrical stress. Resistance circuits whose resistance values are adjusted by this method are used in constant voltage generation circuits and voltage detection circuits, and these circuits are mounted on, for example, semiconductor integrated circuits including analog electronic circuits.

図7は、電圧検出回路の一例を示す回路図である。15は演算増幅器で、その反転入力端子に基準電圧発生回路13が接続され、基準電圧Vrefが印加される。入力端子(Vin)23から入力される測定するべき端子の電圧が分圧抵抗11(RtとRT)と12(Rb)によって分圧されて演算増幅器15の非反転入力端子に入力される。演算増幅器15の出力は出力端子19を介して外部に出力される。この電圧検出回路20において、測定するべき端子の電圧が高く、分圧抵抗11と12により分圧された電圧が基準電圧Vrefよりも高いときは演算増幅器15の出力が「H」を維持し、測定するべき端子の電圧が降下してきて分圧抵抗11と12により分圧された電圧が基準電圧Vref以下になってくると演算増幅器15の出力が「L」になる。   FIG. 7 is a circuit diagram illustrating an example of a voltage detection circuit. Reference numeral 15 denotes an operational amplifier. A reference voltage generating circuit 13 is connected to an inverting input terminal of the operational amplifier 15 and a reference voltage Vref is applied. The voltage of the terminal to be measured input from the input terminal (Vin) 23 is divided by the voltage dividing resistors 11 (Rt and RT) and 12 (Rb) and input to the non-inverting input terminal of the operational amplifier 15. The output of the operational amplifier 15 is output to the outside through the output terminal 19. In this voltage detection circuit 20, when the voltage of the terminal to be measured is high and the voltage divided by the voltage dividing resistors 11 and 12 is higher than the reference voltage Vref, the output of the operational amplifier 15 maintains “H”, When the voltage at the terminal to be measured drops and the voltage divided by the voltage dividing resistors 11 and 12 becomes lower than the reference voltage Vref, the output of the operational amplifier 15 becomes “L”.

図8は、定電圧発生回路の一例を示す回路図である。直流電源5からの電源を負荷7に安定して供給すべく、定電圧発生回路9が設けられている。定電圧発生回路は、直流電源5が接続される入力端子11、基準電圧発生回路(Vref)13、演算増幅器15、出力ドライバを構成するPチャネル型MOSトランジスタ(以下、PMOSと略記する。)17、分圧抵抗R1、R2及び出力端子(Vout)19を備えている。定電圧発生回路9の演算増幅器15では、出力端子がPMOS17のゲート電極に接続され、反転入力端子に基準電圧発生回路13から基準電圧Vrefが印加され、非反転入力端子に出力電圧Voutを抵抗R1とR2で分圧した電圧が印加され、抵抗R11、R12の分圧電圧が基準電圧Vrefに等しくなるように制御される。   FIG. 8 is a circuit diagram showing an example of a constant voltage generation circuit. A constant voltage generating circuit 9 is provided in order to stably supply power from the DC power supply 5 to the load 7. The constant voltage generating circuit includes an input terminal 11 to which the DC power supply 5 is connected, a reference voltage generating circuit (Vref) 13, an operational amplifier 15, and a P-channel MOS transistor (hereinafter abbreviated as PMOS) 17 constituting an output driver. , Voltage dividing resistors R1 and R2 and an output terminal (Vout) 19 are provided. In the operational amplifier 15 of the constant voltage generating circuit 9, the output terminal is connected to the gate electrode of the PMOS 17, the reference voltage Vref is applied from the reference voltage generating circuit 13 to the inverting input terminal, and the output voltage Vout is applied to the non-inverting input terminal by the resistor R1. And the voltage divided by R2 are applied, and the divided voltage of the resistors R11 and R12 is controlled to be equal to the reference voltage Vref.

一般に、図7に示した電圧検出回路や図8に示した定電圧発生回路では、製造プロセスのばらつきに起因して基準電圧発生回路からの基準電圧Vrefが変動するので、その変動に対応すべく、分圧抵抗に抵抗値が調整可能な抵抗RTを設け、分圧抵抗の抵抗値を調整している。この種の分圧抵抗としては、ヒューズの切断により抵抗値を調整可能な抵抗回路を用いて、分圧抵抗の抵抗値を調整している。   In general, in the voltage detection circuit shown in FIG. 7 and the constant voltage generation circuit shown in FIG. 8, the reference voltage Vref from the reference voltage generation circuit fluctuates due to variations in the manufacturing process. A resistor RT whose resistance value can be adjusted is provided in the voltage dividing resistor to adjust the resistance value of the voltage dividing resistor. As this type of voltage dividing resistor, the resistance value of the voltage dividing resistor is adjusted by using a resistance circuit capable of adjusting the resistance value by cutting a fuse.

図9は、分圧抵抗を構成する従来の抵抗回路を示す回路図である。抵抗素子Rb、n+1個(nは正の整数)の設定抵抗体RT1、RT2…、RTn、抵抗体Rtが直列に接続されている。設定抵抗素子RT1、…、RTnには、各設定抵抗体に対応してヒューズf1、…、fnが並列に接続されている。このような抵抗回路は、特許文献1等に開示されている。   FIG. 9 is a circuit diagram showing a conventional resistor circuit constituting a voltage dividing resistor. Resistance elements Rb, n + 1 (n is a positive integer) setting resistors RT1, RT2,..., RTn, and a resistor Rt are connected in series. .., RTn are connected in parallel with fuses f1,..., Fn corresponding to the respective setting resistors. Such a resistance circuit is disclosed in Patent Document 1 and the like.

このような抵抗回路では、任意のヒューズf1、…、fnをレーザー光線で切断することにより、所望の直列抵抗値を得ることができる。この場合、ヒューズf1、…、fnの抵抗値を設定抵抗素子RT1、…、RTnの抵抗値よりも無視できる程度に小さくすることによって、ヒューズ切断後に抵抗値誤差の少ない抵抗値を得ることができる。   In such a resistance circuit, a desired series resistance value can be obtained by cutting arbitrary fuses f1,..., Fn with a laser beam. In this case, by making the resistance values of the fuses f1,..., Fn smaller than the resistance values of the set resistance elements RT1,. .

図9の抵抗回路を図8の定電圧発生回路の分圧抵抗R11、R12に適用する場合、例えば抵抗素子Rb端を接地し、抵抗素子Rt端をPMOS17のドレインに接続し、抵抗素子Rb、RT1間の端子ノードLを演算増幅器15の非反転入力端子に接続する。   When the resistance circuit of FIG. 9 is applied to the voltage dividing resistors R11 and R12 of the constant voltage generation circuit of FIG. 8, for example, the resistance element Rb end is grounded, the resistance element Rt end is connected to the drain of the PMOS 17, and the resistance elements Rb, A terminal node L between RT1 is connected to the non-inverting input terminal of the operational amplifier 15.

また、図9の抵抗回路を図7の電圧検出回路の分圧抵抗R11、R12に適用する場合、例えば、抵抗素子Rb端を接地し、抵抗素子Rt端を入力端子23に接続し、端子ノードLを演算増幅器15の非反転入力端子に接続する。これらの場合、分圧抵抗R11はRbにより構成され、分圧抵抗R12はRt、設定抵抗体RT1、…、RTn及びヒューズf1、…、fnにより構成される。
特開2003−37179号公報
Further, when the resistor circuit of FIG. 9 is applied to the voltage dividing resistors R11 and R12 of the voltage detection circuit of FIG. 7, for example, the resistor element Rb end is grounded, the resistor element Rt end is connected to the input terminal 23, and the terminal node L is connected to the non-inverting input terminal of the operational amplifier 15. In these cases, the voltage dividing resistor R11 is constituted by Rb, and the voltage dividing resistor R12 is constituted by Rt, setting resistors RT1,..., RTn and fuses f1,.
JP 2003-37179 A

上記した図9に示す抵抗回路においては、抵抗値を調整するために所定のヒューズを切断している。しかしながら、半導体の製造工程においては、製造のばらつきが発生する。ビットに対応してヒューズを切断して抵抗値を調整していく場合、トータルの誤差がヒューズ切断による補正量を超えてしまうことがある。例えば、図6に示すように、製造誤差が10%ある場合において、ビット1の補正量ΔVが8、ビット2の補正量ΔV4が4、ビット3の補正量ΔVが2、ビット1の補正量ΔVが1とする。それぞれの誤差は、0.8、0.4、0.2、0.1となる。ビット3までヒューズを切断した時に、トータルの誤差が1.4となり、次のビット1における補正量を超えてしまい補正が行えないという問題があった。   In the resistor circuit shown in FIG. 9, a predetermined fuse is cut in order to adjust the resistance value. However, manufacturing variations occur in the semiconductor manufacturing process. When the resistance value is adjusted by cutting the fuse corresponding to the bit, the total error may exceed the correction amount by cutting the fuse. For example, as shown in FIG. 6, when the manufacturing error is 10%, the correction amount ΔV of bit 1 is 8, the correction amount ΔV4 of bit 2 is 4, the correction amount ΔV of bit 3 is 2, and the correction amount of bit 1 Let ΔV be 1. The respective errors are 0.8, 0.4, 0.2, and 0.1. When the fuse is cut up to bit 3, the total error becomes 1.4, and the correction amount in the next bit 1 is exceeded, and there is a problem that correction cannot be performed.

この発明の目的は、上述した従来の問題点を解決するためになされたものにして、製造のばらつきによる誤差を考慮し、その誤差を含め、抵抗値の調整を行い精度の良い抵抗値が得られる抵抗回路の調整方法を提供することにある。   The object of the present invention is to solve the above-mentioned conventional problems, and takes into account errors due to manufacturing variations, and by adjusting the resistance values including those errors, a highly accurate resistance value is obtained. It is an object to provide a method for adjusting a resistance circuit.

この発明の抵抗回路、複数の抵抗体が直列に接続され、各抵抗体には切断用ヒューズが並列に接続された抵抗値補正用抵抗群と、複数の抵抗体が直列に接続され、各抵抗体には切断用ヒューズが並列に接続された誤差補正用抵抗群と、を備え、前記抵抗値補正用抵抗群と誤差補正用抵抗群が直列に接続され、抵抗値を調整するために、前記抵抗値補正用抵抗群の中からヒューズが切断されるとともに、抵抗体の製造のばらつきの誤差値に応じて誤差補正用抵抗群から誤差分に対応する誤差補正用抵抗体のヒューズが切断される抵抗回路であって、
前記抵抗値補正用抵抗群の抵抗体の数と、誤差補正用抵抗群の抵抗体の数とを同一にするとともに抵抗値補正用抵抗群の各抵抗体と誤差補正用抵抗群の各抵抗体とを対応させ、
誤差補正用抵抗群の各抵抗体の抵抗値を、対応する抵抗値補正用抵抗群の抵抗体の抵抗値の誤差に設定したことを特徴とする。
The resistor circuit of this invention, a plurality of resistors are connected in series, and each resistor is connected to a resistance value correcting resistor group in which a cutting fuse is connected in parallel, and a plurality of resistors are connected in series to each resistor. The body includes an error correction resistor group in which cutting fuses are connected in parallel, and the resistance value correction resistor group and the error correction resistor group are connected in series to adjust the resistance value. The fuse is cut from the resistance correction resistor group, and the error correction resistor fuse corresponding to the error is cut from the error correction resistor group according to the error value of the manufacturing variation of the resistor. A resistance circuit ,
The number of resistors in the resistance value correcting resistor group is the same as the number of resistors in the error correcting resistor group, and each resistor in the resistance value correcting resistor group and each resistor in the error correcting resistor group And
The resistance value of each resistor in the error correction resistor group is set to the error of the resistance value of the corresponding resistor in the resistance value correction resistor group .

この発明の抵抗回路の抵抗調整方法は、複数の抵抗体が直列に接続され、各抵抗体には切断用ヒューズが並列に接続された抵抗値補正用抵抗群と、複数の抵抗体が直列に接続され、各抵抗体には切断用ヒューズが並列に接続された誤差補正用抵抗群と、を備え、前記抵抗値補正用抵抗群と誤差補正用抵抗群が直列に接続され、抵抗値を調整するために、前記抵抗値補正用抵抗群の中からヒューズを切断する抵抗体を選択し、選択された抵抗体の誤差を求め、選択された抵抗体から抵抗値の大きな抵抗体のヒューズを切断し、次に、大きな抵抗体のヒューズを切断する前に、求めた誤差と誤差の許容範囲とを比較し、許容範囲を超える場合には、誤差補正用抵抗群から誤差分を補正する誤差補正用抵抗体を選択し、この抵抗体のヒューズを切断して、誤差を補正する抵抗回路の抵抗値調整方法であって、
前記抵抗値補正用抵抗群の抵抗体の数と、誤差補正用抵抗群の抵抗体の数とを同一にするとともに抵抗値補正用抵抗群の各抵抗体と誤差補正用抵抗群の各抵抗体とを対応させ、
誤差補正用抵抗群の各抵抗体の抵抗値を、対応する抵抗値補正用抵抗群の抵抗体の抵抗値の誤差に設定したことを特徴とする。
According to the resistance adjustment method of the resistance circuit of the present invention, a plurality of resistors are connected in series, and a resistance value correcting resistor group in which a cutting fuse is connected in parallel to each resistor, and a plurality of resistors are connected in series. Each resistor is provided with an error correcting resistor group in which a cutting fuse is connected in parallel. The resistance value correcting resistor group and the error correcting resistor group are connected in series to adjust the resistance value. To select the resistor for cutting the fuse from the resistance value correcting resistor group, obtain the error of the selected resistor, and cut the fuse of the resistor having a large resistance value from the selected resistor Then, before cutting the large resistor fuse, compare the obtained error with the allowable error range, and if it exceeds the allowable range, correct the error from the error correction resistor group. Select a resistor for the fuse and cut the fuse of this resistor Te, a resistance value adjustment method of the resistor circuit you correct the error,
The number of resistors in the resistance value correcting resistor group is the same as the number of resistors in the error correcting resistor group, and each resistor in the resistance value correcting resistor group and each resistor in the error correcting resistor group And
The resistance value of each resistor in the error correction resistor group is set to the error of the resistance value of the corresponding resistor in the resistance value correction resistor group .

また、抵抗回路の抵抗調整方法は、複数の抵抗体が直列に接続され、各抵抗体には切断用ヒューズが並列に接続された抵抗値補正用抵抗群と、複数の抵抗体が直列に接続され、各抵抗体には切断用ヒューズが並列に接続された誤差補正用抵抗群と、を備え、前記抵抗値補正用抵抗群と誤差補正用抵抗群が直列に接続され、抵抗値を調整するために、トリミングコードを求め、トータルの誤差より抵抗値補正用抵抗体が大きい抵抗体の中で最小ビットを求め、該当する最小ビットのヒューズを切断した後、誤差補正用抵抗群から誤差分を補正する誤差補正用抵抗体を選択し、この抵抗体のヒューズを切断して誤差を補正する抵抗回路の抵抗値調整方法であって、
前記抵抗値補正用抵抗群の抵抗体の数と、誤差補正用抵抗群の抵抗体の数とを同一にするとともに抵抗値補正用抵抗群の各抵抗体と誤差補正用抵抗群の各抵抗体とを対応させ、
誤差補正用抵抗群の各抵抗体の抵抗値を、対応する抵抗値補正用抵抗群の抵抗体の抵抗値の誤差に設定したことを特徴とする。
Also, the resistance adjustment method of the resistance circuit is such that a plurality of resistors are connected in series, a resistance value correcting resistor group in which a cutting fuse is connected in parallel to each resistor, and a plurality of resistors are connected in series. Each resistor includes an error correction resistor group in which a cutting fuse is connected in parallel, and the resistance value correction resistor group and the error correction resistor group are connected in series to adjust the resistance value. Therefore, the trimming code is obtained, the smallest bit among the resistors whose resistance value correction resistors are larger than the total error is obtained, the fuse of the corresponding minimum bit is cut, and the error amount is obtained from the error correction resistor group. select a correction to the error correction resistor, a resistance value adjustment method of the resistor circuit you correct the error by cutting the fuses of the resistor,
The number of resistors in the resistance value correcting resistor group is the same as the number of resistors in the error correcting resistor group, and each resistor in the resistance value correcting resistor group and each resistor in the error correcting resistor group And
The resistance value of each resistor in the error correction resistor group is set to the error of the resistance value of the corresponding resistor in the resistance value correction resistor group .

この発明によれば、トータル誤差が抵抗値補正用抵抗体で補正できる補正量を超える前に、誤差補正用抵抗体で誤差分を調整することができ、抵抗体の製造のばらつきの誤差を含め、精度良く調整が行える抵抗回路を提供することができる。   According to the present invention, before the total error exceeds the correction amount that can be corrected by the resistor for correcting the resistance value, the error can be adjusted by the error correcting resistor, including errors in manufacturing variations of the resistor. Therefore, it is possible to provide a resistance circuit that can be adjusted with high accuracy.

この発明の実施の形態について図面を参照しながら詳細に説明する。なお、図中同一または相当部分には同一符号を付し、説明の重複を避けるためにその説明は繰返さない。図1は、この発明に用いられる抵抗回路の一実施形態を示す回路図である。   Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated in order to avoid duplication of description. FIG. 1 is a circuit diagram showing an embodiment of a resistance circuit used in the present invention.

図1に示すように、抵抗値補正用抵抗群1と誤差補正用抵抗群2とが直列に接続されている。抵抗値補正用抵抗群1は、複数の抵抗体R1、R2、…、Rn、…Rmが直列に接続され、各抵抗体R1、R2、…、Rn、…、Rmには切断用ヒューズf1、f2、…、fn、…、fmが並列に接続されている。誤差補正用抵抗群2は、複数の誤差補正用抵抗体Ra1、…、Ramが直列に接続され、各誤差補正用抵抗体Ra1、…、Ranには切断用ヒューズfa1、…、fanが並列に接続されている。   As shown in FIG. 1, a resistance value correcting resistor group 1 and an error correcting resistor group 2 are connected in series. In the resistance value correcting resistor group 1, a plurality of resistors R1, R2,..., Rn,... Rm are connected in series, and the resistors R1, R2,. f2, ..., fn, ..., fm are connected in parallel. In the error correction resistor group 2, a plurality of error correction resistors Ra1,..., Ram are connected in series, and a cutting fuse fa1,. It is connected.

この実施形態においては、トップ側の抵抗体Rtに抵抗値補正用抵抗群1が接続され、トップ側から順に二進数的に抵抗値が減少するように設定されている。トップ側の抵抗体Rt側の抵抗体R1がビット1(B1)に対応し、以下二進数的に抵抗値が減少してビットm(Bm)用の抵抗体Rmまでm個の抵抗体R1、R2、…、Rmが直列に接続されている。   In this embodiment, the resistance value correcting resistor group 1 is connected to the top-side resistor Rt, and the resistance value is set so as to decrease in a binary number in order from the top side. The resistor R1 on the top side resistor Rt side corresponds to the bit 1 (B1), and the resistance value decreases in a binary number to m resistors R1 up to the resistor Rm for the bit m (Bm). R2, ..., Rm are connected in series.

誤差補正用抵抗群2は、抵抗値補正用抵抗群1とボトム側の抵抗体Rbとの間に直列に接続されている。誤差補正用抵抗体Ra1、…、Ramは、誤差に対応して例えば、抵抗値補正用抵抗体の10%の抵抗をそれぞれ有して構成されている。   The error correction resistor group 2 is connected in series between the resistance value correction resistor group 1 and the bottom resistor Rb. The error correction resistors Ra1,..., Ram are configured to have, for example, a 10% resistance of the resistance value correction resistor corresponding to the error.

抵抗値を調整するときには、抵抗回路を用いる回路に実装して、実際に動作させ、オンラインにより、抵抗を調整するためのトリミングコードを求め、そのコードを2進数に変換する。2進数に変換されたトリミングコードに応じて、対応するビットの切断用ヒューズf1、f2…fn−1…fmを選択する。対応するビットの切断用ヒューズf1、f2…fn−1…fmを切断して抵抗値を補正する。   When adjusting the resistance value, it is mounted on a circuit using a resistance circuit and actually operated, and a trimming code for adjusting the resistance is obtained online, and the code is converted into a binary number. Corresponding bit cutting fuses f1, f2,..., Fn-1... Fm are selected according to the trimming code converted into binary numbers. The corresponding fuses f1, f2,..., Fn-1,.

図1の抵抗回路の実施形態を図7の電圧検出回路の分圧抵抗R11、R12に適用した時の抵抗値の補正について説明する。電圧検出回路の一実施形態を図1及び図7を用いて説明する。例えば、抵抗素子Rb端を接地し、抵抗素子Rt端を端子23に接続し、抵抗素子Rb、RT間の端子ノードLを演算増幅器15の非反転入力端子に接続する。分圧抵抗R11はRt、抵抗値補正抵抗体R1、R2、…、Rm、誤差補正用抵抗体Ra1、…、Ram及び切断用ヒューズf1、f2、…、fn−1、…、fm、切断用ヒューズfa1、…、fanにより構成され、分圧抵抗R12はRbにより構成される。   The correction of the resistance value when the embodiment of the resistor circuit of FIG. 1 is applied to the voltage dividing resistors R11 and R12 of the voltage detection circuit of FIG. 7 will be described. An embodiment of the voltage detection circuit will be described with reference to FIGS. For example, the resistance element Rb end is grounded, the resistance element Rt end is connected to the terminal 23, and the terminal node L between the resistance elements Rb and RT is connected to the non-inverting input terminal of the operational amplifier 15. The voltage dividing resistor R11 is Rt, resistance value correcting resistors R1, R2,..., Rm, error correcting resistors Ra1,... Ram, and cutting fuses f1, f2,. .., Fan and the voltage dividing resistor R12 is composed of Rb.

端子ノードLから演算増幅器15の非反転入力端子に入力する分圧電圧を調整する場合、次の数式(1)からトリミングコードTを求めることができる。   When adjusting the divided voltage input from the terminal node L to the non-inverting input terminal of the operational amplifier 15, the trimming code T can be obtained from the following equation (1).

T=(Rt+Rb)×(Vset/Vmes−1)/Rt
ここで、Vsetは電圧検出回路の検出電圧設定値、Vmesはヒューズ切断前に設定差された演算増幅器15の出力が例えば「H」から「L」へ反転する入力端子23での入力電圧値である。
T = (Rt + Rb) × (Vset / Vmes−1) / Rt
Here, Vset is a detection voltage setting value of the voltage detection circuit, Vmes is an input voltage value at the input terminal 23 at which the output of the operational amplifier 15 set and changed before the fuse is blown is inverted from “H” to “L”, for example. is there.

上記した式で求められたトリミングコードTを2進数に変換し、抵抗値補正抵抗体R1、R2、…、Rmに対応するビットの抵抗体のヒューズを切断することにより、検出電圧が設定電圧となる。   The trimming code T obtained by the above equation is converted into a binary number, and the detection voltage is set to the set voltage by cutting the fuse of the bit resistor corresponding to the resistance correction resistors R1, R2,. Become.

この実施形態の説明においては、補正量がΔVで求められ、補正ビットに対応する補正量も図5及び図6に示すように、ΔV1、ΔV2…ΔVとしている。補正量ΔVnとその補正用抵抗体Rnとは以下の式の関係があるので、基準電圧Vref、補正量ΔVnとRbを与えれば、補正用抵抗体のRnの抵抗値を求めることができる。   In the description of this embodiment, the correction amount is obtained by ΔV, and the correction amounts corresponding to the correction bits are also set to ΔV1, ΔV2,... ΔV as shown in FIGS. Since the correction amount ΔVn and the correction resistor Rn have the following relationship, if the reference voltage Vref and the correction amounts ΔVn and Rb are given, the resistance value of Rn of the correction resistor can be obtained.

ΔVn=(Rn/Rb)×Vref   ΔVn = (Rn / Rb) × Vref

図5及び図6に示すように、各補正量に製造プロセス上、誤差が生じる。この実施形態においては、誤差は、量産での実際の製造ばらつきやプロセスレイアウトから経験上予想されるばらつきにより予め決めておく。例えば、誤差が10%の場合には、補正量Δnの10%の値が誤差αnとなる。   As shown in FIGS. 5 and 6, an error occurs in each correction amount in the manufacturing process. In this embodiment, the error is determined in advance based on actual manufacturing variations in mass production and variations expected from experience from the process layout. For example, when the error is 10%, a value of 10% of the correction amount Δn becomes the error αn.

上記したように、トリミングコードを求め、対応するビットのヒューズを切断することにより、検出電圧を設定電圧にするように抵抗値を調整するが、補正用抵抗体にも誤差が存在する。この誤差により、所定のビットのヒューズを切断しても、LSBのビットでは対応できなくなる誤差が生じる場合がある。この場合には、この誤差により、精度が悪くなるという問題がある。この問題につき、図2ないし図6を参照して説明する。   As described above, the trimming code is obtained, and the resistance value is adjusted so that the detection voltage becomes the set voltage by cutting the fuse of the corresponding bit. However, there is also an error in the correction resistor. This error may cause an error that cannot be handled by the LSB bit even if the fuse of the predetermined bit is cut. In this case, there is a problem that the accuracy deteriorates due to this error. This problem will be described with reference to FIGS.

説明を簡単にするために、以下では補正ビットが4ビットの場合を例に挙げる。補正量Δは16とする。各補正量は、ビット1が8、ビット2が4、ビット3が2、ビット1(LSB)が1である。誤差は10%とした。   In order to simplify the description, a case where the correction bit is 4 bits will be described as an example below. The correction amount Δ is 16. For each correction amount, bit 1 is 8, bit 2 is 4, bit 3 is 2, and bit 1 (LSB) is 1. The error was 10%.

図2は誤差がすべて−10%の場合を示している。各ビットのヒューズを切断し、ビット4の補正を行うことにより、設計上は補正量はLSBの範囲内の「1」に収まるよう構成されている。しかし、図2、図4及び図6に示すように、ビット4の処理を行った後のトータル誤差は1.5になっている。このため、設計上予定した補正ができないことになる。   FIG. 2 shows a case where all the errors are −10%. By cutting the fuse of each bit and correcting bit 4, the correction amount is designed to be within “1” within the range of LSB. However, as shown in FIGS. 2, 4 and 6, the total error after processing bit 4 is 1.5. For this reason, the correction scheduled in design cannot be performed.

そこで、この発明においては、この誤差を考慮して、不足分の誤差をトータル誤差を誤差補正用抵抗体Ra1…Ramを用いて補うように処理を行うものである。   Therefore, in the present invention, in consideration of this error, processing is performed so that the error of the shortage is compensated by using the error correction resistors Ra1... Ram.

この実施形態においては、算出したトリミングコードに基づき、補正量のトータル誤差を求める。すなわち、対応するビットを切断するときそれぞれのトータルの誤差を求める。図5に示すように、補正量Δnのトータル誤差はα1+α2+…+αnとなる。   In this embodiment, the total error of the correction amount is obtained based on the calculated trimming code. That is, each total error is obtained when the corresponding bit is cut. As shown in FIG. 5, the total error of the correction amount Δn is α1 + α2 +.

この実施形態では、トータルの誤差(Errn)<補正量Δnとなる最小ビットを求める。図6の例では、3ビットのとき誤差が1.4であり、補正量が2である。また、4ビットのときの補正量は1であり、この誤差は次の補正量で対応できる許容範囲を超えている。すなわち、求めたトータル誤差が誤差の許容範囲内とは次の補正量で対応できる誤差の範囲以内であることを示している。この誤差の許容範囲を比較し、許容範囲を超えるか否か判断することは、トータルの誤差(Errn)<補正量Δnとなる最小ビットを求めることになる。   In this embodiment, the minimum bit that satisfies total error (Errn) <correction amount Δn is obtained. In the example of FIG. 6, the error is 1.4 and the correction amount is 2 for 3 bits. Further, the correction amount in the case of 4 bits is 1, and this error exceeds an allowable range that can be handled by the next correction amount. That is, the obtained total error is within the error tolerance range that can be handled by the next correction amount. Comparing the permissible ranges of this error and determining whether or not the permissible range is exceeded, finds the minimum bit that satisfies total error (Errn) <correction amount Δn.

図4に示す4ビットの場合には、トータルの誤差(Errn)<補正量Δnとなる最小ビットが3ビットとなる。よって、3ビットのヒューズを切断した後、トータル誤差のErnnを補正する。誤差補正用抵抗体Ra1…Ramによる誤差の補正量は、トータルの誤差(1.4)から(トータル誤差補正量+処理ビットの補正量)の1/2である1.7の範囲で誤差補正ビットを選択する。   In the case of 4 bits shown in FIG. 4, the minimum bit that satisfies the total error (Errn) <correction amount Δn is 3 bits. Therefore, after the 3-bit fuse is cut, the total error Ernn is corrected. The error correction amount by the error correction resistors Ra1... Ram is within a range of 1.7 which is ½ of the total error (1.4) to (total error correction amount + processing bit correction amount). Select a bit.

誤差補正量に対応する誤差補正用抵抗体Ra1、…、Ramを選び、該当する切断用ヒューズfa1…fanを切断する。誤差補正用抵抗体Ra1、…、Ramは、誤差に対応して例えば、抵抗値補正用抵抗体の10%の抵抗をそれぞれ有して構成した場合には、トリミングビットと対応して誤差補正用ビットを構成すればよい。この場合には、誤差補正用ビットは、上記の算出した最小ビットまでのビットの誤差補正用抵抗体Ra1…Ramのヒューズを切断して、誤差を補正する。この誤差補正により、次に選択する抵抗値補正用抵抗体の補正量の範囲内で補正が行えるようになる。   The error correction resistors Ra1,..., Ram corresponding to the error correction amount are selected, and the corresponding cutting fuses fa1,. The error correction resistors Ra1,..., Ram correspond to the error, for example, in the case where each of the resistance correction resistors Ra1,. What is necessary is just to comprise a bit. In this case, the error correction bit corrects the error by cutting the fuse of the error correction resistors Ra1... Ram of the bits up to the calculated minimum bit. By this error correction, correction can be performed within the range of the correction amount of the resistance value correcting resistor to be selected next.

この4ビットの例では、図4に示すように、3ビットの処理の後、誤差補正ビットの処理により、4ビット即ちLSBの範囲内での補正が行えるようになる。   In this 4-bit example, as shown in FIG. 4, after the 3-bit processing, correction within the 4-bit, that is, LSB range can be performed by the error correction bit processing.

なお、図3は、誤差がすべて+α(10%)とした場合を示している。すると、4ビットの処理をする前に、ターゲット値を超えてしまうことになる。したがって、このような場合にも、4ビットのヒューズを切断すると、より精度が悪くなるので、4ビットのヒューズは切断せず、4ビットの誤差補正用ヒューズで誤差α4の分の補正を行えばよい。   FIG. 3 shows a case where the errors are all + α (10%). Then, the target value is exceeded before 4-bit processing. Therefore, even in such a case, if the 4-bit fuse is cut, the accuracy becomes worse. Therefore, if the 4-bit error correction fuse is used to correct the error α4, the 4-bit fuse is not cut. Good.

今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。この発明の範囲は、上記した実施の形態の説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。   The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims for patent.

この発明に用いられる抵抗回路の一実施形態を示す回路図である。It is a circuit diagram which shows one Embodiment of the resistance circuit used for this invention. この発明の抵抗回路の調整方法を説明するための図である。It is a figure for demonstrating the adjustment method of the resistance circuit of this invention. この発明の抵抗回路の調整方法を説明するための図である。It is a figure for demonstrating the adjustment method of the resistance circuit of this invention. 3ビットの処理を行ったときのトータル誤差と補正量との関係を示す図である。It is a figure which shows the relationship between a total error when a 3-bit process is performed, and a correction amount. ビットと補正量Δと誤差とトータル誤差の関係を示す図である。It is a figure which shows the relationship between a bit, correction amount (DELTA), an error, and a total error. ビットと補正量Δと誤差とトータル誤差の関係を示す図である。It is a figure which shows the relationship between a bit, correction amount (DELTA), an error, and a total error. 電圧検出回路の一例を示す回路図である。It is a circuit diagram which shows an example of a voltage detection circuit. 定電圧発生回路の一例を示す回路図である。It is a circuit diagram which shows an example of a constant voltage generation circuit. 分圧抵抗を構成する従来の抵抗回路を示す回路図である。It is a circuit diagram which shows the conventional resistance circuit which comprises a voltage dividing resistor.

符号の説明Explanation of symbols

1 抵抗値補正用抵抗群、R1、R2、…、Rn、…Rm 抵抗体、f1、f2、…、fn、…、fm 切断用ヒューズ、2 誤差補正用抵抗群、Ra1、…、Ram 誤差補正用抵抗体、fa1、…、fan 切断用ヒューズ。 1 resistance value correcting resistor group, R1, R2,..., Rn,... Rm resistor, f1, f2,..., Fn cutting fuse, 2 error correcting resistor group, Ra1,. Resistor, fa1,..., Fan cutting fuse.

Claims (3)

複数の抵抗体が直列に接続され、各抵抗体には切断用ヒューズが並列に接続された抵抗値補正用抵抗群と、複数の抵抗体が直列に接続され、各抵抗体には切断用ヒューズが並列に接続された誤差補正用抵抗群と、を備え、前記抵抗値補正用抵抗群と誤差補正用抵抗群が直列に接続され、抵抗値を調整するために、前記抵抗値補正用抵抗群の中からヒューズが切断されるとともに、抵抗体の製造のばらつきの誤差値に応じて誤差補正用抵抗群から誤差分に対応する誤差補正用抵抗体のヒューズが切断される抵抗回路であって、
前記抵抗値補正用抵抗群の抵抗体の数と、誤差補正用抵抗群の抵抗体の数とを同一にするとともに抵抗値補正用抵抗群の各抵抗体と誤差補正用抵抗群の各抵抗体とを対応させ、
誤差補正用抵抗群の各抵抗体の抵抗値を、対応する抵抗値補正用抵抗群の抵抗体の抵抗値の誤差に設定したことを特徴とする抵抗回路
A plurality of resistors are connected in series, a resistance value correcting resistor group in which a cutting fuse is connected in parallel to each resistor, and a plurality of resistors are connected in series, and each resistor is connected to a cutting fuse Are connected in parallel, and the resistance value correcting resistor group and the error correcting resistor group are connected in series, and the resistance value correcting resistor group is used to adjust the resistance value. A resistor circuit in which the fuse of the error correction resistor corresponding to the error is cut from the error correction resistor group in accordance with the error value of the variation in manufacturing of the resistor .
The number of resistors in the resistance value correcting resistor group is the same as the number of resistors in the error correcting resistor group, and each resistor in the resistance value correcting resistor group and each resistor in the error correcting resistor group And
A resistance circuit characterized in that the resistance value of each resistor in the error correction resistor group is set to an error in the resistance value of the resistor in the corresponding resistance value correction resistor group .
複数の抵抗体が直列に接続され、各抵抗体には切断用ヒューズが並列に接続された抵抗値補正用抵抗群と、複数の抵抗体が直列に接続され、各抵抗体には切断用ヒューズが並列に接続された誤差補正用抵抗群と、を備え、前記抵抗値補正用抵抗群と誤差補正用抵抗群が直列に接続され、抵抗値を調整するために、前記抵抗値補正用抵抗群の中からヒューズを切断する抵抗体を選択し、選択された抵抗体の誤差を求め、選択された抵抗体から抵抗値の大きな抵抗体のヒューズを切断し、次に、大きな抵抗体のヒューズを切断する前に、求めた誤差と誤差の許容範囲とを比較し、許容範囲を超える場合には、誤差補正用抵抗群から誤差分を補正する誤差補正用抵抗体を選択し、この抵抗体のヒューズを切断して、誤差を補正する抵抗回路の抵抗値調整方法であって、
前記抵抗値補正用抵抗群の抵抗体の数と、誤差補正用抵抗群の抵抗体の数とを同一にするとともに抵抗値補正用抵抗群の各抵抗体と誤差補正用抵抗群の各抵抗体とを対応させ、
誤差補正用抵抗群の各抵抗体の抵抗値を、対応する抵抗値補正用抵抗群の抵抗体の抵抗値の誤差に設定したことを特徴とする抵抗値調整方法
A plurality of resistors are connected in series, a resistance value correcting resistor group in which a cutting fuse is connected in parallel to each resistor, and a plurality of resistors are connected in series, and each resistor is connected to a cutting fuse Are connected in parallel, and the resistance value correcting resistor group and the error correcting resistor group are connected in series, and the resistance value correcting resistor group is used to adjust the resistance value. Select the resistor to cut the fuse from, select the error of the selected resistor, cut the fuse of the resistor with the large resistance value from the selected resistor, and then connect the fuse with the large resistor Before cutting, compare the obtained error with the allowable error range.If the error exceeds the allowable range, select the error correction resistor that corrects the error from the error correction resistor group. by cutting the fuse, correct the error resistance circuit resistance A settling method,
The number of resistors in the resistance value correcting resistor group is the same as the number of resistors in the error correcting resistor group, and each resistor in the resistance value correcting resistor group and each resistor in the error correcting resistor group And
A resistance value adjusting method, wherein the resistance value of each resistor in the error correcting resistor group is set to an error in the resistance value of the corresponding resistor in the resistance value correcting resistor group .
複数の抵抗体が直列に接続され、各抵抗体には切断用ヒューズが並列に接続された抵抗値補正用抵抗群と、複数の抵抗体が直列に接続され、各抵抗体には切断用ヒューズが並列に接続された誤差補正用抵抗群と、を備え、前記抵抗値補正用抵抗群と誤差補正用抵抗群が直列に接続され、抵抗値を調整するために、トリミングコードを求め、トータルの誤差より抵抗値補正用抵抗体が大きい抵抗体の中で最小ビットを求め、該当する最小ビットのヒューズを切断した後、誤差補正用抵抗群から誤差分を補正する誤差補正用抵抗体を選択し、この抵抗体のヒューズを切断して誤差を補正する抵抗回路の抵抗値調整方法であって、
前記抵抗値補正用抵抗群の抵抗体の数と、誤差補正用抵抗群の抵抗体の数とを同一にするとともに抵抗値補正用抵抗群の各抵抗体と誤差補正用抵抗群の各抵抗体とを対応させ、
誤差補正用抵抗群の各抵抗体の抵抗値を、対応する抵抗値補正用抵抗群の抵抗体の抵抗値の誤差に設定したことを特徴とする抵抗値調整方法
A plurality of resistors are connected in series, a resistance value correcting resistor group in which a cutting fuse is connected in parallel to each resistor, and a plurality of resistors are connected in series, and each resistor is connected to a cutting fuse Are connected in parallel, the resistance correction resistor group and the error correction resistor group are connected in series, and a trimming code is obtained to adjust the resistance value, Find the smallest bit among the resistors whose resistance value correction resistor is larger than the error, cut the fuse of the corresponding minimum bit, and then select the error correction resistor that corrects the error from the error correction resistor group. , a resistance value adjustment method of the resistor circuit you correct the error by cutting the fuses of the resistor,
The number of resistors in the resistance value correcting resistor group is the same as the number of resistors in the error correcting resistor group, and each resistor in the resistance value correcting resistor group and each resistor in the error correcting resistor group And
A resistance value adjusting method, wherein the resistance value of each resistor in the error correcting resistor group is set to an error in the resistance value of the corresponding resistor in the resistance value correcting resistor group .
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