JP5223629B2 - Storage device and storage system - Google Patents

Description

  The present invention relates to a storage device and a storage system.

  2. Description of the Related Art Conventionally, a disk array device is known that calculates the parity of input data and stores the data and parity in different storage means (see, for example, Patent Document 1).

  The disk array device is provided to receive and temporarily store input data, and to provide a plurality of memories for inputting the stored data to the data transmission means, and to be paired with each of the plurality of memories. The error correction information is generated from the same data as the data stored in the memory, and a plurality of error correction information generation means for inputting the generated error correction information to the data transmission means, the data from the memory, and the memory The error correction information from the error correction information generating means is received via the data transmission means, and the data from the memory and the error correction information from the error correction information generating means paired with the memory are stored in different storage means. Storage control means for sorting and storing.

In addition, in a storage device that employs RAID 5 in general, it is necessary to read stored parity and data at the time of data writing, and write data after performing parity calculation based on the read parity and data. Writing speed becomes slow.
JP 2001-337759 A

  An object of the present invention is to provide a storage device and a storage system capable of improving the data writing speed without imposing a load on the host device as compared with the case where the present configuration is not provided.

  In order to achieve the above object, the present invention provides the following storage device and storage system.

[1] A first control unit that transmits and receives data to and from a higher-level device, and the first control unit via an optical transmission line that allows collective transmission of data in the downstream direction from the first control unit. A plurality of second control units connected to the plurality of second control units, and a plurality of storage units connected to the plurality of second control units and storing the data, wherein the first control unit The data received from is divided into data strings, and the data strings are collectively transmitted to the plurality of second control units via the optical transmission path, and the plurality of second control units are configured to perform the first control. A parity calculation unit that calculates parity information based on the data sequence and at least one second control unit writes the parity information in the corresponding storage unit As shown in FIG. A determination unit that determines whether or not to write information, and when the determination unit determines to write parity information to the storage unit, the storage unit corresponding to the parity information calculated by the parity calculation unit A storage device that writes the data string to the corresponding storage unit when it is not determined that the parity information is written to the storage unit by the determination unit.

[2] The determination unit determines, for each data string, based on information included in the data string, so that at least one second control unit writes the parity information in the corresponding storage unit . 1].

[3] The determination unit determines, for each data string, at least one second control unit to write the parity information based on address information specified as a write destination of the data string. ] The memory | storage device as described in.

[4] When the first control unit receives the parity information and the data sequence stored in the plurality of storage units from the plurality of second control units, the first control unit uses the parity information to generate the data sequence. The storage device according to [1], wherein error detection is performed.

[5] The first control unit has detection means for detecting divided data having errors among the plurality of divided data, and when the detected divided data is detected by the detecting means, The storage device according to claim 1, wherein error correction is performed on the erroneous divided data by using parity information and error-free divided data.

[6] The above apparatus further includes a plurality of power supply units that respectively supply power by pairing the plurality of storage units and the plurality of second control units connected to the plurality of storage units. 1].

[7] A first control unit that transmits and receives data between the host device and the host device, and the first control unit via the optical transmission path capable of batch transmission of data in the downstream direction from the first control unit. A plurality of second control units connected to one control unit, and a plurality of storage units connected to the plurality of second control units, respectively, for storing the data, the first control unit Divides the data received from the higher-level device into data strings, and transmits the data strings to the plurality of second control units through the optical transmission line, and the plurality of second control units includes: When the data sequence transmitted in batch from the first control unit is received, a parity calculation unit that calculates parity information based on the data sequence and at least one second control unit correspond to the parity information. For each data string, the data is written in the storage unit. A determination unit that determines whether or not to write parity information in the storage unit, and corresponds to the parity information calculated by the parity calculation unit when the determination unit determines to write the parity information to the storage unit. And a storage device that writes the data string to the corresponding storage units when it is not determined to write parity information to the storage unit by the determination unit .

  According to the first and seventh aspects of the invention, the data writing speed can be improved without imposing a load on the host device, as compared with the case where the present configuration is not provided.

  According to the invention of claim 2, parity information can be distributed and stored in the storage unit.

  According to the invention which concerns on Claim 3, compared with the case where it does not have this structure, a some 2nd control part is realizable with a simple structure.

  According to the invention which concerns on Claim 4, compared with the case where it does not have this structure, the load of the high-order apparatus accompanying an error detection can be reduced.

  According to the invention which concerns on Claim 5, the error correction of division | segmentation data can be enabled by parity information.

  According to the invention which concerns on Claim 6, even when one power supply part fails, the original data can be decompress | restored from the data memorize | stored in the other memory | storage part.

The storage device according to the present embodiment includes a first control unit that transmits and receives data to and from a higher-level device, and an optical transmission path that can perform batch transmission of data from the first control unit in the downlink direction. A plurality of second control units connected to the first control unit, and a plurality of storage units respectively connected to the plurality of second control units and storing the data , The control unit divides the data received from the higher-level device into data strings, and transmits the data string to the plurality of second control units through the optical transmission line, and the plurality of second control units A parity calculation unit that calculates parity information based on the data sequence when receiving the data sequence that is collectively transmitted from the first control unit, and at least one second control unit receives the parity information. The data string to be written to the corresponding storage unit The parity information calculated by the parity calculation unit when the determination unit determines to write the parity information to the storage unit. Is written in the corresponding storage unit, and when the determination unit does not determine that the parity information is written in the storage unit, the data string is written in the corresponding storage unit.

  In the above configuration, when each of the plurality of second control units receives a data string that is collectively transmitted via the optical transmission path, it selects either parity or data and is parallel to the storage unit connected to itself. To write. That is, processing such as calculation of parity, selection of data, and writing of parity or data to the storage unit is performed in parallel by a plurality of second control units on the data string receiving side. Further, since the parity is calculated by the second control unit, it is not necessary to calculate the parity in the host device, and the load on the host device is reduced.

[First Embodiment]
FIG. 1 is a block diagram showing an example of a schematic configuration of a storage system according to the first embodiment of the present invention. The storage system 100 is configured by connecting a storage device 1 to a host device (higher level device) 2.

(Host device)
The host device 2 requests the storage device 1 to write or read data. Such a host device 2 includes, for example, a server, a computer (PC), a workstation (WS), and the like.

  The host device 2 is connected to the storage device 1 via the cable 101. Between the host device 2 and the storage device 1, for example, serial ATA, SAS, Fiber Channel, InfiniBand, PCI Express, IDE, SCSI It conforms to interface standards such as. The cable 101 may be an optical line or an electric line. The host device 2 may include a port connected to a communication network such as a local area network (LAN) or the Internet, and may be connected to another host device or terminal device via the port.

(Storage device)
The storage device 1 includes a host bridge unit (first control unit) 11 that transmits and receives data to and from the host device 2, and an optical branching transmission line 15 and an optical multiplexing transmission line 17 that are described later in the host bridge unit 11. Connected to each of the first to fifth memory controllers (second control units) 12A to 12E and the first to fifth memory controllers 12A to 12E connected to each other through a predetermined size such as 512 bytes. And first to fifth memories (storage units) 13A to 13E in which data is written and read in units of block data (data string).

  The storage device 1 also converts an electrical signal as data sent from the host bridge unit 11 into an optical signal, and an optical branch transmission that branches the optical signal from the E / O 14 and transmits the optical signal collectively in the downstream direction. O / E 16A to 16E which respectively convert the optical signal transmitted by the path 15 and the optical branch transmission path 15 into an electrical signal and send the electrical signal to the first to fifth memory controllers 12A to 12E as data, E / Os 14A to 14E that convert electrical signals as data sent from the first to fifth memory controllers 12A to 12E, respectively, and a plurality of optical signals from the E / Os 14A to 14E into one optical signal. An optical multiplexing transmission line 17 that multiplexes and transmits in the upstream direction, and an optical signal transmitted through the optical multiplexing transmission line 17 is converted into an electric signal, and the electric signal is converted into data. And an O / E16 to send to the host bridge 11 as.

(E / O)
The E / O 14, 14A to 14E include, for example, a light emitting element realized by a semiconductor laser, a light emitting diode, or the like, and a drive circuit that drives the light emitting element.

(O / E)
Each of the O / Es 16 and 16A to 16E includes a light receiving element realized by a semiconductor photodiode or the like and an amplifier circuit that amplifies a current converted from an optical signal received by the light receiving element.

(Optical branch transmission line)
The optical branching transmission line 15 includes an optical fiber 150A for transmitting an optical signal from the E / O 14, an optical branching unit 151 for branching one optical signal incident from the optical fiber 150A into five optical signals, and an optical branching unit. The optical fiber 150B transmits the five optical signals branched by 151 to the O / Es 16A to 16E, respectively.

  The optical branching unit 151 is configured by, for example, a sheet-like optical waveguide (optical sheet bus), an optical coupler, and the like. The sheet-like optical waveguide is made of a sheet-like transparent medium having a uniform thickness, and is made of, for example, a plastic material such as polymethyl methacrylate, polycarbonate, amorphous polyolefin, or inorganic glass. The sheet-like optical waveguide uniformly diffuses the light incident from the optical fiber 150A and emits it to the five optical fibers 150B.

(Optical multiplexing transmission line)
The optical multiplexing transmission path 17 includes an optical fiber 170A that transmits five optical signals from the E / Os 14A to 14E, and an optical multiplexing unit that combines the five optical signals incident from the optical fiber 170A into one optical signal. 171 and an optical fiber 170B that transmits one optical signal multiplexed by the optical multiplexing unit 171 to the O / E 16.

  The optical multiplexing unit 171 is obtained by switching the incident side and the emission side of the optical branching unit 151, and is configured in the same manner as the optical branching unit 151.

(memory)
The first to fifth memories 13A to 13E are storage units in which data is written and read via the first to fifth memory controllers 12A to 12E. For the memories 13A to 13E, for example, a volatile semiconductor memory such as a DRAM or a nonvolatile semiconductor memory such as a flash memory is used. The first to fifth memories 13A to 13E are supplied with a driving voltage from a power supply unit (not shown).

  The memories 13A to 13E may be magnetic hard disks, optical disks such as DVDs, or other storage methods. When a semiconductor memory is used as the memories 13A to 13E, it is advantageous in terms of access speed, fault tolerance, power consumption, etc., compared to a hard disk or the like.

(Host bridge part)
FIG. 2 is a block diagram illustrating an example of a schematic configuration of the host bridge unit. The host bridge unit 11 is connected to the host device 2 and receives a request from the host device 2. The host I / F (interface) unit 110, packet encoders 111, 8B10B encoders 112, ECC, It includes an encoder 113 and a transmitter 114, and a receiver 115, an ECC decoder 116, an 8B10B decoder 117, and a packet decoder 118 that are provided in order in the upstream direction.

  The host bridge unit 11 is configured by, for example, an FPGA (Field Programmable Gate Array) that can reconfigure an internal logic circuit by a logic circuit program.

  The packet encoder 111 generates a packet to be transmitted in the downlink direction in response to a request from the host apparatus 2 received via the host I / F unit 110. When the request from the host device 2 is a write request, the packet includes, for example, a header including a write destination address and block data (data string). When the request from the host device 2 is a read request, the packet is composed of, for example, a header including a read destination address and dummy data.

  The 8B10B encoder 112 divides the packet generated by the packet encoder 111 with a predetermined size, and generates a plurality of fixed-length frames. Then, the 8B10B encoder 112 performs an encoding process (DC balance conversion) by 8B10B conversion on each fixed-length frame. In addition to 8B10B, DC balance conversion such as 4B5B conversion and 64B66B conversion may be used.

  The ECC encoder 113 calculates an error correcting code (Error Correcting Code, hereinafter abbreviated as “ECC”) based on the fixed-length frame on which the encoding process has been performed, and adds the ECC to the fixed-length frame to thereby generate the ECC. Generate a frame. As the ECC, for example, various error correction codes such as a Hamming code, a Manchester code, and a Reed-Solomon code can be used.

  The transmitter 114 converts the ECC frame as parallel data into serial data and outputs the serial data to the E / O 14.

  The receiver 115 converts the ECC frame as serial data sent from the O / E 16 into parallel data and outputs the parallel data to the ECC decoder 116.

  The ECC decoder 116 functions as a detection unit that performs error detection / correction processing of a fixed-length frame in an ECC frame based on the ECC in the ECC frame. When the ECC decoder 116 detects an error that cannot be corrected by the error detection / correction process, that is, an error of 2 bits or more, the ECC decoder 116 transmits error frame position information indicating the error position to the packet decoder 118.

  The 8B10B decoder 117 performs a decoding process by 8B10B conversion on the fixed-length frame on which the error detection / correction process has been performed. In addition, the 8B10B decoder functions as a detection unit that detects errors such as the presence of data that is not in the conversion rule of the 8B10B conversion in a fixed-length frame by decoding processing. The error frame position information is transmitted to the packet decoder 118.

  The packet decoder 118 restores one packet from a plurality of fixed-length frames that have been decoded. Further, the packet decoder 118 includes a parity check unit 118a that performs error detection of a plurality of divided data constituting the block data in the packet based on the parity in the packet.

  When the parity check unit 118a receives error frame position information from the ECC decoder 116 or the 8B10B decoder 117, the parity check unit 118a applies parity to the divided data (errored divided data) including the error position indicated by the error frame position information. In addition, error correction is performed using other divided data having no error. The ECC decoder 116 and the 8B10B decoder 117 may not be configured to transmit error frame position information to the packet decoder 118. In this case, the parity check unit 118a only performs error detection on the divided data.

(Memory controller)
FIG. 3 is a block diagram illustrating an example of a schematic configuration of the memory controller. The first memory controller 12A includes a memory I / F unit 120 connected to the first memory 13A, a packet encoder 121, an 8B10B encoder 122, an ECC encoder 123, and a transmitter 124 that are sequentially provided in the upstream direction. A receiver 125, an ECC decoder 126, an 8B10B decoder 127, and a packet decoder 128 are provided in order in the direction.

  Here, since the first to fifth memory controllers 12A to 12E have the same configuration, the first memory controller 12A will be described. The packet encoder 121, 8B10B encoder 122, ECC encoder 123, transmitter 124, receiver 125, ECC decoder 126, 8B10B decoder 127, and packet decoder 128 included in the first memory controller 12A are packet encoders 111 included in the host bridge unit 11. , 8B10B encoder 112, ECC encoder 113, transmitter 114, receiver 115, ECC decoder 116, 8B10B decoder 117, and packet decoder 118 have the same basic functions, and differences between them will be described.

  When receiving a write request packet, the packet decoder 128 extracts a write destination address and block data from the packet. The packet decoder 128 calculates a parity for each block data based on the block data and a write data determination unit 128a that determines data to be written to the first memory 13A connected to the first memory controller 12A. And a parity calculation unit 128b.

  For example, the write data determination unit 128a determines whether to write the parity calculated by the parity calculation unit 128b or the block data based on the write destination address (address information).

  Specifically, the write data determination unit 128a calculates a remainder when the write destination address is divided by the total number of memories 13A to 13E included in the storage device 1, and when the remainder matches the own controller number, It is determined that the parity is written in the first memory 13A, and when it does not match, it is determined that the block data is written. Here, “0” to “4” are assigned to the first to fifth memory controllers 12A to 12E as the controller numbers. The write data determination unit 128a uses, for example, the current time as information serving as a common reference in the first to fifth memory controllers 12A to 12E, instead of using the write destination address when determining the write target. The random number generated by the host bridge unit 11 may be added to the packet, and the random number may be used. At that time, information that can identify whether the data is parity or block data is stored together.

  When the write data determination unit 128a determines to write block data, the write data determination unit 128a uses a plurality of divided data obtained by dividing the block data by a data distribution number obtained by subtracting 1 from the total number of memories (here, “4”). It is determined that one piece of data is selected and the selected divided data is written to the first memory 13A.

  Then, the packet decoder 128 sends the parity calculated by the parity calculation unit 128b or the divided data selected by the write data determination unit 128a to the memory I / F unit 120 together with the write destination address. When the packet decoder 128 receives a read request packet, the packet decoder 128 extracts a read destination address from the packet and sends the read destination address to the memory I / F unit 120.

  When either the divided data or the parity is sent from the packet decoder 128, the memory I / F unit 120 writes either the divided data or the parity to the write destination address of the first memory 13A. In addition, when a read destination address is sent from the packet decoder 128, the memory I / F unit 120 reads data stored in the read destination address from the first memory 13A, and reads the read data to the packet encoder. 121.

  As described above, since the parity calculation unit 128b calculates the parity without reading the parity and the divided data stored in the memories 13A to 13E, for example, the reading process is omitted as compared with the case of using RAID5 or the like. As a result, the writing speed becomes faster. The host bridge unit 11 and the memory controller 12 may omit the ECC encoder and the ECC decoder when the error detection / correction processing by ECC is not performed. When the 8B10B conversion is not performed, the host bridge unit 11 and the memory controller 12 The 8B10B decoder may be omitted.

(Operation of the first embodiment)
Next, an example of the overall operation of the storage system 100 will be described separately for a data write operation and a read operation.

(1) Data Write Operation An example of a data write operation will be described with reference to FIGS.

  FIG. 4 is a diagram illustrating an example of a framing flow in the host bridge unit. First, when the packet encoder 111 of the host bridge unit 11 receives a write request from the host apparatus 2 together with a write destination address and write data via the host I / F unit 110, the packet encoder 111 generates a packet corresponding to the write request.

  Specifically, the packet encoder 111 divides the write data, for example, in units of 512 bytes, and generates a plurality of block data 200b. Then, the packet encoder 111 adds an 8-byte header 200a including a write destination address to each block data, and generates a 520-byte packet 200 as shown in FIG. Note that four data when one block data 200b is divided by the number of data distributions is the divided data 200c.

Next, the 8B10B encoder 112 divides the 520-byte packet 200 in units of 40 bytes (320 bits), and generates 13 fixed-length frames 201 of 40 bytes as shown in FIG. 4B. Then, the 8B10B encoder 112 performs an encoding process by 8B10B conversion on each fixed-length frame 201, and as shown in FIG.
A 400-bit fixed-length frame 202 encoded with 8B10B is generated.

  Next, the ECC encoder 113 calculates a 20-bit ECC 203a based on the 400-bit fixed length frame 202. Then, the ECC encoder 113 adds the calculated 20-bit ECC 203a to the 400-bit fixed-length frame 202, and generates a 420-bit ECC frame 203 as shown in FIG.

  Then, the ECC encoder 113 divides the 420-bit ECC frame 203 into, for example, every 20 bits and sequentially sends them to the transmitter 114. The transmitter 114 performs parallel / serial conversion every 20 bits, and after the conversion, Serial data is output to the E / O 14.

  Next, the E / O 14 converts the serial data from the transmitter 114 into an optical signal, and the converted optical signal is sent to the optical branching unit 151 via the optical fiber 150A. Branch in the direction.

  The optical signals branched by the optical branching unit 151 are converted into electrical signals by the O / Es 16A to 16E via the optical fiber 150B, and serial data is sent to the receivers 125 of the first to fifth memory controllers 12A to 12E. Sent as. Note that the subsequent processing is executed in parallel by each unit included in each of the first to fifth memory controllers 12A to 12E.

  The receiver 125 performs serial / parallel conversion on the serial data every 20 bits, and outputs the converted parallel data to the ECC decoder 126.

  Next, when the ECC decoder 126 receives the 20-bit parallel data, the ECC decoder 126 collects the data for 21 cycles into 420 bits, which is used as one ECC frame 203. Here, an example of processing by each of the memory controllers 12A to 12E will be described with reference to the flowchart of FIG.

  FIG. 5 is a flowchart showing an example of the operation of the memory controller. First, the ECC decoder 126 performs an error detection process on the fixed frame of the packet based on the ECC in the ECC frame 203 (S1). As a result, when detecting an error of 2 bits or more (S2: 2 bits or more), the ECC decoder 126 ends the error and requests, for example, the host bridge unit 11 to retransmit the data. On the other hand, when the ECC decoder 126 detects a 1-bit error (S2: 1 bit), it performs error correction processing (S3).

  Then, the ECC decoder 126 removes the ECC from the ECC frame 203 after the error correction process, and generates a 40-bit fixed length frame 202. When no error is detected (S2: 0 bit), the ECC decoder 126 generates a 400-bit fixed-length frame 202 from the ECC frame 203.

  Next, the 8B10B decoder 127 performs a decoding process by 10B8B conversion on the 400-bit fixed-length frame 202 to generate a 40-byte (320-bit) fixed-length frame 201 (S10).

  Next, when the packet decoder 128 sequentially receives the 13 fixed-length frames 201 of 40 bytes, the packet decoder 128 restores the packet 200 of 520 bytes from the 13 fixed-length frames 201. The packet decoder 128 analyzes the header in the packet 200 and determines whether the packet 200 is a write request packet or a read request packet (S20).

  When the packet 200 is a write request packet (S20: write), the write data determination unit 128a refers to the write destination address in the header, and the remainder when the write destination address is divided by the total number of memories. Is calculated. Then, the write data determination unit 128a determines whether or not the remainder matches the own controller number (S30).

  If the write data determination unit 128a determines that the remainder matches the controller number of its own (S30: Yes), it sends an instruction to the parity calculation unit 128b to calculate the parity. When receiving the instruction, the parity calculation unit 128b calculates the parity based on the block data in the packet (S31).

  When the packet decoder 128 sends the parity calculated by the parity calculation unit 128b to the memory I / F unit 120, the memory I / F unit 120 writes the parity to the write destination address of the memory 13A (S32).

  On the other hand, when the write data determination unit 128a determines that the remainder does not match the own controller number (S30: No), one of the four divided data obtained by dividing the block data by the data distribution number is divided. Data is selected as a write target (S40).

  Then, when the packet decoder 128 sends the divided data selected by the write data determining unit 128a to the memory I / F unit 120, the memory I / F unit 120 writes the divided data into the memory 13A (S50).

(Data flow in write operation)
FIG. 6 is a diagram illustrating an example of a data flow between the host bridge unit and each memory controller in a data write operation. Here, when the write data D from the host device 2 is assumed, the data when the write data D is divided in units of 512 bytes is represented as block data D0 to D2, and each block data D0 to D2 is represented by a data distribution number (here, , “4”), the divided data is represented as divided data D01 to D04, D11 to D14, and D21 to D24.

  The host bridge unit 11 divides the write data D into three block data D0 to D2, and frames the divided data D01 to D04, D10 to D14, and D20 to D24 constituting the block data D0 to D2. It transmits to the optical branch transmission line 15 via / O14.

  Next, the divided data D01 to D04, D10 to D14, and D20 to D24 are serially transmitted as optical signals to the optical branch transmission path 15.

  The optical signals are received as block data D0 to D2 by the first to fifth memory controllers 12A to 12E via the O / Es 16A to 16E, respectively.

  Each of the first to fifth memory controllers 12A to 12E calculates a parity when the remainder when the write destination address of each block data D0 to D3 is divided by the total number of memories coincides with its own controller number, The calculated parity is written, and when the data does not match, one divided data is selected and the selected divided data is written.

  For example, when the write destination address of the block data D0 is “0x0005”, the remainder when the write destination address “0x0005” is divided by the total number of memories “5” is “0”. Accordingly, the first memory controller 12A with the controller number “0” calculates the parity P0 based on the divided data D01 to D04, and writes the parity P0 in the first memory 13A.

  The second to fifth memory controllers 12B to 12E subtract the own controller number from the write destination address “0x0005”, and calculate a remainder when the subtracted value is divided by the total number of memories “5”. Then, the second to fifth memory controllers 12B to 12E select the divided data corresponding to the remainder as a writing target.

  For example, in the second memory controller 12B with the controller number “1”, the subtraction value “0x0004” obtained by subtracting the controller number “1” from the write destination address “0x0005” is divided by the total memory number “5”. Is calculated as “4”. Then, the second memory controller 12B selects the “4” -th divided data D04 from the divided data D01 to D04 as the divided data corresponding to the remainder “4”, and uses the divided data D04 as the second divided data D04. Write to memory 13B. Similarly, the third to fifth memory controllers 12C to 12E select the divided data D03, D02, and D01, respectively, and write them to the third to fifth memories 13C to 13E, respectively.

(2) Data Read Operation An example of the data read operation will be described with reference to FIG.

  First, when the packet encoder 111 of the host bridge unit 11 receives a read request from the host device 2 together with a read destination address via the host I / F unit 110, the packet encoder 111 generates a packet corresponding to the read request.

  Next, the generated packet is encoded as an optical signal from the E / O 14 via the transmitter 114 as an ECC frame to which the ECC is added by the ECC encoder 113 after the encoding process by the 8B10B encoder 112, similarly to the writing operation. It is transmitted to the branch transmission line 15.

  Next, the optical signal is branched by the optical branch transmission line 15 and converted into electrical signals by the O / Es 16A to 16E, and then received by the receivers 125 of the first to fifth memory controllers 12A to 12E. The receiver 125 performs serial / parallel conversion, and the ECC decoder 126 receives it as an ECC frame.

  The ECC frame is subjected to error detection / correction processing (S1 to S3) by the ECC decoder 126 and decoding processing (S10) by the 8B10B decoder 127, and is restored as a packet by the packet decoder 128, as in the write operation. It is determined whether the packet is a write request packet or a read request packet (S20).

  If the packet is determined to be a read request packet (S20: Read), the packet decoder 128 sends the read destination address in the packet to the memory I / F unit 120, and the memory I / F unit 120 Reads either the divided data or the parity corresponding to the read destination address from the first memory 13A (S60).

  Next, the read divided data or parity is sent to the E / O 14A as an ECC frame via the packet encoder 121, 8B10B encoder 122, ECC encoder 123, and transmitter 124, and an optical multiplexing transmission path as an optical signal from the E / O 14A. 17 is transmitted.

  Next, the optical signal is multiplexed by the optical multiplexing unit 171 of the optical multiplexing transmission line 17, converted into an electric signal by the O / E 16, received by the receiver 115 of the host bridge unit 11, and serially received by the receiver 115. / Parallel conversion is performed, and the ECC decoder 116 receives it as an ECC frame.

  Next, the ECC decoder 116 performs error detection / correction processing of the ECC frame based on the ECC in the ECC frame, and when an uncorrectable error is detected at that time, an error frame indicating the error position is detected. The position information is transmitted to the packet decoder 118. Then, the ECC decoder 116 sends a fixed-length frame obtained by removing the ECC from the ECC frame to the 8B10B decoder 117.

  Next, the 8B10B decoder 117 performs decoding processing by 10B8B conversion on the fixed-length frame and, when an error is detected in the decoding processing, transmits error frame position information indicating the error position to the packet decoder 118. . Then, the 8B10B decoder 117 sends the fixed-length frame after the decoding process to the packet decoder 118.

  Then, the packet decoder 118 restores a packet from a plurality of fixed-length frames, and extracts four divided data and parity from the packet.

  Next, when receiving the error frame position information from the ECC decoder 116 or the 8B10B decoder 117, the parity check unit 118a counts the number of divided data having an error from the error frame position information. In the case where error frame position information has not been received, processing is performed in the same manner as in the case where the number of divided data with errors is “0”.

  When the number of divided data with errors is “0”, the parity check unit 118a performs error detection of the four divided data extracted based on the parity extracted from the packet. As a result, if no error is detected, the parity check unit 118a sends block data consisting of four divided data to the host I / F unit 110 as it is. If an error is detected, an error is detected by parity check. An error notification indicating that has been detected is sent to the host I / F unit 110.

  When the number of divided data with errors is “1”, the parity check unit 118a performs error correction of the divided data with errors using the parity and the divided data without errors in the packet, and the error Block data composed of the four divided data after correction is sent to the host I / F unit 110.

  When the number of divided data with errors is “2” or more, the parity check unit 118a sends an error notification indicating that an error has been detected by ECC or 8B10B decoding processing to the host I / F unit 110.

  When the host I / F unit 110 receives block data from the parity check unit 118a, the host I / F unit 110 transmits the block data to the host device 2 via the cable 101 as read data. When the host I / F unit 110 receives an error notification from the parity check unit 118 a, the host I / F unit 110 sends the error notification to the host device 2.

(Data flow in read operation)
FIG. 7 is a diagram illustrating an example of a data flow between each memory controller and the host bridge unit in a data read operation. Here, assuming that the read data D is divided, the data when the read data D is divided in units of 512 bytes is expressed as block data D0 to D2, and each block data D0 to D2 is divided into the number of data distributions (here, four). The data in this case is expressed as divided data D01 to D04, D11 to D14, and D21 to D24.

  The first to fifth memory controllers 12A to 12E read data corresponding to the read destination address specified by the read request packet from the first to fifth memories 13A to 13E, respectively.

  For example, when the read destination address is “0x0005”, the first memory controller 12A reads the parity P0, and the second to fifth memory controllers 12B to 12E read the divided data D04 to D01, respectively.

  Then, the first to fifth memory controllers 12A to 12E frame the read parity P0 and the divided data D01 to D04 and transmit them to the optical multiplexing transmission line 17 via the E / Os 14A to 14E. At this time, the five optical signals from the E / Os 14A to 14E are time-division multiplexed in the optical multiplexing transmission line 17.

  Next, the parity P0 and the divided data D01 to D04 are serially transmitted as optical signals to the optical multiplexing transmission path 17, and the optical signals are received by the host bridge unit 11 via the O / E 16.

  Next, the parity check unit 118a of the host bridge unit 11 detects an error as a result of performing error detection of the divided data D01 to D04 based on the parity P0, and the divided data having an error is specified by the error frame position information. If so, error correction of the divided data is performed. Then, the host bridge unit 11 generates block data D0 from the divided data D01 to D04, sequentially generates block data D1 and D2, and reads the read data D including the block data D0 to D2 to the host device 2. send.

[Second Embodiment]
FIG. 8 is a block diagram showing an example of a schematic configuration of the storage system according to the second embodiment of the present invention. The storage system 100 is configured by connecting the storage device 1 to the host device 2 as in the first embodiment.

  Compared with the first embodiment, the storage device 1 according to the present embodiment has first to fifth power supply provided independently for each of the first to fifth power supply ranges 180A to 180E. The point provided with the parts 18A-18E differs, and others are comprised similarly.

  The first to fifth power supply units 18A to 18E supply drive voltages to the respective units included in the first and fifth power supply ranges 180A to 180E connected to the first to fifth power supply units 18A to 18E. For example, the first power supply unit 18A supplies a drive voltage to the first memory controller 12A, the first memory 13A, the E / O 14A, and the O / E 16A included in the first power supply range 180A.

  When an abnormality occurs in any of the first to fifth power supply units 18A to 18E, the host bridge unit 11 cannot read data from the memory connected to the power supply unit in which the abnormality has occurred. Therefore, the data is restored based on the data read from the other memory.

[Other embodiments]
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, in each of the above embodiments, the number of memory controllers and memories is five, but it is sufficient that the parity and data can be distributed and stored, and the number is not limited to five as long as it is three or more.

  In each of the above embodiments, each of the memory controllers selects either parity or data and writes it to the memory. However, one memory controller writes the parity in a fixed manner, and the other memory controller writes the data. You may do it.

  In each of the above embodiments, the host bridge unit and the memory controller are connected by separate optical transmission paths in the downlink direction and the uplink direction, but one optical transmission path is transmitted in the downlink and uplink directions. Or may be connected by an electric transmission line in the upstream direction.

  In each of the above-described embodiments, time division multiplexing is performed on a plurality of optical signals in the optical multiplexing transmission line for transmission, but other multiplexing methods such as wavelength division multiplexing may be applied.

FIG. 1 is a block diagram showing an example of a schematic configuration of a storage system according to the first embodiment of the present invention. FIG. 2 is a block diagram illustrating an example of a schematic configuration of the host bridge unit. FIG. 3 is a block diagram illustrating an example of a schematic configuration of the memory controller. FIG. 4 is a diagram illustrating an example of a framing flow in the host bridge unit. FIG. 5 is a flowchart showing an example of the operation of the memory controller. FIG. 6 is a diagram illustrating an example of a data flow between the host bridge unit and each memory controller in a data write operation. FIG. 7 is a diagram illustrating an example of a data flow between each memory controller and the host bridge unit in a data read operation. FIG. 8 is a block diagram showing an example of a schematic configuration of the storage system according to the second embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory | storage device, 2 ... Host apparatus, 11 ... Host bridge part, 12A-12E ... Memory controller, 13A-13E ... Memory, 14, 14A-14E ... E / O, 15 ... Optical branching transmission path, 16, 16A- 164E ... O / E, 17 ... Optical multiplexing transmission line, 18A to 18E ... Power supply unit, 100 ... Storage system, 101 ... Cable, 110 ... Host I / F unit, 111 ... Packet encoder, 112 ... 8B10B encoder, 113 ... ECC encoder 114 ... transmitter 115 ... receiver 116 ... ECC decoder 117 ... 8B10B decoder 118 ... packet decoder 118a ... parity check unit 120 ... memory I / F unit 121 ... packet encoder 122 ... 8B10B encoder 123 ... ECC encoder, 124 ... Transformer , 125 ... receiver, 126 ... ECC decoder, 127 ... 8B10B decoder, 128 ... packet decoder, 128a ... write data determination unit, 128b ... parity calculation unit, 150A, 150B ... optical fiber, 151 ... optical branching unit, 170A, 170B: Optical fiber, 171: Optical multiplexing unit, 180A to 180E ... Power supply range, 200 ... Packet, 200a ... Header, 200b ... Block data, 200c ... Divided data, 201, 202 ... Fixed length frame, 203 ... ECC frame, 203a ... ECC

Claims (7)

A first control unit that transmits and receives data to and from a host device;
A plurality of second control units connected to the first control unit via an optical transmission line capable of batch transmission of data in the downstream direction from the first control unit;
A plurality of storage units each connected to the plurality of second control units and storing the data;
The first control unit divides data received from the host device into data strings, and transmits the data strings to the plurality of second control units via the optical transmission path,
The plurality of second control units, when receiving the data sequence collectively transmitted from the first control unit, calculate a parity information based on the data sequence, and at least one second control unit A control unit that determines whether to write parity information to the storage unit for each data string so that the control unit writes the parity information to the corresponding storage unit. When it is determined to write to the storage unit, the parity information calculated by the parity calculation unit is written to the corresponding storage unit, and when the parity information is not determined to be written to the storage unit by the determination unit, A storage device that writes a data string to the corresponding storage unit. 2. The determination unit according to claim 1, wherein, based on information included in the data sequence, the determination unit determines for each data sequence such that at least one second control unit writes the parity information in the corresponding storage unit. Storage device. 2. The determination unit according to claim 1, wherein the determination unit determines , based on address information specified as a writing destination of the data string, for each data string such that at least one second control unit writes the parity information . Storage device.   When the first control unit receives the parity information and the data sequence stored in the plurality of storage units from the plurality of second control units, the error detection of the data sequence is performed using the parity information. The storage device according to claim 1, wherein:   The first control unit includes a detecting unit that detects erroneous divided data among the plurality of divided data, and when the detecting unit detects the erroneous divided data, the parity information and The storage device according to claim 1, wherein error correction is performed on the divided data having an error using divided data having no error.   2. The apparatus according to claim 1, further comprising a plurality of power supply units that respectively supply power by pairing the plurality of storage units and the plurality of second control units respectively connected to the plurality of storage units. Storage device. A host device;
A first control unit that transmits / receives data to / from the host device, and is connected to the first control unit via an optical transmission line capable of batch transmission of data from the first control unit in the downstream direction. A plurality of second control units, and a plurality of storage units connected to the plurality of second control units and storing the data,
The first control unit divides data received from the host device into data strings, and transmits the data strings to the plurality of second control units via the optical transmission path,
The plurality of second control units, when receiving the data sequence collectively transmitted from the first control unit, calculate a parity information based on the data sequence, and at least one second control unit A control unit that determines whether to write parity information to the storage unit for each data string so that the control unit writes the parity information to the corresponding storage unit. When it is determined to write to the storage unit, the parity information calculated by the parity calculation unit is written to the corresponding storage unit, and when the parity information is not determined to be written to the storage unit by the determination unit, A storage system comprising: a storage device that writes a data string to the corresponding storage units.

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