JP5228355B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device in which a gate electrode is formed on a semiconductor region via a gate insulating film, and a method for manufacturing the same.

  In recent years, in a MOS type semiconductor device, there is a concern about the increase in resistance of a polycrystalline silicon gate and the decrease in driving current due to the generation of a depletion layer as miniaturization progresses. As means for solving these problems, attempts have been made to form the gate electrode from metal. However, when this metal gate is introduced into a normal semiconductor process, various defect levels are generated when the metal material itself enters a semiconductor other than the desired location. For this reason, it is not easy to introduce into existing semiconductor processes.

  In view of this, a silicide gate has been developed in which a polycrystalline silicon layer is covered with a metal such as Ni or Co and heat-treated to react the polycrystalline silicon with the metal. This silicide gate has a lower resistance than the polycrystalline silicon gate, and can be formed using the polycrystalline silicon layer used in the conventional polycrystalline silicon gate, and introduced into the existing semiconductor process with some process changes. There is an advantage that it is easy to do.

  Furthermore, as the integrated circuit becomes finer, the gate electrode length becomes shorter. When the gate electrode length is, for example, 0.5 μm or less, it is difficult to obtain a sufficiently low resistance value with a normal silicide gate. For this reason, full silicidation has been proposed in which when the polycrystalline silicon layer is silicided, the entire polycrystalline silicon layer is silicided (see, for example, Non-Patent Document 1). By forming the entire gate electrode from silicide, the gate resistance can be reduced, and a depletion layer that may be generated in the polycrystalline silicon layer can be prevented, and the transistor characteristics are improved. .

  Furthermore, Patent Document 1 discloses a technique for increasing the content of Ni, which is a silicide metal, to a predetermined value range in order to expand the work function control range for the gate electrode to which the above-described full silicidation is applied. ing.

JP 2005-129551 A J Kedzierski et.al IEDM2002 p.247

However, even if the Ni content is increased as in Patent Document 1, for example, a sufficiently wide work function control range cannot be obtained yet, and thus a wide range control of the threshold voltage (V _th ) of the gate electrode is realized. It ’s hard to say. Specifically, it has been found that even if a large amount of Ni exceeding 1 × 10 ²¹ / cm ³ is introduced into the interface of the silicide gate with the gate insulating film, the control range of V _th is still not sufficient. ing.

The present invention has been made in view of the above problems, and it is easy and easy to employ a gate electrode made of a metal semiconductor compound to reduce resistance sufficiently, without adding a troublesome configuration and manufacturing process. An object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same, which can reliably control a sufficiently wide range of the threshold voltage (V _th ) of the gate electrode.

The semiconductor device of the present invention includes a semiconductor region and a gate electrode formed on the semiconductor region via a gate insulating film, and the gate electrode is a metal semiconductor formed by a chemical reaction between a semiconductor and a refractory metal. It consists compound, carbon, an additional element is at least one kind selected from nitrogen and oxygen, see containing 10 to 20% by weight, the additive element to the interface site the interface between the gate insulating film More segregation than other parts .

The method for manufacturing a semiconductor device of the present invention includes 10 wt% or more and 20 wt% or less of an additive element that is at least one selected from carbon, nitrogen, and oxygen via a gate insulating film on a semiconductor region. Forming an electrode-shaped semiconductor layer; forming a refractory metal film on the semiconductor layer; and heat-treating the semiconductor layer into a metal-semiconductor compound to form the additive element at an interface with the gate insulating film Forming a gate electrode that segregates more than a part other than the interface part .
The method for manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film on a semiconductor substrate, and an additive element that is at least one selected from carbon, nitrogen, and oxygen on the gate insulating film. A step of forming a semiconductor layer including 20% by weight or less by weight, a step of forming a protective film on the semiconductor layer, a step of patterning the protective film, the semiconductor layer, and the gate insulating film; Using the protective film, the semiconductor layer, and the gate insulating film as a mask, implanting impurities into the semiconductor substrate to form a source region and a drain region; and after the impurity implantation, the protective film, the source region And forming an insulating film covering the drain region, polishing the insulating film and exposing the protective film,
Removing the protective film and exposing the semiconductor layer; and forming a metal film on the insulating film and the semiconductor layer and forming the semiconductor layer into a metal semiconductor compound by heat treatment.

According to the present invention, a gate electrode made of a metal semiconductor compound is used to achieve a sufficiently low resistance, but the threshold voltage (V _{th) of the} gate electrode can be easily and reliably added without adding a complicated configuration and manufacturing process. ), A highly reliable semiconductor device capable of sufficiently wide range control is realized.

-Basic outline of the present invention-
In the present invention, in a so-called MIS (Metal Insulator Semiconductor) type semiconductor device, the gate electrode is formed from a metal semiconductor compound formed by a chemical reaction between a semiconductor and a refractory metal, and has a larger band gap than the channel portion of the semiconductor region. The semiconductor layer is formed as a metal semiconductor compound. Here, as a specific configuration for obtaining the band gap, a semiconductor layer in which an additive element which is at least one selected from carbon, nitrogen, and oxygen is introduced before forming a metal semiconductor compound is used. Form.

By introducing the above additive into the semiconductor layer that is the gate electrode material before forming the metal semiconductor compound, the band gap of the semiconductor layer itself is expanded. Thereby, a band edge spreads compared with a semiconductor region. Then, by forming the semiconductor layer into a metal semiconductor compound, the variable range of the work function of the metal semiconductor compound is widened, and the threshold voltage (V _th ) can be greatly changed.

Specifically, when silicon (for example, a silicon substrate) is used for the semiconductor region and polycrystalline silicon is used for the gate electrode material, the polycrystalline silicon film is added with at least one selected from carbon, nitrogen, and oxygen After forming the semiconductor layer so as to contain an element, a refractory metal film of Ni, Co, Pd, Pt or the like is laminated on the semiconductor layer and heat-treated to form a gate electrode. Here, as another example of the semiconductor region, germanium (eg, a germanium substrate) is used. In this case, a germanium film (containing silicon or the like (Ge _x Si _1-x , 0 <x ≦ 1 etc.)) may be formed to contain the above-described additive elements to form a semiconductor layer. Thereafter, a refractory metal film of Ni, Co or the like is laminated on the semiconductor layer, and the semiconductor layer is germanide by heat treatment to form a gate electrode.

Hereinafter, a case where silicon is used for the semiconductor region and the gate electrode is formed by siliciding the semiconductor layer will be described in detail.
FIG. 1 shows the results of examining the relationship between the C ratio (C / Si: wt%) and the band gap (Eg: eV) in a semiconductor layer containing carbon (C) in silicon.
Here, an amorphous semiconductor film is formed by a plasma CVD method (P-CVD method). By forming the semiconductor film in an amorphous state, later silicidation is facilitated. The film formation conditions are as follows: the film formation temperature is 300 ° C., the pressure is 0.3 torr (40 Pa), the input power is 20 W, a mixed gas of CH ₄ and SiH ₄ is used as the source gas, and CH ₄ / SiH ₄ = 0. It was changed to -0.7. As a result, it was confirmed that by adding about 20 wt% of C to silicon, Eg changed to 2 eV or more together with the conduction band (Ec) and the valence band (Ev).

Similarly, FIG. 2 shows the results of examining the relationship between the N ratio (N / Si: wt%) and the band gap (Eg: eV) in a semiconductor layer containing nitrogen (N) in silicon. .
Here, an amorphous semiconductor film is formed by a plasma CVD method (P-CVD method). By forming the semiconductor film in an amorphous state, later silicidation is facilitated. The film formation conditions are as follows: the film formation temperature is 300 ° C., the pressure is 0.3 torr (40 Pa), the input power is 20 W, a mixed gas of NH ₃ and SiH ₄ is used as the source gas, and NH ₃ / SiH ₄ = 0. Changed to ~ 1.0. As a result, it was confirmed that Eg changed to 1.9 eV or more together with Ec and Ev by adding about 20 wt% of N to silicon.

  Thereafter, a Ni film, for example, is formed on the semiconductor layer, and silicided by heat treatment to form a gate electrode. In order to perform the silicidation surely and to achieve full silicidation, the amount of additive must be 20% or less for both C and N. In the gate electrode formed by the method of the present invention, Eg before silicidation is expanded to about 1.6 <Eg ≦ 2.0. Here, the addition amount is 0 when the lower limit is 1.6, and is about 20% when the upper limit is 2.0. The gate electrode is polycrystallized by, for example, an annealing process at the time of impurity activation of the source / drain, and has a state of Eg of about 1.6 <Eg ≦ 2.0, and about 1.1 <Eg ≦ 1.5. Become. Accordingly, in the present invention, an appropriate range of Eg in the gate electrode after polycrystallization and before full silicidation is about 1.1 <Eg ≦ 1.5.

Then, C (gate electrode capacity: × 10 ⁻¹¹ f) −V (gate voltage: V) characteristics when an n-type impurity such as phosphorus (P) is introduced into the gate electrode formed by adding N to silicon. Was examined based on a comparison with a conventional gate electrode to which N was not added. The result is shown in FIG.

Here, as a gate electrode of the present invention, 10 wt% of N was added to silicon (Si _0.9 N _0.1 ), and a semiconductor layer formed by ion implantation of P was silicided. As for the silicidation conditions, a rapid annealing process (RTA) was performed at 400 ° C. using a Ni film to form a fully silicided gate electrode having a thickness of about 130 nm. On the other hand, as a gate electrode of the comparative example, a semiconductor layer obtained by ion implantation of P into silicon was silicided under the same conditions as described above.
As shown in the figure, it can be seen that the CV curve is shifted to the left in the gate electrode of the present invention than in the gate electrode of the comparative example. This means that the work function control range of the MOS semiconductor device having the gate electrode of the present invention is larger than that of the comparative example.

-Specific embodiment to which the present invention is applied-
Hereinafter, specific embodiments in which the present invention is applied to CMOS transistors will be described in detail with reference to the drawings. In this embodiment, for convenience of explanation, the configuration of the CMOS transistor is described together with its manufacturing method.
FIG. 4 is a schematic cross-sectional view showing the method of manufacturing the CMOS transistor according to the present embodiment in the order of steps.

First, as shown in FIG. 4A, after the STI element isolation structure 2 is formed on the silicon substrate 1, the wells 12 and 22 and the LDD regions 18 and 28 are sequentially formed.
Specifically, first, an element isolation structure in the element isolation region of the silicon substrate 1, here, an STI element isolation structure 2 (insulating material such as silicon oxide in a groove formed in the element isolation structure) by an STI (Shallow Trench Isolation) method. To be embedded). Thereby, an active region 11 (hereinafter referred to as n-type active region 11) for forming an n-type element on the silicon substrate 1 and an active region 21 (hereinafter referred to as p-type active region 21) for forming a p-type element are formed. .) Are defined.

Next, the p-type active region 21 is covered with a resist, and a p-type impurity such as boron (B) is introduced into the n-type active region 11 by ion implantation using the resist as a mask. This ion implantation is performed for well formation and channel region formation (threshold control). First, after deep introduction, for example, acceleration energy is about 10 keV so as to be shallower and higher in concentration. Ions are implanted under the condition that the dose is about 1 × 10 ¹³ / cm ² .

Next, after removing the resist by ashing or the like, the n-type active region 11 is covered with a resist, and an n-type impurity such as phosphorus (P) is introduced into the p-type active region 21 by ion implantation using the resist as a mask. . Similarly, this ion implantation is performed for well formation and channel region formation (threshold control). First, after deep introduction, for example, acceleration energy is 50 keV so as to be shallower and higher in concentration. The ion implantation is performed under the condition that the dose is about 1 × 10 ¹³ / cm ² . The resist is removed by ashing or the like.
Further, the impurities are activated by heat treatment. Thereby, a p-well 12 and an n-well 22 (channel region not shown) are formed.

Subsequently, as shown in FIG. 4B, gate insulating films 13 and 23, semiconductor layers 14a and 24a, and a protective film 20 are sequentially formed, and ion implantation of the LDD regions 18 and 28 is performed.
Specifically, first, an insulating film, here a silicon oxide film, is formed in the n-type active region 11 and the p-type active region 21 by a CVD method to a film thickness of about 2 nm, for example.

Next, by using a mixed gas of CH ₄ and SiH ₄ as a source gas by a P-CVD method, C is contained in amorphous silicon so as to contain, for example, about 20 wt% (C / Si≈0.2). The contained amorphous silicon film (hereinafter referred to as C-containing a-Si film) is deposited to a thickness of about 100 nm, for example. This C-containing a-Si film is formed at a relatively low temperature, here about 300 ° C.

Note that a PVD method (sputtering method) may be used instead of the P-CVD method. Further, instead of the C-containing a-Si film, an amorphous silicon film containing N or an amorphous silicon film containing O may be formed. In order to form the former, for example, a mixed gas of NH ₃ and SiH ₄ is used as the source gas, and in order to form the latter, for example, a mixed gas of N ₂ O and SiH ₄ is used as the source gas.
Thereafter, an insulating film such as a silicon nitride film is deposited by a CVD method so as to cover the C-containing a-Si film.

  Next, the silicon nitride film, the C-containing a-Si film, and the silicon oxide film are processed into electrode shapes, and the gate insulating films 13 and 23, the semiconductor layers 14a and 24a on the gate insulating films 13 and 23, and the semiconductor layer 14a. , 24a is formed.

Next, a portion corresponding to the p-type active region 21 is covered with a resist, and using the resist and the semiconductor layer 14a as a mask, an n-type impurity, for example, phosphorus (P) is introduced into the n-type active region 11 by using an n-type source / Ions are implanted so as to be shallower and lower in concentration than the drain region 16.
Next, after the resist is removed by ashing or the like, a portion corresponding to the n-type active region 11 is covered with the resist, and a p-type impurity such as boron is added to the p-type active region 21 using the resist and the semiconductor layer 24a as a mask. (B) is ion-implanted so as to be shallower and lower in concentration than a p-type source / drain region 26 described later. The resist is removed by ashing or the like.
In FIG. 4B, the LDD regions 18 and 28 are shown.

Subsequently, as shown in FIG. 4C, sidewalls 15 and 25 and source / drain regions 16 and 26 are sequentially formed.
Specifically, first, the entire surface is covered with an insulating material such as silicon oxide or silicon nitride, and the insulating material is subjected to anisotropic etching (etchback) on the entire surface to form sidewalls on both side surfaces of the semiconductor layers 14a and 24a. 15 and 25 are formed.

A portion corresponding to the p-type active region 21 is covered with a resist, and the resist, the semiconductor layer 14a, and the sidewall 15 are used as a mask. The ion implantation is performed under the condition that the dose is about 7 × 10 ¹⁵ / cm ² . At this time, phosphorus is ion-implanted through the protective film 20 and into the semiconductor layer 14a.
Next, after removing the resist by ashing or the like, a portion corresponding to the n-type active region 11 is covered with the resist, and the p-type active region 21 is p-type using the resist, the semiconductor layer 24a, and the sidewall 25 as a mask. Impurities such as boron (B) are ion-implanted under the conditions of an acceleration energy of about 5 keV and a dose of about 5 × 10 ¹⁵ / cm ² . At this time, boron is ion-implanted through the protective film 20 and into the semiconductor layer 14b. The resist is removed by ashing or the like.

  Then, for example, annealing (RTA) is performed at 1000 ° C. to activate the implanted ions, the n-type active region 11 includes the n-type LDD region 18 and the n-type source / drain region 16, and the p-type active region 21 includes A p-type LDD region 28 and a p-type source / drain region 26 are formed.

Subsequently, as shown in FIG. 5A, a thick insulating film 31 is deposited on the entire surface.
More specifically, an insulating material having a different etching selectivity with respect to the insulating film 31, here the protective film 20, for example, a silicon oxide film is deposited on the entire surface by the CVD method.

Subsequently, as shown in FIG. 5B, the insulating film 31 is planarized.
Specifically, using the protective film 20 as a polishing stopper, the insulating film 31 is polished by a chemical mechanical polishing method (CMP method) until the surface of the protective film 20 is exposed, and the insulating film 31 is planarized.

Subsequently, as shown in FIG. 5B, the protective film 20 is removed.
Specifically, the protective film 20 is removed by wet etching. Here, the wet etching is performed using an etchant capable of selectively etching the protective film 20 which is a silicon nitride film.

Subsequently, as shown in FIG. 6A, a Ni film 3 is formed.
More specifically, a silicide metal, here Ni film 3, is deposited on the entire surface including the n-type active region 11 and the p-type active region 21 to a thickness of about 60 nm, for example, by sputtering.

Subsequently, as shown in FIG. 6B, gate electrodes 14 and 24 that are fully silicided are formed.
More specifically, for example, the semiconductor layers 14a and 24a, here, the entirety thereof are Ni silicided by RTA treatment at about 400 ° C., for example. Thereafter, unreacted Ni is removed. By full silicidation of the semiconductor layers 14a and 24a, gate electrodes 14 and 25 containing C and P or B and made of NiSi are formed.

  Here, in the gate electrodes 14 and 25, C as an additive element is segregated more at the interface portion between the gate electrodes 14 and 25 and the gate insulating films 13 and 23 than at the portion other than the interface portion. The concentration of the additive element at the interface site is particularly important for increasing or decreasing the work function. If the amount of segregation of the additive element at the interface site is greater than that at other sites, a sufficient work function change can be obtained without interfering with silicidation. It is done.

  Thereafter, through a process of forming an interlayer insulating film covering the MOS transistors 17 and 27, wirings electrically connected to the source / drains 16 and 26, and the like, the n-type active region 11 has a p-type MOS transistor 17, A CMOS transistor in which an n-type MOS transistor 18 is provided in the p-type active region 21 is completed.

As described above, according to the present embodiment, a full silicide gate is used to achieve a sufficiently low resistance, but the gate electrode threshold voltage can be easily and reliably added without adding a complicated structure and manufacturing process. A highly reliable CMOS transistor capable of controlling a sufficiently wide range of (V _th ) is realized.

  The conventional CMOS transistor has a drawback that the work function difference between the p-type MOS transistor 17 and the n-type MOS transistor 18 is small, and sufficient drive capability as a transistor cannot be obtained unless the operating voltage is increased more than necessary. On the other hand, in the CMOS transistor of this embodiment, a large work function difference between the p-type MOS transistor 17 and the n-type MOS transistor 18 is ensured, and an operating voltage equivalent to that of the gate electrode of polycrystalline silicon can be obtained. Become.

  In the present embodiment, the gate electrode is exemplified as an object to which the additive element C, N, or O is added. However, the gate electrode may be applied to another structure, for example, a wiring of a semiconductor device. For example, a wiring made of polycrystalline silicon is formed by adding C, N, or O. In this case, since the work function of the wiring can be changed greatly, it is possible to suppress the work function difference at the time of wiring connection between the wiring and the other wiring connected as much as possible. Become.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1) a semiconductor region;
A gate electrode formed on the semiconductor region via a gate insulating film,
The gate electrode is made of a metal semiconductor compound obtained by a chemical reaction between a semiconductor and a refractory metal, and includes an additive element that is at least one selected from carbon, nitrogen, and oxygen. .

  (Supplementary note 2) The supplementary note 1, wherein the gate electrode has a band gap before the chemical reaction within a range of 1.1 (eV) to 1.5 (eV) or less. Semiconductor device.

  (Supplementary note 3) The semiconductor device according to Supplementary note 1 or 2, wherein the gate electrode is segregated more at the interface portion with the gate insulating film than at the portion other than the interface portion. .

  (Appendix 4) The semiconductor device according to any one of appendices 1 to 3, wherein the gate electrode is entirely formed into the metal semiconductor compound.

(Supplementary Note 5) The gate electrode includes a p-type gate electrode formed in a first active region defined in the semiconductor region and an n-type gate formed in a second active region defined in the semiconductor region. With electrodes,
The semiconductor device according to any one of appendices 1 to 4, wherein the p-type gate electrode contains a p-type impurity and the n-type gate electrode contains an n-type impurity.

(Appendix 6) A step of forming an electrode-shaped semiconductor layer containing an additive element which is at least one selected from carbon, nitrogen and oxygen on a semiconductor region via a gate insulating film;
Forming a gate electrode by forming a refractory metal film on the semiconductor layer and heat-treating the semiconductor layer into a metal semiconductor compound.

  (Supplementary note 7) The gate electrode according to Supplementary note 6, wherein the band gap before the heat treatment is set to a value in the range of 1.1 (eV) to 1.5 (eV) or less. A method for manufacturing a semiconductor device.

  (Supplementary note 8) The method for manufacturing a semiconductor device according to supplementary note 6 or 7, wherein the semiconductor layer is formed in an amorphous state.

  (Supplementary note 9) The method for manufacturing a semiconductor device according to any one of supplementary notes 6 to 8, wherein the semiconductor layer is formed by a CVD method or a PVD method so as to contain the additive element.

  (Supplementary note 10) The method for manufacturing a semiconductor device according to any one of supplementary notes 6 to 9, wherein the gate electrode is formed by forming the entire semiconductor layer into the metal semiconductor compound.

(Supplementary Note 11) The gate electrode includes a p-type gate electrode formed in a first active region defined in the semiconductor region and an n-type gate formed in a second active region defined in the semiconductor region. When configuring with electrodes,
After introducing a p-type impurity into the semiconductor layer formed in the first active region and an n-type impurity into the semiconductor layer formed in the second active region,
Both the semiconductor layers are formed into the metal semiconductor compound, and the p-type gate electrode is formed in the first active region, and the n-type gate electrode is formed in the second active region. The method for manufacturing a semiconductor device according to any one of appendices 6 to 10.

It is a characteristic view which shows the relationship between the ratio (C / Si: wt%) of C, and a band gap (Eg: eV) in the semiconductor layer which contains carbon (C) in silicon. It is a characteristic view which shows the relationship between the ratio (N / Si: wt%) of N and the band gap (Eg: eV) in the semiconductor layer which contains nitrogen (N) in silicon. It is a characteristic view shown based on the comparison with the conventional gate electrode which does not add N about the CV characteristic at the time of introduce | transducing an n-type impurity into the said gate electrode formed by adding N to silicon. It is a schematic sectional drawing which shows the manufacturing method of the CMOS transistor by this embodiment in order of a process. FIG. 5 is a schematic cross-sectional view illustrating the method of manufacturing the CMOS transistor according to the present embodiment in order of processes subsequent to FIG. 4. FIG. 6 is a schematic cross-sectional view illustrating the method of manufacturing the CMOS transistor according to the present embodiment in order of processes following FIG. 5.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 STI element isolation structure 11, 21 Active region 12, 22 Well 13, 23 Gate insulating film 14a, 24a Semiconductor layer 14, 24 Gate electrode 15, 25 Side wall 16, 26 Source / drain region 17, 27 MOS transistor 18, 28 LDD region 20 Protective film 31 Insulating film

Claims (7)

A semiconductor region;
A gate electrode formed on the semiconductor region via a gate insulating film,
The gate electrode is made of a metal semiconductor compound obtained by a chemical reaction between a semiconductor and a refractory metal, and contains at least one additive element selected from carbon, nitrogen and oxygen in an amount of 10 wt% to 20 wt%. hereinafter unrealized, the semiconductor device in which the additive element at an interface portion between the gate insulating film is characterized in that it more segregated than sites other than the interface portion.   2. The semiconductor device according to claim 1, wherein the gate electrode has a band gap before the chemical reaction within a range of 1.1 (eV) to 1.5 (eV) or less. . Wherein the gate electrode, the semiconductor device according to claim 1 or 2, characterized in that the whole is formed by the metal-semiconductor compound of. Forming an electrode-shaped semiconductor layer containing 10 wt% or more and 20 wt% or less of an additive element selected from carbon, nitrogen, and oxygen on a semiconductor region via a gate insulating film; ,
A refractory metal film is formed on the semiconductor layer, and the semiconductor layer is converted into a metal semiconductor compound by heat treatment, so that the additive element is segregated more at the interface part with the gate insulating film than at the part other than the interface part. Forming a gate electrode to be manufactured. A method for manufacturing a semiconductor device, comprising: 5. The semiconductor device according to claim 4 , wherein the gate electrode has a band gap before the heat treatment within a range of 1.1 (eV) to 1.5 (eV) or less. Production method. Forming another semiconductor layer having a wiring shape including an additive element which is at least one selected from carbon, nitrogen, and oxygen above the gate electrode;
The refractory metal film is formed on the other semiconductor layer, the other semiconductor layer and a metal-semiconductor compound by a heat treatment, according to claim 4 or 5, further comprising a step of forming a wiring The manufacturing method of the semiconductor device as described in 2. Forming a gate insulating film on the semiconductor substrate;
Forming a semiconductor layer containing 10 wt% or more and 20 wt% or less of an additive element that is at least one selected from carbon, nitrogen, and oxygen on the gate insulating film;
Forming a protective film on the semiconductor layer;
Patterning the protective film, the semiconductor layer, and the gate insulating film;
Using the patterned protective film, the semiconductor layer, and the gate insulating film as a mask to implant impurities into the semiconductor substrate to form a source region and a drain region;
After the impurity implantation, forming an insulating film covering the protective film, the source region and the drain region;
Polishing the insulating film and exposing the protective film;
Removing the protective film to expose the semiconductor layer;
Forming a metal film over the insulating film and the semiconductor layer, and forming the semiconductor layer into a metal semiconductor compound by a heat treatment.

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