JP5228499B2 - Degradation detection circuit and semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a deterioration detection circuit and a semiconductor integrated circuit capable of detecting an electromigration phenomenon.

  With the recent increase in speed of LSIs, the electromigration phenomenon of LSI internal wiring has become a problem. The electromigration phenomenon is a phenomenon in which the electron current flowing through the wiring gradually “pushes” the metal atoms constituting the wiring and causes a defect of metal atoms called voids inside the wiring. The average life of the wiring due to the electromigration phenomenon is expressed by Black's empirical formula and greatly depends on the type of metal atom (wiring material), current density, and temperature.

  Al (aluminum) is the majority of wiring materials in LSI, but wiring degradation due to electromigration phenomenon has become a major problem in the 150nm to 90nm generation of process technology. For this reason, in recent years, the above-described problems have been improved by replacing the wiring material with Al → Cu (copper).

  However, the miniaturization of wiring due to process technology and the increase in the ON current of MOS transistors continue to progress, and the current density in the wiring has increased significantly. In other words, electromigration means that the current density per unit area of wiring increases several times per generation due to the synergistic effect of increasing MOS ON current + reducing wiring cross-sectional area (reducing the area by about half for each generation). The problem of wiring deterioration due to the phenomenon is exacerbated. At present, wiring materials with better performance and cost than Cu have not been discovered, and at least several generations will need to design LSIs using Cu.

  Various inspection methods have been proposed for wiring deterioration due to the electromigration phenomenon.

  For example, as a technical literature filed prior to the present invention, a technique for measuring the electromigration lifetime of a wiring from a change in resistance value by applying a direct current to the wiring in the LSI to be measured from the outside is disclosed. (For example, refer to Patent Document 1).

  Also disclosed is a technology that eliminates defective LSIs by providing pilot wiring for inspection so that the LSI's main functional parts and IO terminals are shared inside the LSI, and selecting the pilot wiring during inspection to perform a burn-in test. There are documents (see, for example, Patent Document 2).

  In addition, a technology that promotes heating by applying direct current and alternating current to the internal wiring itself to be tested, rather than installing a heat source necessary for the accelerated test, so that the accelerated test can be performed only by the test subject Is disclosed (for example, see Patent Document 3).

  Further, there is a document that discloses a technique that enables a heating test by arranging a heating element to which a DC voltage is applied in the vicinity of a test wiring (see, for example, Patent Document 4).

Further, there is a document that discloses a technique that enables an AC stress test by adding a ring oscillator to a wiring to be tested and applying a pulse waveform (see, for example, Patent Document 5).
Japanese Patent Laid-Open No. 4-191684 JP-A-1-238134 JP 2005-536871 A JP 7-201944 A JP-A-6-216212

  However, the above Patent Document 1 does not suggest a detailed mounting method on the LSI. Moreover, the technique of the said patent document 2 is limited to the test before shipment. Patent Documents 3, 4, and 5 are premised on an integrated circuit dedicated for testing or testing, and no consideration is given to a method of applying an actual product to an LSI.

  For this reason, the techniques disclosed in Patent Documents 1 to 5 cannot detect the electromigration deterioration phenomenon in the LSI after shipment.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a deterioration detection circuit and a semiconductor integrated circuit capable of detecting an electromigration deterioration phenomenon in an LSI after shipment, which is the problem described above. It is what.

  In order to achieve this object, the present invention has the following features.

<Deterioration detection circuit>
The deterioration detection circuit according to the present invention is
A deterioration detection circuit that detects wiring deterioration due to electromigration phenomenon,
A frequency multiplication circuit for inputting a clock signal and generating a frequency doubled signal having a frequency twice that of the clock signal;
A frequency dividing circuit for generating a frequency-divided signal having a half frequency of the clock signal;
A test circuit for inputting the frequency-divided signal and detecting wiring deterioration;
And a heater circuit that inputs the frequency-multiplied signal and heats the test circuit.

<Semiconductor integrated circuit>
The semiconductor integrated circuit according to the present invention is
The semiconductor integrated circuit includes N (where N is an integer of 2 or more) deterioration detection circuits described above.

  According to the present invention, it is possible to detect an electromigration deterioration phenomenon in an LSI after shipment.

First, the outline of the semiconductor integrated circuit of this embodiment will be described with reference to FIG.
The semiconductor integrated circuit according to this embodiment is a semiconductor integrated circuit including N (where N is an integer of 2 or more) deterioration detection circuits (1) that detect wiring deterioration due to electromigration.

  The degradation detection circuit (1) receives a clock signal and generates a frequency-multiplied signal having a frequency twice that of the clock signal, and a frequency-dividing circuit having a frequency half that of the clock signal. A frequency divider (11) that generates a signal, a test circuit (17) that receives a frequency-divided signal and detects wiring deterioration, and a heater circuit (16) that inputs a frequency-divided signal and heats the test circuit (17) ).

  Thereby, the heater circuit (16) is self-contained, and the heater circuit (16) can heat the test circuit (17). As a result, it is possible to detect the electromigration deterioration phenomenon in the LSI after shipment. Further, by configuring the heater circuit (16) using a frequency-multiplied signal having a frequency twice that of the clock signal, it is possible to detect the electromigration deterioration phenomenon with a simple and miniaturized configuration. Hereinafter, the semiconductor integrated circuit according to the present embodiment will be described in detail with reference to the accompanying drawings.

<Configuration of semiconductor integrated circuit>
First, the configuration of the semiconductor integrated circuit of this embodiment will be described with reference to FIG.

  The semiconductor integrated circuit according to this embodiment includes a plurality of deterioration detection circuits (1), an exclusive OR circuit (4), and an F / F (6).

  The output signal of each deterioration detection circuit (1) is output to the exclusive OR circuit (4).

  The exclusive logical sum circuit (4) is a comparator that compares output signals of adjacent deterioration detection circuits (1) and outputs the compared signal to the F / F (6). F / F (6) holds a comparison signal and holds a comparison result compared by the exclusive OR circuit (4).

  The F / F (6) is serially connected, and the comparison result held in the F / F (6) is output to the outside of the LSI.

  Each deterioration detection circuit (1) is serially connected and configured to input a clock signal. Each deterioration detection circuit (1) is configured to receive a control signal from outside the LSI.

<Deterioration detection circuit; 1 internal configuration>
Next, the internal configuration of each deterioration detection circuit (1) will be described.
The deterioration detection circuit (1) in this embodiment includes a frequency divider (10), a frequency divider (11), a selector (12), an F / F (13), a buffer (14, 15), A heater circuit (16), a test circuit (17), and an output buffer (18) are included.

  The frequency doubler circuit (10) receives the clock signal, generates a frequency doubled signal having a frequency twice that of the clock signal, and outputs the generated frequency doubled signal to the selector (12).

  The frequency divider (11) receives a clock signal, generates a frequency-divided signal having a half frequency of the clock signal, and uses the generated frequency-divided signal as an input signal to the test circuit (17) as a buffer (15 ).

  The F / F (13) holds a control signal for controlling the selector (12). Although not shown in FIG. 1, a clock signal is input to F / F (13).

  The selector (12) receives the doubled signal, the clock signal, and the GND signal, and based on the control signal input from the F / F (13), the doubled signal, the clock signal, and the GND signal And the selected selection signal is output to the buffer (14) as an input signal of the heater circuit (16).

  The buffer (14) drives the heater circuit (16) based on the selection signal (any one of the frequency-multiplied signal, the clock signal, and the GND signal) input from the selector (12).

  The buffer (15) drives the test circuit (17) based on the frequency-divided signal input from the frequency-dividing circuit (11).

  The heater circuit (16) is a circuit for heating the test circuit (17).

  The test circuit (17) is a circuit for degrading the wiring configuring the test circuit (17) and detecting the deterioration phenomenon of the wiring. The output signal of the test circuit (17) is output to the output buffer (18).

  The output buffer (18) outputs the output signal of the test circuit (17) to the exclusive OR circuit (4).

  The deterioration detection circuit (1) in the present embodiment is provided with a frequency doubler circuit (10), generates a frequency doubled signal having a frequency twice that of the clock signal, and the generated frequency doubled signal is supplied to the heater circuit (16). It is constructed to be used as an input signal. Thereby, the heater circuit (16) is self-contained, and the heater circuit (16) can heat the test circuit (17). As a result, the test circuit (17) can be heated without providing an external heat source. For this reason, in this embodiment, it is possible to detect the deterioration phenomenon of the wiring during the normal operation of the LSI.

  In addition, the deterioration detection circuit (1) in this embodiment inputs a frequency-divided signal having a frequency twice that of the clock signal to the heater circuit (16), and also outputs a frequency-divided signal having a frequency that is half that of the clock signal. It is constructed to input to the test circuit (17). As a result, it is possible to efficiently detect the deterioration phenomenon of the wiring during the normal operation of the LSI.

  A signal having the highest frequency in a general LSI is a clock signal, and a circuit operating at the same frequency as the clock signal or the clock signal in the LSI operates as the highest heat generation source, a so-called hot spot. . The wiring life due to the electromigration phenomenon is expressed by the following Black's empirical formula (Formula 1).

  MTTF∝exp {Ea ÷ (k × T)} × J ^ −n (Expression 1)

  Where MTTF is the average life, Ea is the activation energy, k is the Boltzmann constant, T is the absolute temperature, J is the current density, n is a constant determined by the material, etc. Indicates a child.

  As is clear from Black's empirical formula in (Equation 1), the electromigration phenomenon is a phenomenon accelerated by heat generation, so the vicinity of the hot spot is the region where the wiring degradation is most advanced, and the degradation phenomenon is detected. It can be said that this is a site to be performed.

  Since the deterioration detection circuit (1) of the present embodiment inputs a frequency doubled signal having a frequency twice that of the clock signal to the heater circuit (16), the heater circuit (16) is twice the clock signal. It will operate at a frequency. This makes it possible to use the heater circuit (16) as a heat source that exceeds the hot spot in a normal LSI.

  Further, according to Black's empirical formula (Formula 1), the average life depends on the current density. As a rule of thumb, 2 is used as the coefficient n representing the dependence, and the average life of the wiring is inversely proportional to the square of the current density.

  In the deterioration detection circuit (1) of the present embodiment, a frequency-divided signal having a half frequency of the clock signal is input to the test circuit (17). The general signal inside the LSI is normally driven from the F / F (13). In this case, the frequency of the signal having the highest operating rate, that is, the operating rate of 100% is half the frequency of the clock signal. . Therefore, the deterioration detection circuit (1) of this embodiment can use the worst value inside the LSI as the current density of the test circuit (17).

  In the deterioration detection circuit (1) of the present embodiment, the heater circuit (16) and the test circuit (17) are configured by wiring. For the purpose of detecting deterioration, it is preferable that the wiring constituting the test circuit (17) is the thinnest wiring among the wiring widths used in the LSI in the wiring layer to be tested.

  Note that the wiring life of the electromigration phenomenon is inversely proportional to the square of the current density according to Black's empirical formula in (Equation 1) above, so by adopting thin wiring in the design rule of the process used for LSI manufacturing Therefore, it is possible to construct a wiring model that progresses most rapidly in the LSI.

  On the other hand, for the heater circuit (16), in order to avoid the deterioration of the heater circuit (16) itself during normal LSI operation, a wiring width with a margin against electromigration phenomenon wiring deterioration is adopted. It is preferable to do. When the wiring width is doubled that of the test circuit (16), the wiring life is about four times according to the Black empirical formula (Equation 1). It is preferable that the wiring constituting the heater circuit (16) satisfy the general wiring design rules and be arranged closest to the test circuit (17). As a result, the test circuit (17) can be efficiently heated.

  The deterioration detection circuit (1) of the present embodiment can easily build an accelerated test state inside the LSI by providing the heater circuit (16) and the test circuit (17), and Therefore, it is possible to detect the deterioration phenomenon of the wiring during the normal operation of the LSI.

  In addition, the semiconductor integrated circuit according to the present embodiment includes a plurality of the above-described deterioration detection circuits (1), and compares the output signals of adjacent deterioration detection circuits (1) with an exclusive OR circuit (4). It is configured to do.

  The plurality of deterioration detection circuits (1) are serially connected, and are configured to input a clock signal to each deterioration detection circuit (1). The clock signal is input to the heater circuit (16) in the deterioration detection circuit (1). In addition to the clock signal, the heater circuit (16) is configured to receive a frequency doubled signal having a frequency twice that of the clock signal.

  As can be seen from the Black empirical formula (Equation 1) described above, the electromigration phenomenon has a large dependence on temperature. Therefore, by changing the set temperature of each deterioration detection circuit (1), it is possible to reset the expected life until disconnection occurs due to wiring deterioration due to electromigration phenomenon.

  The selector (12) is configured to output a clock signal or a frequency-multiplied signal to the heater circuit (16) based on the F / F (13) control signal. As a result, the signal output to the heater circuit (16) can be changed from a frequency-multiplied signal to a clock signal, so the signal frequency given to the heater circuit (16) is lowered and the expected life until disconnection occurs. It becomes possible to delay.

  The selector (12) is configured to output a GND signal to the heater circuit (16) based on the control signal of the F / F (13). When the GND signal is input to the heater circuit (16), the operation of the heater circuit (16) stops, so that the operating temperature of the test circuit (17) can be matched with the temperature without the LSI. As a result, it is possible to set the same expected life as that of general wiring. Therefore, the semiconductor integrated circuit of the present embodiment is provided with a plurality of deterioration detection circuits (1), set different assumed lifetimes for each deterioration detection circuit (1), and each deterioration detection circuit (1) It becomes possible to compare the deterioration results.

(Second Embodiment)
Next, a second embodiment will be described.

  The semiconductor integrated circuit of the present embodiment is configured by including a test circuit signal generation circuit (20) in each deterioration detection circuit (1). The test circuit signal generation circuit (20) receives the frequency-divided signal and outputs a signal obtained by reducing the transition probability according to the set value to the test circuit (17) via the buffer (15). FIG. 3 shows an internal configuration of the test circuit signal generation circuit (20).

  The test circuit signal generation circuit (33) includes an F / F (100), a shift register (102), and an AND circuit (103).

F / F (100) holds a control signal.
The shift register (102) is configured to output data one bit at a time and to input the output data to its least significant bit again. The initial value of the shift register (102) is set by the F / F (100) that holds the control signal. Note that the shift register (102) is driven by a clock signal.
The logical product circuit (103) generates a logical product of the frequency-divided signal and the output signal of the shift register (102), and outputs the generated signal to the test circuit (17) via the buffer (15). Is.

  FIG. 4 shows a timing chart showing the operation of the test circuit signal generation circuit (20). As shown in FIG. 4, when the output signal of the shift register (102) is “0”, it is disabled, no signal is output from the AND circuit (103), and the output signal of the shift register (102) is “ Only in the case of 1 ″, a signal is output from the AND circuit (103).

  In the semiconductor integrated circuit according to the present embodiment, the test circuit signal generation circuit (20) shown in FIG. 3 is provided for each deterioration detection circuit (1), so that the test is performed for each deterioration detection circuit (1). It is possible to set the operation rate of the signal applied to the circuit (17) separately.

  Further, the test circuit signal generation circuit (20) can increase the types of frequencies for the test circuit (17).

  By increasing the deterioration detection circuit (1) and increasing the variations in its assumed life, it becomes possible to detect the life of the wiring more accurately.

  The above-described embodiment is a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiment alone, and various modifications are made without departing from the gist of the present invention. Implementation is possible.

  For example, the control operation in each device constituting the semiconductor integrated circuit in the present embodiment described above can be executed using hardware, software, or a combined configuration of both.

  In the case of executing processing using software, it is possible to install and execute a program in which a processing sequence is recorded in a memory in a computer incorporated in dedicated hardware. Alternatively, the program can be installed and executed on a general-purpose computer capable of executing various processes.

  For example, the program can be recorded in advance on a hard disk or ROM (Read Only Memory) as a recording medium. Alternatively, the program can be stored (recorded) temporarily or permanently in a removable recording medium. Such a removable recording medium can be provided as so-called package software. Examples of the removable recording medium include a floppy (registered trademark) disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, and a semiconductor memory.

  The program is installed in the computer from the removable recording medium as described above. In addition, it is wirelessly transferred from the download site to the computer. In addition, it is transferred to the computer via a network by wire.

  In addition, the semiconductor integrated circuit according to the present embodiment is not only executed in time series according to the processing operation described in the above embodiment, but also the processing capability of the apparatus that executes the processing, or in parallel as necessary. It can also be constructed to run individually.

  The present invention is applicable to digital circuits and the like.

It is a figure which shows the structural example of the semiconductor integrated circuit in this embodiment. It is a figure which shows the structural example of the semiconductor integrated circuit in 2nd Embodiment. It is a figure which shows the example of an internal structure of the signal generation circuit for test circuits (20). It is a figure for demonstrating operation | movement of the signal generation circuit for test circuits (20).

Explanation of symbols

1 Deterioration detection circuit 4 Exclusive OR circuit (comparator)
6 F / F
10 frequency divider 11 frequency divider 12 selector 13 F / F
14, 15 Buffer 16 Heater circuit 17 Test circuit 18 Output buffer 20 Test circuit signal generation circuit 100 F / F
102 Shift register 103 AND circuit

Claims (10)

A deterioration detection circuit that detects wiring deterioration due to electromigration phenomenon,
A frequency multiplication circuit for inputting a clock signal and generating a frequency doubled signal having a frequency twice that of the clock signal;
A frequency dividing circuit for generating a frequency-divided signal having a half frequency of the clock signal;
A test circuit for inputting the frequency-divided signal and detecting wiring deterioration;
A deterioration detection circuit, comprising: a heater circuit that inputs the frequency-multiplied signal and heats the test circuit.   The deterioration detection circuit according to claim 1, wherein the test circuit and the heater circuit are configured by wiring.   The deterioration detection circuit according to claim 1, wherein the heater circuit is disposed in the vicinity of the test circuit. The test circuit includes:
4. The deterioration detection circuit according to claim 1, wherein the deterioration detection circuit is configured by thin wiring in a design rule of a process used for manufacturing an LSI.   5. The deterioration detection circuit according to claim 1, further comprising a selection circuit that outputs any one of the frequency-multiplied signal and the clock signal to the heater circuit. 6.   5. The deterioration according to claim 1, further comprising: a selection circuit that outputs any one of the frequency-multiplied signal, the clock signal, and the GND signal to the heater circuit. Detection circuit.   7. The test circuit signal generation circuit according to claim 1, further comprising: a test circuit signal generation circuit that inputs the frequency-divided signal and outputs a signal obtained by reducing a transition probability according to a set value to the test circuit. Deterioration detection circuit. The test circuit signal generation circuit includes:
A shift register that holds the setting value;
8. The deterioration according to claim 7, further comprising: a logical product circuit that generates a logical product of the divided signal and an output signal of the shift register and outputs the generated signal to the test circuit. Detection circuit.   9. A semiconductor integrated circuit comprising: N (where N is an integer of 2 or more) deterioration detection circuits according to any one of claims 1 to 8.   10. The semiconductor integrated circuit according to claim 9, further comprising a comparator for comparing the output signal of the Kth (where 1 ≦ k <N) degradation detection circuit and the output signal of the (k + 1) th degradation detection circuit. circuit.

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