JP5229513B2 - Multilayer chip capacitor - Google Patents

Description

  The present invention relates to a multilayer chip capacitor, and more particularly, to a multilayer chip capacitor having a reduced equivalent series inductance (ESL; Equivalent Series Inductance).

  Multilayer chip capacitors are usefully used as decoupling capacitors disposed in high-frequency circuits such as LSI power supply circuits. In order to stabilize the power supply circuit, the multilayer chip capacitor should have a lower ESL value. Such demands are increasing further with the trend of higher frequency and higher current of electronic devices. The stability of the power supply circuit depends on the ESL of the multilayer chip capacitor, and is particularly stable at a low ESL.

  In addition to the decoupling, the multilayer capacitor may be used as an EMI filter. In this case as well, it is preferable that the ESL is low in order to exhibit better high frequency noise removal and attenuation characteristics.

  In order to reduce ESL, Patent Document 1 proposes a method in which leads of a first internal electrode and a second internal electrode having different polarities are arranged in an interdigitated arrangement. FIG. 1A is a perspective view showing the outer shape of the multilayer chip capacitor, and FIG. 1B is a cross-sectional view of the multilayer chip capacitor taken along the line AA ′. FIG. 2 is an exploded perspective view showing the internal electrode structure of the multilayer chip capacitor of FIG.

  1 and 2, a first internal electrode 14 and a second internal electrode 15 having different polarities are formed on the dielectric layers 11a and 11b. Each internal electrode is connected to the external electrodes 12 and 13 through leads 16 and 17. The leads 16 of the first internal electrode 14 are arranged in an array that is combined adjacent to the leads 17 of the second internal electrode 15. Since the polarities of the voltages supplied to the adjacent leads are different, the magnetic flux generated by the high frequency current flowing from the external electrode is canceled out between the adjacent leads, thereby reducing the ESL.

  However, in order to implement a more stable power supply circuit in the decoupling capacitor and effectively remove high frequency noise in the EMI filter, it is necessary to further reduce the ESL of the capacitor.

US Pat. No. 5,880,925

  In order to solve the above problems, the present invention provides a multilayer capacitor having a further reduced ESL.

  The multilayer chip capacitor according to the first aspect of the present invention includes a capacitor body having a first side surface, a second side surface, an upper surface and a lower surface, which are formed by stacking a plurality of dielectric layers, and the capacitor body, A plurality of first and second internal electrodes arranged alternately to face each other through a dielectric layer, and formed on the first side surface and partially extended to the lower surface surrounding the lower edge of the first side surface A first external electrode having a first polarity; a second external electrode having a first polarity formed on the second side surface and surrounding the lower edge of the second side surface and partially extending to a lower surface; and the first and second external electrodes A third external electrode of the second polarity formed on the lower surface from between the electrodes.

  The first and second internal electrodes are disposed perpendicular to the lower surface of the capacitor body. Each of the first internal electrodes includes a first lead drawn to the first side surface and the lower surface and a second lead drawn to the second side surface and the lower surface, and each of the second internal electrodes is the first lead. And a third lead led to the lower surface from between the second leads. The first to third leads are in contact with and connected to the first to third external electrodes over the entire length of the edge of each lead exposed on the outer surface of the capacitor body.

  According to the embodiment of the present invention, the first external electrode may partially extend to the upper and lower surfaces of the capacitor body, surrounding the upper and lower corners of the first side surface of the capacitor body. The second external electrode may extend partially on the upper and lower surfaces of the capacitor body, surrounding the upper and lower corners of the second side surface of the capacitor body.

  According to the embodiment of the present invention, the width of the portion of the first lead drawn to the lower surface of the capacitor body may be the same as the width of the portion of the second lead drawn to the lower surface of the capacitor body. I can do it. In this case, it is preferable that the width of the third lead is larger than the width of the portion of the first lead drawn out to the lower surface.

  According to an embodiment of the present invention, the length of the capacitor body along the stacking direction may be shorter than the distance between the first side surface and the second side surface. In this case, the width of the portion of the first lead drawn to the lower surface may be the same as the width of the portion of the second lead drawn to the lower surface. In particular, in terms of a significant decrease in ESL, the ratio of the width of the third lead to the width of the first lead portion led out to the lower surface is preferably 1.38 or more.

  According to another embodiment of the present invention, the length of the capacitor body along the stacking direction may be longer than the distance between the first side surface and the second side surface. In this case, the width of the first lead portion drawn to the lower surface may be the same as the width of the second lead portion drawn to the lower surface. In particular, in terms of ESL reduction, the ratio of the width of the third lead to the width of the first lead portion led out to the lower surface of the capacitor body is preferably 2 or more.

  According to an embodiment of the present invention, the multilayer chip capacitor includes a first chip formed on the upper surface of the capacitor body from between the first external electrode and the second external electrode in addition to the first to third external electrodes. A bipolar fourth external electrode may be further included. In this case, the second internal electrode may further include a fourth lead that is drawn to the upper surface from between the first and second leads and connected to the fourth external electrode. In addition, the first lead can be drawn to the first side surface, the lower surface and the upper surface, and the second lead can be drawn to the second side surface, the lower surface and the upper surface. The first external electrode extends partially on the upper and lower surfaces surrounding the upper and lower corners of the first side surface, and the second external electrode surrounds the upper and lower corners of the second side surface and is aligned with the upper and lower surfaces. Can be extended. The fourth lead may be connected in contact with the fourth external electrode over the entire length of the edge of the fourth lead exposed on the lower surface. The multilayer chip capacitor may be vertically symmetric in the entire internal and external structure.

The multilayer chip capacitor according to the second aspect of the present invention provides:
A capacitor body formed by stacking a plurality of dielectric layers and having a lower surface on which a substrate is mounted;
A plurality of internal electrodes disposed perpendicularly to the bottom surface through a dielectric layer in the capacitor body;
First and second external electrodes having a first polarity formed on opposite side surfaces of the capacitor body and partially extended on the lower surface;
A third external electrode of the second polarity formed on the lower surface from between the first and second external electrodes,
The width of the third external electrode is larger than the width of the first external electrode portion extended to the lower surface and the width of the second external electrode portion extended to the lower surface.

  According to an embodiment of the second aspect, the first and second external electrodes may be symmetrically formed in a mirror image and may be extended to the lower surface with the same width.

  A multilayer chip capacitor according to a third aspect of the present invention includes a capacitor main body formed by stacking a plurality of dielectric layers and having first and second side surfaces facing a lower surface mounted on a substrate, and the capacitor main body. A plurality of first and second polarity internal electrodes, which are alternately arranged so as to face each other through a dielectric layer, and are arranged perpendicularly to the lower surface of the capacitor body, are formed on the first and second side surfaces, respectively. The first and second external electrodes are partially extended to the lower surface and electrically connected to the first polar internal electrode, and are formed on the lower surface from between the first and second external electrodes. A multilayer external capacitor connected to a bipolar internal electrode, and the multilayer chip capacitor forms two current loops that proceed from the first and second external electrodes to the third external electrode.

  According to an embodiment of the third aspect, the plurality of first polar internal electrodes have a first internal electrode pattern coupled to both the first and second external electrodes, and the plurality of second polarities. The internal electrode may have a second internal electrode pattern connected to the third external electrode.

  According to another embodiment of the third aspect, the plurality of first polar internal electrodes include a first internal electrode pattern connected only to the first external electrode and a second internal electrode connected only to the second external electrode. A third internal electrode pattern including an electrode pattern, wherein the first and second internal electrode patterns are alternately and repeatedly arranged along the stacking direction, and the plurality of second polar internal electrodes are connected only to the third external electrode. Can have.

  In the third aspect, the multilayer chip capacitor may further include a fourth external electrode having a second polarity formed on the upper surface of the capacitor body from between the first external electrode and the second external electrode.

  According to an embodiment having the fourth external electrode, the plurality of internal electrodes include a plurality of first polarity internal electrodes and a second polarity internal electrode that are alternately disposed opposite to each other in the capacitor body. The first polarity internal electrode has an “H” -shaped electrode pattern connected to the first and second external electrodes, and the second polarity internal electrode is connected to the third and fourth external electrodes. Any of them may have a “ten” -shaped electrode pattern.

  According to another embodiment having the fourth external electrode, the plurality of internal electrodes include a plurality of first polarity internal electrodes and a second polarity internal electrode that are alternately disposed opposite to each other in the capacitor body. However, two "T" -shaped first polarity electrode patterns lying in opposite directions so as to be alternately connected to the first external electrode and the second external electrode are repeatedly arranged alternately to form the plurality of first electrodes. A unipolar internal electrode is formed, and each of the second polar internal electrodes may have a “ten” -shaped electrode pattern.

A multilayer chip capacitor according to a fourth aspect of the present invention includes a capacitor main body formed by stacking a plurality of dielectric layers and having first and second side surfaces facing a lower surface mounted on a substrate. A plurality of first polarity and second polarity internal electrodes arranged alternately so as to face each other through a dielectric layer and perpendicular to the lower surface, and formed on the first and second side surfaces, respectively, on the lower surface First and second external electrodes that are partially extended and electrically connected to the first polar internal electrode, and formed between the first and second external electrodes on the lower surface, and the second polar internal electrode A third external electrode connected,
The first polarity internal electrode is connected to the first polarity main part and one of the first and second external electrodes, and is drawn from the first polarity main part to the lower surface and one side surface. With polar leads,
The second polarity internal electrode has a second polarity main part and a second polarity lead drawn from the second polarity main part to the lower surface so as to be connected to the third external electrode-the first polarity main The distance from the lower part to the lower surface is the same as the distance from the second polarity main part to the lower surface-,
The gap between adjacent first and second polarity leads is G, the distance from the first polarity main portion to the lower surface is M, the total number of internal electrodes arranged in the capacitor body is N, and the lower surface is drawn to the lower surface. When the ratio of the width W ₂ of the second polarity lead to the width W ₁ of the first polarity lead portion is W ₂ / W ₁ , the G, M, N, and W ₂ / W ₁ are adjusted to make the final ESL becomes 100 pH or less.

  According to an embodiment of the fourth aspect, each of the first polarity internal electrodes has two first polarity leads to be connected to the first and second external electrodes, but the two first polarity leads Can be a first lead drawn to the lower surface and the first side surface and connected to the first external electrode, and a second lead drawn to the lower surface and the second side surface and connected to the second external electrode.

  According to another embodiment of the fourth aspect, the plurality of first polar internal electrodes are a first internal electrode pattern connected only to the first external electrode and a second internal electrode connected only to the second external electrode. The first and second internal electrode patterns are alternately and repeatedly arranged along the stacking direction, and the plurality of second polar internal electrodes are connected to only the third external electrode. Can have. The first internal electrode pattern has a first lead drawn to the lower surface and the first side surface and connected to the first external electrode, and the second internal electrode pattern is drawn to the lower surface and the second side surface and has the first lead. There may be a second lead connected to the two external electrodes.

  In the fourth aspect, the multilayer chip capacitor may further include a fourth external electrode having a second polarity formed on the upper surface of the capacitor body from between the first external electrode and the second external electrode.

  According to an embodiment having the fourth external electrode, the first polarity internal electrode has an “H” -shaped electrode pattern to be connected to the first and second external electrodes, and the second polarity The internal electrode may have a “ten” -shaped electrode pattern so as to be connected to the third and fourth external electrodes.

  According to another embodiment having the fourth external electrode, two “T” -shaped first polarity electrode patterns lying in opposite directions to be alternately connected to the first external electrode and the second external electrode are provided. The plurality of first polarity internal electrodes are repeatedly arranged alternately to form the plurality of first polarity internal electrodes, and each of the second polarity internal electrodes has a “ten” -shaped electrode pattern so as to be connected to the third and fourth external electrodes. I can do it.

A multilayer chip capacitor according to a fifth aspect of the present invention is formed by stacking a plurality of dielectric layers, and has third and fourth side surfaces facing first and second side surfaces facing a lower surface mounted on a substrate. A capacitor body;
A plurality of first and second polarity internal electrodes disposed alternately in the capacitor body so as to face each other through a dielectric layer, and disposed in parallel to the lower surface of the capacitor body;
A first external electrode formed on the first side surface, partially extended to the third and fourth side surfaces and electrically connected to the first polar internal electrode;
A second external electrode formed on the second side surface, partially extended to the third and fourth side surfaces and electrically connected to the first polar internal electrode;
A third external electrode formed on the third and fourth side surfaces from between the first and second side surfaces and electrically connected to the second polarity internal electrode;
The internal electrode having the first polarity is led to one side surface of the first and second side surfaces and the third and fourth side surfaces so as to be connected to one of the first and second external electrodes. Having a first polarity lead;
The second polarity internal electrode has two second polarity leads respectively led to the third and fourth side surfaces to be connected to the third external electrode;
The ratio of the width of the second polarity lead to the width of the first polarity lead portion led out to the third and fourth side surfaces is 1.43 or more.

  According to an embodiment of the fifth aspect, the first polar internal electrode has an “H” -shaped electrode pattern to be connected to the first and second external electrodes, and the second polar internal electrode Each may have a “ten” -shaped electrode pattern to be connected to the third external electrode.

  According to another embodiment of the fifth aspect, two “T” -shaped first polarity electrode patterns lying in opposite directions so as to be alternately connected to the first external electrode and the second external electrode are alternately replaced. The plurality of first polar internal electrodes may be repeatedly arranged, and the second polar internal electrodes may have a “10” -shaped electrode pattern so as to be connected to the third external electrode.

  In the present specification, the “lower surface” of the capacitor body refers to a surface mounted on the circuit board when the capacitor is mounted on the circuit board, and the upper surface of the capacitor body refers to a surface facing the lower surface.

  According to the present invention, the ESL of the multilayer chip capacitor is further reduced. As a result, when applied to a decoupling capacitor, an EMI filter, and the like, voltage fluctuations in the power supply circuit can be more effectively suppressed, and the high-frequency attenuation characteristics and the high-frequency noise removal effect can be further improved.

  Embodiments of the present invention will be described below with reference to the accompanying drawings. However, the embodiment of the present invention can be modified into various forms, and the scope of the present invention is not limited by the embodiment described below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. The shape and size of elements in the drawings may be exaggerated for a clearer description, and elements denoted by the same reference numerals in the drawings are the same elements.

  FIG. 3 is a perspective view showing the internal structure of the multilayer chip capacitor according to one embodiment (FIG. 3A), and a perspective view showing a state in which the multilayer chip capacitor is mounted on a circuit board (FIG. 3). (B)). In the present embodiment, the length L of the capacitor body 31 in the stacking direction (x direction) is smaller than the distance W between both side surfaces C and D parallel to the stacking direction.

  3A and 3B, the multilayer capacitor 30 includes a capacitor body formed by laminating a plurality of dielectric layers (see reference numerals '31a' and '31b' in FIG. 4). 31 is included. Inside the capacitor main body 31, the first internal electrode 32 and the second internal electrode 33 are alternately arranged so as to face each other with a dielectric layer interposed therebetween. The capacitor body 31 has a rectangular parallelepiped shape.

First and second external electrodes 34a and 34b having the same polarity are formed on the first and second side surfaces C and D of the main body 31, respectively. In particular, the first and second external electrodes 34a, 34b are extended respectively to the corresponding sides C, the lower surface only extended the width W ₁₀ predetermined surrounds the lower edge of the D (square) B. The first and second external electrodes 34 a and 34 b have the same polarity and are electrically connected to the first internal electrode 32 through the leads 32 a and 32 b of the first internal electrode 32. The first and second external electrodes 34a and 34b are extended to the upper surface A by a predetermined extension width so as to surround the upper edges (corners) of the corresponding side surfaces C and D. In the present embodiment, the first and second external electrodes 34a and 34b do not necessarily extend to the upper surface, but the first and second external electrodes can be applied not only to the lower surface B but also to the upper surface A. This is advantageous in terms of process. As shown in FIG. 3, the first and second external electrodes 34 a and 34 b are formed in a mirror phase symmetrically to each other and can be extended to the lower surface B with the same width. Unlike this, the width of the first external electrode 34a extended to the lower surface may not be the same as the width of the second external electrode 34b extended to the lower surface due to variations in the external electrode coating process. .

The third external electrode 35 of other polarity is separated from the first and second external electrodes 34a and 34b, and is formed on the lower surface B (particularly the central portion of the lower surface) along the stacking direction from between the external electrodes 34a and 34b. Has been. The third external electrode 35 is electrically connected to the second internal electrode 33 through the lead 33 a of the second internal electrode 33. In FIG. 3, the reference symbol W ₂₀ indicates the width of the third external electrode 35.

  According to the capacitor 30, the lower surface B of the capacitor body 31 is parallel to the stacking direction (x direction), and the internal electrodes 32 and 33 are arranged perpendicular to the circuit board 101 (the lower surface B is a mounting surface on the circuit board). ). When the internal electrodes are arranged perpendicular to the mounting surface of the circuit board in this way, the external electrodes 34a and 34b can be formed from the electrode pads (104a, 104b, 105: see FIG. 3B) of the circuit board without a separate current path. , 35 can pass through the internal electrodes 32, 33 directly through the thickness. Accordingly, the ESL can be lowered as compared with other capacitors having internal electrodes arranged horizontally on the circuit board, and the ESL is further lowered by increasing the number of stacked layers.

  Referring to FIG. 3B, the first and second external electrodes 34a and 34b are connected to the (+) electrode pads 104a and 104b of the circuit board 101, and the third external electrode 35 is the (−) electrode of the circuit board 101. It is connected to the pad 105. For example, when the capacitor 30 is used as a three-terminal EMI filter, the first and second external electrodes 34a and 34b are connected to the input end and output end of the signal line, respectively, and the third external electrode 35 is connected to the ground end. High frequency noise in the signal line can be removed (in this case, the (+) electrode pads 104a and 104b correspond to the input / output terminals and the (−) electrode pad 105 corresponds to the ground terminal).

  As another application example, when the capacitor 30 is used as a decoupling capacitor, the first and second external electrodes 34a and 34b are connected to the power supply line, and the third external electrode 35 is connected to the ground line to stabilize the power supply circuit. (In this case, the (+) electrode pads 104a and 104b correspond to power supply lines, and the (−) electrode pad 105 corresponds to a ground terminal).

  4 is a perspective view showing the arrangement of the external electrodes of the capacitor 30 of FIG. 3 (FIG. 4A), a cross-sectional view showing the structure of the first internal electrode (FIG. 4B), and the second internal It is sectional drawing (FIG.4 (c)) showing the structure of the electrode. 4 corresponds to a cross-sectional view cut in a direction perpendicular to the stacking direction (x direction).

  Referring to FIG. 4, first and second internal electrodes 32 and 33 are alternately formed on the dielectric layers 31 a and 31 b in the capacitor body 31. Each of the internal electrodes 32 and 33 can be divided into a main portion and a lead. (In FIG. 4, the boundary between the main part and the lead is indicated by a dotted line for convenience). The 'main part' of the internal electrode is a main part that contributes to capacitance as a part where the internal electrodes facing each other are overlapped when viewed from the stacking direction, and the 'lead' of the internal electrode extends from the main part and extends to the external electrode The part that provides the connection.

  The first internal electrode 32 includes a first lead 32a drawn to the first side surface (C: left side as viewed from the drawing) and a second lead 32b drawn to the second side surface (D: right side). Further, the first lead 32a is drawn not only to the first side face C but also to the lower face B. Accordingly, the first lead 32 a is extended to a width wider than the width (z direction) on the short side of the main portion of the first internal electrode 32. Similarly, the second lead 32b is drawn not only to the second side face D but also to the lower face B and has a wide width. Edges (lead edges on the outer surface) of the leads 32a and 32b exposed on the outer surface of the capacitor body are continuously extended from the side surface (C or D) to the lower surface B through corners. The second internal electrode 33 includes a third lead 33a led out to the lower surface. The third lead is drawn out from between the first lead 32a and the second lead 32b to the central portion of the lower surface B when viewed from the stacking direction and connected to the third external electrode (see FIG. 4C).

  As shown in FIGS. 4B and 4C, the first lead 32a of the first internal electrode 32 is the entire edge (end) exposed on the outer surface (first side C and lower surface B) of the capacitor body. The first external electrode 34a is in contact with and connected to the first external electrode 34a. The second lead 32b of the first internal electrode 32 is in contact with and connected to the second external electrode 34b over the entire length of the edge exposed on the outer surface (second side surface D and lower surface B) of the capacitor body. . The first internal electrode 32 is connected to the first and second external electrodes 34a and 34b, and the first internal electrode and the first and second external electrodes have the same polarity.

The third lead 33a of the second inner electrode 33 is in contact with and connected to the third outer electrode 35 over the entire length of the edge exposed on the outer surface (lower surface B) of the capacitor body. Therefore, as shown in FIG. 4, the widths W ₁₀ and W ₂₀ of the external electrodes extended in the y direction are equal to or larger than the widths W ₁ and W _{2 in} the y direction of the leads connected thereto. When viewed from a cut surface perpendicular to the stacking direction, the length of each external electrode 34a, 34b, 35 is equal to or greater than the length of the exposed edge of each lead 32a, 32b, 33a connected thereto. The second internal electrode 33 is connected to the third external electrode 35 through the third lead 33 a, and the second internal electrode 33 and the third external electrode 35 have a polarity different from that of the first internal electrode 32.

  As described above, the third lead 33a having the other polarity is disposed adjacent to and between the first and second leads 32a and 32b having the same polarity, so that the magnetic flux is canceled between the adjacent current paths, and the parasitic inductance. Decrease. Further, since the first and second leads 32a and 32b are in contact with the first and second external electrodes 34a and 34b with a wide width across the side surfaces C and D and the lower surface B, respectively, the contact area of the contact portion between the inner and outer electrodes is reduced. The current path flowing from the first and second leads can have a wide width. Since the wide current path contributes to reducing the parasitic inductance, the ESL of the entire capacitor is further reduced.

As shown in FIGS. 4B and 4C, when viewed from the stacking direction (x direction), the capacitor 30 has symmetrical internal and external structures. In particular, the width W ₁ of the drawn-out portion on the bottom surface B in the first lead 32a, the width W ₁ of the drawn-out portion on the bottom surface B in the second lead 32b are mutually identical. In this case, the width W ₂ of the third lead is preferably larger than the width W ₁ of the portion drawn on the lower surface of the first lead.

When viewed from the side of the parasitic inductance, it is preferable that the width W ₂ of the third lead is greater than the width W ₁ of the portion drawn on the lower surface of the first and second lead. The inventors have experimentally discovered that the ESL decreases as the ratio of the width of the first lead to the third lead (W ₂ / W ₁ ) increases in the y direction. According to this experiment, the ratio (W ₂ / W ₁ ) of the width particularly decreases significantly at 1.38 or more.

FIG. 5 is a graph showing experimental results of ESL evaluation performed using the capacitor sample as shown in FIG. In particular, FIG. 5 shows a change in the ESL value according to the ratio (W ₂ / W ₁ ) of the width W ₂ of the third lead to the width W ₁ of the first (or second) lead portion drawn to the lower surface B. Specific data for the above graph is shown in Table 1 below.

As shown in Table 1 and Figure 5, it can be seen that ESL value of the multilayer capacitor with the ratio of W ₂ with respect to W ₁ is changed. When W ₁ is larger than W ₂ , for example, when W ₂ / W ₁ is 0.3, the ESL value represents 99.17 pH, but when W ₁ is decreased and W ₂ is increased, the ESL value gradually decreases. I understand that.

In particular, when the width ratio (W ₂ / W ₁ ) is 1.38 or more, it can be seen that the ESL is remarkably low. As shown in Table 1 and FIG. 5, when the width ratio (W ₂ / W ₁ ) is 0.3, the ESL is 99 pH or more, and when the width ratio (W ₂ / W ₁ ) is 1, the ESL is Although the pH is 87 pH or more, when the width ratio (W ₂ / W ₁ ) is about 1.38, the ESL value is greatly lowered to 83.43 pH or less. When the width ratio (W ₂ / W ₁ ) is greater than ₂ , the decrease in ESL due to the increase in the width ratio (W ₂ / W ₁ ) becomes very gradual. Therefore, in order to implement the minimized ESL in the three-terminal capacitor of FIG. 4, the width ratio (W ₂ / W ₁ ) is preferably 1.38 or more. Also, the ESL can be precisely controlled through adjustment of the width ratio (W ₂ / W ₁ ).

In the side surface of the external electrode forming step, the width ratio (W ₂ / W ₁ ) is preferably 7 or less. When the width ratio (W ₂ / W ₁ ) is greater than 7, the extension width W ₁₀ to the lower surface of the first external electrode is too small, or the width W ₂₀ of the third external electrode is too wide, When using an external electrode application process, it may be difficult to apply each external electrode precisely.

  FIG. 6 is a perspective view (FIG. 6A) illustrating the outer shape of a capacitor according to another embodiment of the present invention, a first internal electrode structure (FIG. 6B), and a second internal electrode structure (FIG. 6). It is sectional drawing for representing (c)). In the present embodiment, the capacitor 60 further includes a fourth external electrode 65 b connected to the second internal electrode 63. In particular, in this embodiment, the internal and external structures of the capacitor are vertically symmetrical.

Referring to FIG. 6A, the first and second external electrodes 64a and 64b are formed on the first and second side surfaces C and D, respectively, and have predetermined widths around the upper and lower corners of the corresponding side surfaces C and D. only W ₁₀ extend partially into the upper surface a and lower surface B. The third and fourth external electrodes 65a and 65b are formed on the upper surface A and the lower surface B from between the first external electrode and the second external electrode, respectively, and extend along the stacking direction (x direction). Third and fourth external electrodes 65a, 65b is particularly arranged in the center portion of the upper and lower surfaces, has a predetermined width _{W 20} of the side C, the direction perpendicular to D (y direction).

  Referring to FIGS. 6B and 6C, a first internal electrode 62 and a second internal electrode 63 are formed on the dielectric layers 61a and 61b, respectively. The first internal electrode 62 is formed in an “H” shape and is connected to the first and second external electrodes 64a and 64b through the first and second leads 62a and 62b. In particular, the first lead 62 a is drawn to the first side C, the upper surface A, and the lower surface B of the main body 61, and the second lead 62 b is drawn to the second side D, the upper surface A, and the lower surface B of the main body 61.

  The second internal electrode 63 is formed in a “ten” shape, and is connected to the third and fourth external electrodes 65a and 65b through the third and fourth leads 63a and 63b. The second internal electrode 63 and the third and fourth external electrodes 65 a and 65 b have different polarities from the first internal electrode 62. Each lead 62a, 62b, 63a, 63b is connected in contact with the corresponding external electrode 64a, 64b, 65a, 65b over the entire length of the edge of each lead exposed on the outer surface of the capacitor body. The leads 62a and 62b of the first internal electrode 62 are in contact with the external electrodes 64a and 64b corresponding to a wide contact area across the first side surface C, the lower surface B, and the upper surface A. Therefore, the effect of reducing ESL can be obtained as in the above-described embodiment.

  As in this embodiment, by forming the internal and external structures of the capacitor body in a symmetric structure (compared to the embodiment of FIG. 4), the directionality of the capacitor chip can be eliminated, thereby Any surface of the upper surface A and the lower surface B can be provided as a mounting surface during surface mounting. Therefore, there is an advantage that it is not necessary to consider the direction of the mounting surface when mounting the capacitor.

  FIG. 7 is a perspective view illustrating an arrangement of external electrodes of a capacitor according to still another embodiment of the present invention (FIG. 7A), a first internal electrode (FIG. 7B), and a second internal electrode (FIG. 7). It is sectional drawing showing the structure of (c)). The capacitor of this embodiment is the same as that shown in FIG. 4 except that the length L of the capacitor body in the stacking direction (x direction) is larger than the distance W between both side surfaces parallel to the stacking direction. It has almost the same structure as the form.

Referring to FIG. 7, the first and second external electrodes 74a one polarity, 74b is extended part by a predetermined width W ₁₀ on both sides C, are formed respectively on the D and the upper surface A and lower surface B of the capacitor body 71 The A third external electrode 75 having another polarity is formed on the lower surface of the capacitor body 71 and is separated from the first and second external electrodes 74a and 74b. The third external electrode 75 has a width W _{20 in the} y direction. Similar to the embodiment of FIG. 4, the first and second external electrodes 74 a and 74 b are in contact with the first and second leads 72 a and 72 b, respectively, with a wide contact area extending over the side surface and the bottom surface, thereby forming the first internal electrode 72. Connected. The third external electrode 75 is connected to the second internal electrode 73 in contact with the third lead 73a. Reference numerals 71a and 71b in FIG. 7 denote dielectric layers.

  In particular, the length L of the capacitor body 71 in the stacking direction (x direction) is greater than the distance W between the side surfaces C and D parallel to the stacking direction. Such a structure is suitable for increasing the number of stacked internal electrodes, and a larger capacity and smaller ESL can be realized as the number of stacked layers increases.

In the present embodiment, it is preferable that the width _{W 2} of the third lead 73a is larger than the width _{W 1} of the drawn-out portion on the lower surface B of the first or second lead (72a or 72b). According to the ESL evaluation test conducted by the inventors on samples having various width ratios (W ₂ / W ₁ ), the ESL decreases as the width ratio (W ₂ / W ₁ ) increases. I confirmed the facts.

FIG. 8 is a graphical representation of the test results for the sample according to the embodiment of FIG. 7, and represents the ESL value according to the width ratio (W ₂ / W ₁ ). Specific data regarding the graph is shown in Table 2 below.

Lead electrode ratio

Referring to FIG. 8 and Table 2, when the ratio of W ₁ and W ₂ (W ₂ / W ₁ ) is 0.82 or less, an ESL value exceeding 90 pH is represented, but the W ₂ / W ₁ value is 2 or more. In this case, the ESL value represents a remarkably low value of 76.09 pH or less. When W ₂ / W ₁ is 2 or more, the ESL gradually decreases as W ₂ / W ₁ increases. The width ratio (W ₂ / W ₁ ) is preferably 7 or less on the side of the external electrode application step.

Therefore, as shown in FIG. 7, when the length L of the main body in the stacking direction is larger than the distance W between the opposite side surfaces C and D parallel to the stacking direction, the width ratio (W ₂ / W _By setting ₁ ) to 2.0 or more, it is possible to implement a highly reduced ESL high-performance decoupling capacitor or EMI filter.

  FIG. 9 is a perspective view illustrating an arrangement of external electrodes of a capacitor according to still another embodiment of the present invention (FIG. 9A), a first internal electrode (FIG. 9B), and a second internal electrode (FIG. 9A). It is sectional drawing showing the structure of FIG.9 (c)). In the present embodiment, the capacitor further includes a fourth external electrode 95b formed on the upper surface A and connected to the second internal electrode 93 (the internal and external structures are vertically symmetrical). Further, the length L of the capacitor body in the stacking direction is larger than the distance W between the two side surfaces C and D.

Referring to FIG. 9A, the first and second external electrodes 94a and 94b are formed on the first and second side surfaces C and D, respectively, and have predetermined widths around the upper and lower corners of the corresponding side surfaces C and D. only W ₁₀ extend partially into the upper surface a and lower surface B. The third and fourth external electrodes 95a and 95b are formed on the upper surface A and the lower surface B from between the first external electrode and the second external electrode, respectively, and extend along the stacking direction (x direction). Third and fourth external electrodes 95a, 95b is particularly arranged in the center portion of the upper and lower surfaces has a width _{W 20} of the side C, the direction perpendicular to D (y direction).

  Referring to FIGS. 9B and 9C, first and second internal electrodes 93 are formed on the dielectric layers 91a and 91b, respectively. The first internal electrode 92 is connected to the first and second external electrodes 94a and 94b through the first and second leads 92a and 92b. In particular, the first lead 92 a is drawn to the first side C, the upper surface A, and the lower surface B of the main body 91, and the second lead 92 b is drawn to the second side D, the upper surface A, and the lower surface B of the main body 91.

  The second internal electrode 93 is connected to the third and fourth external electrodes 95a and 95b through the third and fourth leads 93a and 93b. The second internal electrode 93 and the third and fourth external electrodes 95 a and 95 b have different polarities from the first internal electrode 92. The first to fourth leads 92a, 92b, 93a, 93b are in contact with and connected to the corresponding external electrodes 94a, 94b, 95a, 95b over the entire length of the edge of each lead exposed on the outer surface of the capacitor body. The

  Each lead 92a, 92b of the first internal electrode 92 is connected in contact with the external electrodes 94a, 94b corresponding to a wide contact area across the first side face C, the lower face B, and the upper face A, thereby reducing ESL. In addition, since the inner and outer structures of the capacitor are vertically symmetric, either the upper surface or the lower surface can be provided as a mounting surface, thereby eliminating the need to consider the direction of the mounting surface when mounting the capacitor. Occurs. Further, by making the length L of the main body larger than the distance between the side surfaces C and D, it is advantageous for increasing the number of laminated internal electrodes, and a larger capacity and a smaller ESL can be realized.

  The multilayer chip capacitor according to the embodiment of the present invention has an advantage that the number of current loops (current loops caused by current flowing from or to the mounting board) connected in parallel can be increased while the total number of external electrodes is small. provide. This is clearly shown in FIG.

  FIG. 10 is a side view schematically illustrating a current loop formed in a capacitor during operation of the multilayer chip capacitor according to the embodiment of the present invention. 10 shows only the current loop of the capacitor of FIG. 6 for the sake of convenience, those skilled in the art can fully understand that the same current loop is formed by the capacitors of FIGS. This also applies to the capacitors of FIGS. 16 and 17).

  As shown in FIG. 10, when viewed from the direction perpendicular to the internal electrode surface, the capacitor travels from the first external electrode 64a to the third external electrode 65a through the first internal electrode 62 and the second internal electrode 63 during operation. A loop CL1 and a current loop CL2 that travels from the second external electrode 64b to the third external electrode 65a through the first and second internal electrodes 62 and 63 are formed. Thus, by forming the above two parallel-connected current loops CL1 and CL2 with only four or three external electrodes, it is possible to reduce the number of external electrodes and at the same time obtain a low ESL.

  According to experiments conducted by the present inventors, it is possible to control the ESL of the capacitor by adjusting four important design factors as described below, and in particular, to reduce the final ESL of the capacitor to 100 pH or less. I understood that I could do it.

FIG. 11 shows the gap G between the leads of adjacent internal electrodes, the lead widths W ₁ and W ₂ , and the distances M ₁ and M ₂ from the main portion to the bottom surface of the internal electrodes in the multilayer chip capacitor of FIG. It is a vertical sectional view. The gap G is lead 62a of different polarities adjacent, intervals between 63a, the distance M ₁ is the distance to the bottom surface B of the capacitor body from the main portion of the first internal electrode 62, the distance M ₂ to the second internal electrode 63 is a distance from the main part 63 to the lower surface B. Here, M ₁ = M ₂ = M.

FIG. 12 is a graph showing frequency (MHz) vs. ESL (H) characteristics for the multilayer chip capacitor of FIG. In the graph of FIG. 12, when the distance (M = M ₁ = M ₂ ) is 100 μm, the lead width ratio (W ₂ / W ₁ ) is 6.0, and the total number of internal electrodes is 200 layers, the multilayer chip capacitor 60 Represents the ESL characteristic. As shown in FIG. 12, at a frequency of 10 MHz or higher, both G = 300 μm and G = 200 μm have low ESL values of 100 pH or less. The smaller the gap G, the lower the ESL of the capacitor. As the gap G is smaller, the areas of the current loops CL1 and CL2 shown in FIG. 10 are smaller, thereby reducing the inductance component due to the current loop.

FIG. 13 is a graph showing a change in ESL relative value according to the ratio of the lead widths (R = W ₂ / W ₁ ) in the multilayer chip capacitor of FIG. The graph of FIG. 13 represents the ESL relative value of the multilayer chip capacitor 60 when the distance M is 100 μm, the gap G is 200 μm, and the total number of internal electrodes is 50 layers. In the graph of FIG. 13, the relative value (%) of ESL is a value obtained by setting the ESL at the reference value 100 when W ₂ / W ₁ = 0.3. As shown in the graph of FIG. 13, the ESL decreases as the ratio of the lead width (W ₂ / W ₁ ) increases, and in particular, the decrease rate (gradient) of ESL increases rapidly around W ₂ / W ₁ = 1.38. It turns out to change.

FIG. 14 is a graph showing the frequency (MHz) vs. ESL (H) characteristics for the multilayer chip capacitor of FIG. The graph of FIG. 14 represents the ESL characteristic of the multilayer chip capacitor 60 when the gap G is 200 μm, the lead width ratio (W ₂ / W ₁ ) is 6.0, and the total number of internal electrodes is 50 layers. As shown in the graph of FIG. 14, when the distance M = 100 μm, the ESL value is almost 100 pH or less in the frequency range of 100 to 1000 MHz (except around 100 MHz). When the distance M = 70 μm, the ESL value lower than 100 pH is expressed over the entire frequency range of 100 to 1000 MHz. The smaller the distance M, the smaller the inductance of the capacitor. This is due to a decrease in the area of the current loop (CL1, CL2: see FIG. 10) due to the decrease in the distance M.

FIG. 15 is a graph showing a change in the relative value of ESL according to the total number of internal electrodes in the main body (total number of internal electrodes stacked) in the multilayer chip capacitor of FIG. The vertical arrangement of the internal electrodes provides the advantage of further reducing ESL with increasing number of internal electrode stacks. The graph of FIG. 15 represents the ESL relative value of the multilayer chip capacitor 60 when the gap G is 200 μm, the lead width ratio (W ₂ / W ₁ ) is 6.0, and the distance M is 100 μm. As shown in FIG. 15, the ESL decreases as the number of stacked internal electrodes increases.

As described above, it can be confirmed that the inductance or ESL characteristic of the capacitor varies depending on four important design factors (G, W ₂ / W ₁ , M, the number of stacked internal electrodes). By adjusting these four design factors, it is possible to realize an ESL of 100 pH or less, which is required for a decoupling capacitor mainly used in a high-speed MPU package. The ESL (or inductance) behavior described above with four design factors is not limited to the embodiment of FIG. 11 (or FIG. 6). The same ESL behavior is expressed for the capacitor of FIG. 4 (or FIG. 3) that does not have the fourth external electrode on the top surface. The fourth external electrode 65b is for the convenience of mounting the capacitor (that is, the capacitor can be mounted on the circuit board regardless of the upper and lower sides), and does not actually contribute to the current path.

  FIG. 16 is a perspective view (FIG. 16 (a)) showing the outer shape of a multilayer chip capacitor according to still another embodiment of the present invention, and a vertical sectional view (FIG. 16 (b)) showing the internal electrode structure. is there. In the present embodiment, unlike the above-described embodiments, each unipolar internal electrode does not have the same electrode pattern, but is divided into two electrode patterns. Also in this embodiment, the internal electrodes 132, 132 ′, and 133 are arranged perpendicular to the lower surface (the surface mounted on the circuit board).

  Referring to FIG. 16A, the external shape of the capacitor 130 is the same as that of the capacitor 30 of FIGS. First and second external electrodes 134a and 134b having the same polarity are formed on the first and second side surfaces of the main body 131, respectively, and partially extend to the lower surface B and the upper surface so as to surround the lower corner. The third external electrode 135 of other polarity is spaced from the first and second external electrodes 134a and 134b and is formed on the lower surface along the stacking direction (y direction) from between the first and second external electrodes 134a and 134b. .

  Referring to FIGS. 16A and 16B, in the capacitor body 131, a first polarity first internal electrode pattern 132 and a first polarity second internal electrode pattern 132 ′ are formed as dielectric layers 131a and 131a ′. Placed in turn on top. A third internal electrode pattern 133 having another polarity is disposed on the dielectric layer 131b between the first electrode patterns 132 and 132 ′ having the first polarity. Accordingly, the first, third, and second internal electrode patterns 132, 133, and 132 ′ are repeatedly arranged alternately in the order of 132, 133, 132 ′, 133, 132, 133, 132 ′,. . That is, the first polarity internal electrode (132 or 132 ′) and the second polarity internal electrode 133 are alternately arranged to face each other through the dielectric layer, and the first polarity internal electrodes 132 and 132 ′ are the first polarity. The internal electrode pattern 132 and the second internal electrode pattern 132 ′ have an arrangement structure that is alternately arranged along the stacking direction (y direction). As described above, the internal electrode having the first polarity is divided into the two electrode patterns 132 and 132 ′, and the internal electrode having the second polarity has only one electrode pattern 133.

  As shown in FIG. 16B, the first polarity first internal electrode pattern 132 is connected to the first external electrode 134a through the first lead 132a led out to the first side surface and the lower surface B. The second internal electrode pattern 132 ′ having the first polarity is connected to the second external electrode 134b through the second lead 132a ′ led out to the second side surface and the lower surface B. The third polarity third internal electrode pattern 133 is connected to the third external electrode 135 through a third lead 133a led to the lower surface.

  The first and second leads 132a and 132a ′ are in contact with and connected to the first and second external electrodes 134a and 134b over the entire length of the lead edges exposed on the side surfaces and the lower surface, respectively, thereby connecting the inner and outer surfaces. The contact area of the contact portion between the electrodes is maximized, and the current path flowing through the contact portion has a wide width. The third lead 133 contacts and is connected to the third external electrode 135 over the entire length of the lead edge exposed on the lower surface.

Also in the embodiment of FIG. 16, as described with reference to FIGS. 11 to 15, the capacitor 130 depends on the gap G, the lead width ratio (W ₂ / W ₁ ), the distance M, and the number of stacked internal electrodes. The ESL value changes, and an ESL of 100 pH or less can be realized by adjusting the above four design factors. The capacitor of FIG. 16 has no difference except that the first polarity internal electrode is separated into two electrode patterns when compared with the capacitor of FIG. 15)) and almost the same ESL change behavior.

  17 is a perspective view (FIG. 17A) showing the outer shape of the multilayer chip capacitor according to the modification of FIG. 16, and a vertical sectional view showing the internal electrode structure (FIG. 17B). 17 is different from the capacitor 130 in FIG. 16 in that the capacitor 160 further includes a fourth external electrode 165b on the upper surface and has a vertically symmetrical external and internal structure.

  Referring to FIG. 17A, the outer shape of the capacitor 160 is almost the same as the capacitor 60 of FIG. First and second external electrodes 164a and 164b having the same polarity are formed on the first and second side surfaces of the main body 161, respectively, and partially extend to the lower surface B and the upper surface so as to surround the lower and upper corners of the main body 161. The third and fourth external electrodes 165a and 165b having other polarities are formed on the lower surface B and the upper surface, respectively, along the stacking direction (y direction).

  Referring to FIGS. 17A and 17B, a first internal electrode pattern 162 having a first polarity and a second internal electrode pattern 162 ′ having a first polarity are formed in dielectric layers 161a and 161a ′ in the capacitor body 161. Placed in turn on top. A third internal electrode pattern 163 of another polarity is disposed on the dielectric layer 161b between the first polarity internal electrode patterns 162 and 162 ′. Each of the first polar internal electrodes has a “T” -shaped electrode pattern. Two “T” -shaped electrode patterns 162 and 162 ′ lying in opposite directions are repeatedly arranged alternately to form a plurality of first polar internal electrodes. Each of the third internal electrode patterns 163 has a “ten” -shaped electrode pattern.

  As shown in FIG. 17B, the first polarity first internal electrode pattern 162 is connected to the first external electrode 164a through the first lead 162a drawn out to the first side surface, the lower surface and the upper surface. The second internal electrode pattern 162 ′ having the first polarity is connected to the second external electrode 164b through the second side 162a ′ drawn to the second side surface, the lower surface, and the upper surface. The third internal electrode pattern 163 having the second polarity is connected to the third and fourth external electrodes 165a and 165b through the third and fourth leads 163a and 163b drawn to the lower surface and the upper surface, respectively.

  The first and second leads 162a and 162a ′ are in contact with and connected to the first and second external electrodes 164a and 164b over the entire length of the lead edge exposed on the side surfaces and the lower surface, respectively. The contact area of the contact portion between the electrodes is maximized, and the current path flowing through the contact portion has a wide width. The third lead 163 contacts and is connected to the third external electrode 165 over the entire length of the lead edge exposed on the lower surface.

  By forming the internal and external structures of the capacitor main body in a symmetric structure as in this embodiment (compared to the embodiment of FIG. 16), the directionality of the capacitor chip can be removed, thereby the surface of the capacitor. Either the upper surface or the lower surface can be provided as a mounting surface during mounting. Therefore, there is an advantage that it is not necessary to consider the direction of the mounting surface when mounting the capacitor.

Also in the embodiment of FIG. 17, as described with reference to FIGS. 11 to 15, the capacitor 160 depends on the gap G, the ratio of the lead width (W ₂ / W ₁ ), the distance M, and the number of stacked internal electrodes. The ESL value changes, and an ESL of 100 pH or less can be realized by adjusting the above four design factors. The capacitor of FIG. 17 has no difference except that the internal electrode of the first polarity is separated into two electrode patterns when compared with the capacitor of FIG. 6 (or FIG. 11). The ESL change behavior is almost the same as (see FIGS. 11 to 15).

  FIG. 18 is a perspective view (FIG. 18A) showing the outer shape of a multilayer chip capacitor according to still another embodiment of the present invention, and a horizontal sectional view (FIG. 18B) showing the structure of the internal electrode. is there. In the embodiment of FIG. 18, the internal electrodes are horizontally disposed on the lower surface (the surface mounted on the circuit board).

  Referring to FIG. 18A, the capacitor 260 has a symmetrical outer shape in the vertical and horizontal directions. First and second external electrodes 264a and 264b having a first polarity are formed on the first side surface S1 and the second side surface S2 of the capacitor body 260, respectively. The other third side surface S3 and the fourth side surface S4 are opposed to each other. Are formed with third external electrodes 265a and 265b having a second polarity. The third external electrodes 265a and 265b are separated from each other into two parts. However, the two separated parts may be connected as a single body to completely surround the central part of the main body 261 in a band shape. The first and second external electrodes 264a and 264b are both partially extended to the third and fourth side surfaces S3 and S4.

  Referring to FIG. 18B, the structure of the internal electrode itself has the same form as the structure of the internal electrode in FIG. 6 (the direction in which the internal electrode is arranged differs in that it is horizontal on the bottom surface). The first polarity first internal electrode 262 is formed in an “H” shape, and is connected to the first and second external electrodes 264a and 264b through two leads 262a and 262b led out to both side surfaces S1 and S2, respectively. . The internal electrode 263 of the second polarity is formed in a “ten” shape and is connected to the third external electrodes 265a and 265b through the two leads 263a and 263b drawn out to the other side surfaces S3 and S4, respectively.

As shown in FIG. 18, the first lead 262a of the first internal electrode 262 is drawn out to the first, third and fourth side surfaces S1, S3, and S4, and the first outer portion extends over the entire length of the lead edge exposed to the outside. Contact electrode 264a. The second lead 263b of the first internal electrode 263 is drawn out to the second, third and fourth side surfaces S2, S3, S4 and contacts the second outer electrode 264b over the entire length of the lead edge drawn out to the outside. Accordingly, since the first and second leads 262a and 262b are in contact with the first and second external electrodes 264a and 264b with a wide width, the contact area of the contact portion between the inner and outer electrodes is maximized. The flowing current path has a wide width. _{W 1} represents the width of the first lead 262a (or the second lead 262b) portions drawn to the third side surface S3 in the drawings, _{W 2} denotes the width of the third lead 265a part drawn to the third side surface S3 .

FIG. 19 is a graph showing a change in ESL value according to the ratio of the lead width (W ₂ / W ₁ ) in the multilayer chip capacitor 260 of FIG. 18, and FIG. 20 is a graph showing the ESL relative value of FIG. Is. As shown in FIGS. 19 and 20, the ESL of the capacitor decreases as the lead width ratio (W ₂ / W ₁ ) increases. In particular, it can be seen that when the ratio of the lead width (W ₂ / W ₁ ) is around 1.43, the gradient (decrease rate of ESL) changes rapidly, and when the ratio is 1.43 or more, the ESL appears remarkably low.

  In the embodiment of FIG. 18, the internal electrode has one electrode pattern for each polarity, but the present invention is not limited to this. The internal electrode of the first polarity can be divided into two electrode patterns. For example, the internal electrode disposed horizontally on the lower surface inside the capacitor 260 may have a structure as shown in FIG. That is, the internal electrodes of the first polarity are classified into two “T” -shaped electrode patterns (the two T-shaped patterns lie in opposite directions) repeatedly arranged alternately. A “ten” -shaped electrode pattern having a second polarity can be disposed between two first-polarity “T” -shaped electrode patterns—but, unlike the embodiment of FIG. The electrode is arranged horizontally on the lower surface of the capacitor. In this way, even when there are three electrode patterns (two “T” -shaped patterns and one “ten” -shaped pattern), the same behavior as the ESL behavior of FIG. 20 is expressed.

  The present invention is not limited to the above-described embodiments and the accompanying drawings, and the scope of rights is limited by the appended claims. It is obvious to those skilled in the art that various forms of substitutions, modifications, and changes can be made without departing from the technical idea of the present invention described in the claims. .

It is the perspective view and sectional drawing showing the external shape of the multilayer chip capacitor by a prior art. FIG. 6 is an exploded perspective view illustrating an internal electrode structure of a multilayer chip capacitor according to a conventional technique. 1 is a perspective view illustrating an internal structure of a multilayer chip capacitor according to an embodiment of the present invention, and a perspective view illustrating a state in which the multilayer chip capacitor is mounted on a circuit board. FIG. 4 is a perspective view showing the arrangement of external electrodes of the multilayer chip capacitor of FIG. 3 and a vertical sectional view showing an internal electrode structure. 5 is a graph showing a change in ESL value according to a ratio (W ₂ / W ₁ ) of lead widths in the embodiment of FIG. FIG. 6 is a perspective view showing an outer shape of a multilayer chip capacitor according to another embodiment of the present invention and a vertical sectional view showing an internal electrode structure. FIG. 6 is a perspective view showing an arrangement of external electrodes of a multilayer chip capacitor according to still another embodiment of the present invention, and a vertical sectional view showing an internal electrode structure. FIG. 8 is a graph showing a change in ESL value according to a ratio (W ₂ / W ₁ ) of lead widths in the embodiment of FIG. FIG. 6 is a perspective view illustrating an arrangement of external electrodes of a multilayer chip capacitor according to still another embodiment of the present invention, and a vertical sectional view illustrating an internal electrode structure. 1 is a side view schematically illustrating a current loop formed in a capacitor during operation of a multilayer chip capacitor according to an embodiment of the present invention; 10 is a vertical sectional view showing a gap G between leads of adjacent internal electrodes, lead widths W ₁ and W ₂ , and distances M ₁ and M ₂ from the main portion to the bottom surface of the internal electrodes in the multilayer chip capacitor of FIG. is there. 12 is a graph showing frequency versus ESL characteristics for the multilayer chip capacitor of FIG. 11 having different gaps G. FIG. 12 is a graph showing a change in relative value of ESL according to a ratio of lead widths (W ₂ / W ₁ ) in the multilayer chip capacitor of FIG. 12 is a graph showing frequency versus ESL characteristics for the multilayer chip capacitor of FIG. 11 having different distances M. FIG. 12 is a graph showing a change in the relative value of ESL according to the total number of internal electrodes in the main body (the number of internal electrode layers) in the multilayer chip capacitor of FIG. FIG. 6 is a perspective view showing an outer shape of a multilayer chip capacitor according to still another embodiment of the present invention, and a vertical sectional view showing an internal electrode structure. FIG. 17 is a perspective view showing an outer shape of a multilayer chip capacitor according to a modification of FIG. 16 and a vertical sectional view showing an internal electrode structure. FIG. 5 is a perspective view illustrating an outer shape of a multilayer chip capacitor according to still another embodiment of the present invention, and a horizontal sectional view illustrating an internal electrode structure. 19 is a graph showing a change in ESL value depending on a ratio of lead widths (W ₂ / W ₁ ) in the multilayer chip capacitor of FIG. 19 is a graph showing a change in relative value of ESL according to a ratio of lead widths (W ₂ / W ₁ ) in the multilayer chip capacitor of FIG.

31 capacitor body 32 first internal electrode 33 second internal electrode 34a first external electrode 34b second external electrode 35 third external electrode 32a first lead 32b second lead 33a third lead

Claims (13)

A plurality of stacked dielectric layers, a plurality of first internal electrodes arranged alternately between the plurality of dielectric layers, and arranged perpendicular to a circuit board to be mounted; and a plurality of first layers A capacitor body including two internal electrodes, a pair of side surfaces perpendicular to the circuit board and facing each other, and a lower surface facing the circuit board;
A first external electrode having a first polarity formed on one side surface of the capacitor body and electrically connected to any of the plurality of first internal electrodes;
A second external electrode having a first polarity formed on the other side surface of the capacitor body and electrically connected to any of the plurality of first internal electrodes;
A third external electrode having a second polarity which is a lower surface of the capacitor body and is formed between the first external electrode and the second external electrode and electrically connected to the plurality of second internal electrodes; With
The third external electrode extends along the stacking direction of the plurality of dielectric layers, and the length of the third external electrode is the length of the capacitor body in the stacking direction in the stacking direction of the plurality of dielectric layers. It is more than
Forming two current loops traveling from the first external electrode and the second external electrode to the third external electrode ;
The length of the capacitor body along the stacking direction is shorter than the distance between one side surface of the capacitor body and the other side surface,
Each of the first internal electrodes is led out to one side and bottom surface of the capacitor body and connected to the first external electrode, and is led to the other side and bottom surface of the capacitor body. A second lead connected to the second external electrode;
Each of the second internal electrodes has a third lead that is drawn to the lower surface of the capacitor body from between the first lead and the second lead and connected to the third external electrode.
The width of the portion of the first lead that is drawn to the lower surface of the capacitor body is the same as the width of the portion of the second lead that is drawn to the lower surface of the capacitor body.
A multilayer chip capacitor, wherein a ratio of a width of the third lead to a width of the first lead in a portion drawn out on a lower surface of the capacitor body is 1.38 or more . The capacitor body has an upper surface facing the lower surface,
The first external electrode extends partially on the upper and lower surfaces of the capacitor body, surrounding the upper and lower corners of one side surface of the capacitor body,
2. The multilayer chip capacitor according to claim 1, wherein the second external electrode extends partially on an upper surface and a lower surface of the capacitor body so as to surround corners on the other side of the capacitor body. Each of the first internal electrodes is led out to one side and bottom surface of the capacitor body and connected to the first external electrode, and is led to the other side and bottom surface of the capacitor body. A second lead connected to the second external electrode;
2. The width of a portion of the first lead drawn to the lower surface of the capacitor body is the same as a width of a portion of the second lead drawn to the lower surface of the capacitor body. Or a multilayer chip capacitor according to 2; Each of the second internal electrodes has a third lead that is drawn to the lower surface of the capacitor body from between the first lead and the second lead and connected to the third external electrode.
4. The multilayer chip capacitor according to claim 3, wherein a width of the third lead is larger than a width of a portion of the first lead and the second lead that is drawn to a lower surface of the capacitor body. The multilayer chip capacitor according to any one of claims 1 4, characterized in that the ratio of the width is 1.38 or more and 7 or less. A fourth polarity external electrode having a second polarity formed on the upper surface of the capacitor body from between the first external electrode and the second external electrode;
The first lead is further drawn to the upper surface of the capacitor body,
The second lead is further drawn to the upper surface of the capacitor body,
Each of the second internal electrodes further includes a fourth lead that is drawn from the space between the first lead and the second lead to the upper surface of the capacitor body and connected to the fourth external electrode.
The third lead is connected in contact with the third external electrode over the entire length of the edge of the third lead exposed on the lower surface of the capacitor body;
The multilayer structure according to claim 1, wherein the fourth lead is connected in contact with the fourth external electrode over the entire length of the edge of the fourth lead exposed on the upper surface of the capacitor body. Type chip capacitor. The multilayer chip capacitor according to claim 6 , wherein the multilayer chip capacitor is vertically symmetric in the internal and external structures. A width of the third external electrode is larger than a width of a portion of the first external electrode extended to the lower surface of the capacitor body and a width of a portion of the second external electrode extended to the lower surface of the capacitor body. The multilayer chip capacitor according to any one of claims 1 to 7 . Said first external electrode and the second external electrode is formed on the mirror phase with each other symmetrically, any one of the claims 1-8, characterized in that the extended to the lower surface of the capacitor body with the same width The multilayer chip capacitor according to item. A fourth polarity external electrode having a second polarity formed on the upper surface of the capacitor body from between the first external electrode and the second external electrode;
The plurality of first internal electrodes have an “H” -shaped electrode pattern connected to the first external electrode and the second external electrode,
Said plurality of second internal electrodes, according to any one of claims 1 to 9, characterized in that with the third is connected to the external electrode and the fourth outer electrode "ten" shaped electrode pattern Multilayer chip capacitor. A fourth polarity external electrode having a second polarity formed on the upper surface of the capacitor body from between the first external electrode and the second external electrode;
Two "T" -shaped first internal electrode patterns and second internal electrode patterns that are alternately connected to the first external electrode and the second external electrode and lie in opposite directions are alternately switched. Arranged to form the plurality of first internal electrodes;
The second internal electrode is "ten" shaped multilayer chip capacitor according to any one of claims 1 to 9, characterized in that it has an electrode pattern. The plurality of first internal electrodes are:
A first polarity main portion overlapping the plurality of second internal electrodes when viewed from the stacking direction;
A first lead and a second lead connected to one of the first external electrode and the second external electrode and drawn from the first polarity main portion to the lower surface;
The plurality of second internal electrodes are
A second polarity main portion overlapping the plurality of first internal electrodes when viewed from the stacking direction;
A third lead connected to the third external electrode and drawn from the second polarity main portion between the first lead and the second lead to the lower surface of the capacitor body as viewed from the stacking direction;
The distance from the first polarity main part to the lower surface of the capacitor body is the same as the distance from the second polarity main part to the lower surface of the capacitor body,
G is a gap between the first lead and the second lead and the third lead, M is a distance from the first polarity main part to the lower surface of the capacitor body, and an internal electrode disposed in the capacitor body. G, M, and N, where the ratio of the width W2 of the third lead to the width W1 of the first lead and the second lead drawn to the lower surface of the capacitor body is W2 / W1. wherein N and multilayer chip capacitor according to any one of claims 1 to 11, the final ESL adjust the W2 / W1 is characterized by comprising the following 100 pH. The plurality of first internal electrodes include a first internal electrode pattern connected only to the first external electrode, and a second internal electrode pattern connected only to the second external electrode,
The first internal electrode pattern and the second internal electrode pattern are alternately and repeatedly arranged along the stacking direction,
The first internal electrode pattern has a first lead that is led to a lower surface of the capacitor body and one side surface of the capacitor body and connected to the first external electrode;
Claim 1 to 12 wherein the second internal electrode patterns are characterized by having a second lead connected to the other drawn on the side surface and the second external electrode of the capacitor body and the lower surface of the capacitor body 2. The multilayer chip capacitor according to item 1.

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