JP5234806B2 - Logic simulation apparatus and simulation method thereof - Google Patents

Description

  The present invention relates to a logic simulation apparatus and a simulation method thereof, and more particularly to a logic simulation apparatus and a simulation method for a large-scale circuit design using a device such as an FPGA (Field Programmable Gate Array).

  In recent years, large-scale circuit design has become possible due to improvements in the technology of devices such as FPGAs. On the other hand, in the simulation of circuit design (for example, logic simulation), the function to simulate is increasing more than before. On the other hand, the simulation environment has been improved, and it has become possible to simulate even a large-scale circuit in a relatively short time.

  FIG. 8 is a block diagram of an example of a logic simulation apparatus related to the present invention. Referring to the figure, an example of a related logic simulation device includes a function specification unit 1, a hardware description language (HDL) description generation unit 2, a logic simulation (SIM) unit 5, and a logic synthesis unit. 3, a layout unit 4, an application specific integrated circuit (ASIC) unit 6, and a field programmable gate array (FPGA) unit 7.

  The function specification section 1 describes functions to be realized. The hardware language description generation unit 2 performs hardware language description based on the functions described in the function specification unit 1. The logic simulation unit 5 performs logic verification of the HDL created by the hardware language description generation unit 2 and executes a simulation to check whether the function described in the function specification unit 1 is realized. When the logic simulation unit 5 confirms that there is no problem in operation, the logic synthesis unit 3 performs logic synthesis, the layout unit 4 performs layout, and the ASIC unit 6 or the FPGA unit 7. Is generated.

  FIG. 9 is a configuration diagram of a part of a circuit in the hardware language description generation unit 2 as an example of a related logic simulation device, and a counter generation block 50 as an example. Referring to the figure, the counter generation block 50 includes a counter (for example, an N-bit counter (N is a positive integer)) 51, a data register (ALL “0”) 52 set as an initial value, and a counter output. A maximum value (MAX value) 53 and a clock 54 are included. Therefore, in the logic simulation in the logic simulation unit 5, it is necessary to check the operation by fully counting N bits.

  FIG. 10 is a time chart showing the operation of the N-bit counter 51 in an example of a related logic simulation apparatus. The figure shows an example of a 16-bit counter (N = 16). In synchronization with the clock 54, the counter 51 is sequentially counted up from an initial value “0000” to “FFFFh (h is a hexadecimal number)”. When the count value reaches the MAX value, that is, “FFFFh”, it is cleared (“0000”). This figure shows that such a 16-bit counter takes “16536 clocks (CLK)” to count from “0000” to “FFFFh”.

  On the other hand, as an invention related to the present invention, an example of a test circuit adding device for a semiconductor integrated circuit is disclosed in Patent Document 1. This is based on the circuit state obtained by the failure simulation using the test pattern, searching for multiple undetected failure propagation paths, detecting the optimum test circuit insertion position from the searched circuit, and detecting the detected signal. By adding a test additional circuit that performs parity check while taking timing into consideration, a test circuit can be automatically and efficiently inserted at the optimal position to find a fault that could not be found by fault simulation using existing test patterns. It is to detect.

  An example of a test circuit for the counter circuit is disclosed in Patent Document 2. This relates to a test circuit that shortens the test time of the counter circuit. The counter circuit is divided into a plurality of blocks (for example, one block of 4 bits), and the test circuit transfers “1111” for each block of the counter circuit. Then, the test circuit counts up the counter circuit and checks whether or not a carry is performed. Then, when the carry is carried and the count value is “0000” and the adjacent upper bits are “1”, it is determined as normal. This is executed for each block.

Japanese Patent Laid-Open No. 06-148292 JP 2001-352239 A

  However, in the related techniques described in FIGS. 8 to 10, there is a problem that the time spent for simulation becomes enormous as the value of “N” increases. In other words, the specification of a circuit that requires “insignificant time” just waiting until the simulation result is known leads to a delay in the simulation confirmation.

  On the other hand, the invention described in Patent Document 1 is common to the present invention in that a test circuit is added, but its purpose is to find a failure that cannot be found by a failure simulation based on an existing test pattern. The object is completely different from the present invention. Therefore, the object of the present invention to shorten the logic simulation time cannot be obtained from the invention described in Patent Document 1.

  The invention described in Patent Document 2 is common to the present invention in that the test time of the counter circuit is shortened, but only the counter circuit and the test circuit are described in Patent Document 2. The counter circuit and the test circuit correspond to a test mode specification unit 10-2 of the present invention described later. On the other hand, Patent Document 2 does not describe a configuration corresponding to a functional specification unit 10-1 of the present invention described later.

  The present invention is characterized in that logic simulation is performed using the test mode specification unit 10-2 together with the function specification unit 10-1 from the HDL design stage. That is, since the circuit can be designed in consideration of the test mode from the design stage, there is an effect that there is little backtracking from the logic simulation. Therefore, from the invention described in Patent Document 2 that does not have a configuration corresponding to the function specification unit 10-1, the logic simulation time of a part of the function specification unit 10-1 is shortened using the test mode specification unit 10-2. The effect of the present invention is not obtained.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a logic simulation apparatus and a simulation method thereof that can shorten the logic simulation time as compared with the related art.

In order to solve the above problems, a logic simulation apparatus according to the present invention includes a function specification section in which a predetermined function is described, and a test mode in which a test function for reducing the execution time of a part of the predetermined function is described. A hardware language generated by the specification language, a hardware language description generation unit for performing a hardware language description for realizing the predetermined function and the test function based on the function specification unit and the test mode specification unit, and a hardware language generated by the hardware language description generation unit A logic simulation unit that performs logic verification of the description, and the logic simulation is performed using the test mode specification unit together with the function specification unit from the hardware language design stage.

Further, the simulation method according to the present invention includes a function specification section in which a predetermined function is described, a test mode specification section in which a test function for shortening an execution time of a part of the predetermined function is described, and the function specification A logic simulation apparatus simulation method comprising: a hardware language description generating unit for performing a hardware language description for realizing the predetermined function and the test function based on a test unit and a test mode specification unit; and a logic simulation unit, wherein the logic simulation is performed. The unit includes a logic verification step for performing logic verification of the hardware language description generated by the hardware language description generation unit, and logic simulation is performed using the test mode specification unit together with the function specification unit from the hardware language design stage. It is characterized by that.

Further, the program according to the present invention includes a function specification part in which a predetermined function is described, a test mode specification part in which a test function for shortening an execution time of a part of the predetermined function is described, and the function specification part And a simulation method of a logic simulation device including a hardware language description generating unit for performing a hardware language description for realizing the predetermined function and the test function based on a test mode specification unit, and a logic simulation unit, It is for causing a simulation unit to execute a logic verification step for performing logic verification of the hardware language description generated by the hardware language description generation unit, and the test mode specification unit together with the function specification unit from the hardware language design stage A logic simulation is performed using.

  According to the present invention, the logic simulation time can be shortened compared to the related art by having the above configuration.

It is a block diagram which shows the operation principle of the logic simulation apparatus which concerns on this invention. 1 is a configuration diagram of a first embodiment of a logic simulation apparatus according to the present invention. 3 is a configuration diagram of a circuit counter generation block 200 and a counter value test load circuit 100 in the hardware language description generation unit 11 of the first embodiment of the logic simulation apparatus according to the present invention. FIG. It is a flowchart which shows operation | movement of 1st Example. 3 is a time chart showing an example of the operation of a counter 201. It is a block diagram of the test circuit of 2nd Example of this invention. It is a timing chart which shows operation | movement of 2nd Example of a logic simulation object circuit. It is a block diagram of an example of the logic simulation apparatus relevant to this invention. It is a block diagram of the counter production | generation block 50 in the hard language description production | generation part 2 of an example of a related logic simulation apparatus. It is a time chart which shows operation | movement of the N bit counter 51 in an example of a related logic simulation apparatus.

  First, the operating principle of the present invention will be described before the description of the embodiments of the present invention. FIG. 1 is a block diagram showing the operation principle of a logic simulation apparatus according to the present invention. Referring to FIG. 1, the logic simulation apparatus according to the present invention includes a function specification unit 10-1, a test mode specification unit 10-2, a hardware language description generation unit 11, and a logic simulation unit 14. The

  The function specification section 10-1 describes a predetermined function. The test mode specification section 10-2 describes a test function for shortening the execution time of a part of the predetermined functions. The hardware language description generation unit 11 performs hardware language description based on the function specification unit 10-1 and the test mode specification unit 10-2. The logic simulation unit 14 performs logic verification of the hardware language description generated by the hardware language description generation unit 11.

  As described above, in the present invention, the logic simulation unit 14 includes the test function specification unit 10-2 in which the test function for shortening the execution time of a part of the predetermined function is described. 1 and the test mode specification unit 10-2 are used to perform a logic simulation, whereby the logic simulation time can be shortened.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

  FIG. 2 is a block diagram of the first embodiment of the logic simulation apparatus according to the present invention. In the figure, the same components as those in FIG. Referring to FIG. 2, the logic simulation apparatus according to the first embodiment of the present invention includes a specification unit 10, a hardware language (HDL) description generation unit 11, a logic simulation (SIM) unit 14, a logic synthesis unit 12, , The layout unit 13, the ASIC unit 15, the FPGA unit 16, and the program storage unit 17. The specification unit 10 includes a function specification unit 10-1 and a test mode specification unit 10-2.

  The function specification section 10-1 describes a predetermined function. The test mode specification section 10-2 describes a test function for shortening the execution time of a part of the predetermined functions. That is, the test mode specification unit 10-2 examines a location (in the present invention, a counter as an example) that is likely to require a lot of time from the function realized by the function specification unit 10-1. This is a specification document that describes the content of adding a test circuit to the determined location.

  The hardware language (HDL) description generation unit 11 performs hardware language description based on the function specification unit 10-1 and the test mode specification unit 10-2. The logic simulation unit 14 performs logic verification of the HDL created by the hardware language description generation unit 11, and determines whether or not the functions described in the function specification unit 10-1 and the test mode specification unit 10-2 are realized. Check by running a simulation. When the logic simulation unit 14 confirms that there is no problem in operation, the logic synthesis unit 12 performs logic synthesis, the layout unit 13 performs layout, and the ASIC unit 15 or the FPGA unit 16. Is generated.

  FIG. 3 is a block diagram of a part of a circuit in the hard language description generation unit 11 of the first embodiment of the logic simulation apparatus according to the present invention, for example, a counter generation block 200 and a counter value test load circuit 100. The counter generation block 200 corresponds to the counter generation block 50 (see FIG. 7) of the related art. A feature of the present invention is that a counter value test load circuit 100 is added to the counter generation block 200.

  Referring to FIG. 3, the counter generation block 200 has a counter (for example, an N-bit counter (N is a positive integer)) 201, a data register 52 in which a first initial value is set, and a second initial value. A test dedicated register (N bit) 202, a counter output maximum value (MAX value) 53, and a clock 54. In addition, ALL “0” is set in the data register 52, that is, “0000” is preset as an example in the present embodiment, and “FFFEh” is preset as an example in the test dedicated register 202. This “FFFEh” is a count value immediately before the timing to be confirmed in the logic simulation, for example.

  On the other hand, the counter value test load circuit 100 includes a selector 102, an AND gate 101, a test load (TEST LD) terminal 111, and a test (TEST) terminal 112. The output of the AND gate 101 is input to the selection input terminal (SEL) of the selector 10. A test load permission signal from a test-dedicated register (not shown) is input to one of the two inputs of the AND gate 101, and a test signal from a test (TEST) terminal 112 is input to the other. On the other hand, “1” from the test load (TEST LD) terminal 111 and “0” from the outside are input to the selector 102.

  The test (TEST) terminal 112 is for validating the test circuit. When the test signal from the test (TEST) terminal 112 and the test load permission signal are input to the AND gate 101, the AND condition is satisfied, and the AND A test load signal is input from the gate 101 to the selection input terminal (SEL) of the selector 102. When this test load signal is input to the selector 102, the output from the selector 102 changes from "0" (normal mode) to "1" (test mode).

  On the other hand, when the output “0” (normal mode) is input from the selector 102 to the LD2 terminal of the counter 201, the first initial value “0000” is set as the initial setting value of the counter 201, and the output “1” is output from the selector 102. When (test mode) is input to the LD2 terminal of the counter 201, the counter generation block 200 is configured such that the second initial value “FFFEh” is set as the initial setting value of the counter 201.

  Next, the operation of the counter generation block 200 will be described in detail. FIG. 4 is a flowchart showing the operation of the first embodiment, and FIG. 5 is a time chart showing an example of the operation of the counter 201. The following operation is executed by the logic simulation unit 14 in FIG. 2 controlling the hardware language description generation unit 11. The program storage unit 17 in FIG. 2 will be described later.

  First, the operation in the normal mode will be described. Since it is not the test mode (“No” in step S1 in FIG. 4), the first initial value is set in the counter 201 as the initial value. Next, the operation (step S5 in FIG. 4) for setting the first initial value in the counter 201 as the initial value will be described.

  Referring to FIG. 3, in this case, at least the test load permission signal is not input to the AND gate 101 of the counter value test load circuit 100. Therefore, the AND condition is not satisfied, and the test load signal from the AND gate 101 is not input to the selection input terminal (SEL) of the selector 102. As a result, the output “0” (normal mode) is input from the selector 102 to the LD 2 terminal of the counter 201. When “0” is input to the LD2 terminal, the counter 201 sets the first initial value “0000” as the initial setting value (step S5 in FIG. 4).

  Next, the counter 201 starts counting (step S3 in FIG. 4). Next, the count-up operation will be described. When the clock 54 is input to the CLK terminal of the counter 201, the counter 201 sequentially counts from “0000” to “FFFFh”, and when the count value reaches the maximum value “FFFFh”, that is, the maximum value (MAX value) 53 ( In step S4 of FIG. 4, “Yes”), the count value is cleared (“0000”), and the operation is terminated.

  If the count value is not the maximum value “FFFFh”, that is, the maximum value (MAX value) 53 (“No” in step S4 in FIG. 4), the process stays at step S4 until the count is increased. On the other hand, it is also possible to return to step S5 from step S4 “Yes” without causing the operation to end, and to perform the counting operation again. Therefore, in this case, it takes 16536 CLK to count from “0000” to “FFFFh” (see FIG. 8).

  Next, the operation in the test mode will be described. Since it is the test mode (“Yes” in step S1 in FIG. 4), the second initial value is set in the counter 201 as the initial value. Next, the operation (step S2 in FIG. 4) for setting the second initial value in the counter 201 as the initial value will be described.

  Referring to FIG. 3, in this case, a test load permission signal and a test signal from the test terminal 112 are input to the AND gate 101 of the counter value test load circuit 100. Therefore, the AND condition is satisfied, and the test load signal is input from the AND gate 101 to the selection input terminal (SEL) of the selector 102. As a result, the output “1” (test mode) is input from the selector 102 to the LD 2 terminal of the counter 201. When “1” is input to the LD2 terminal, the counter 201 sets a second initial value (for example, “FFFEh”) as an initial setting value (step S2 in FIG. 4).

  Next, the counter 201 starts counting (step S3 in FIG. 4). Next, the count-up operation will be described. When the clock 54 is input to the CLK terminal of the counter 201, the counter 201 counts up to “0000” and “0001”, then jumps to “FFFEh” and counts up to “FFFFh”. The count value is the maximum value “FFFFh”. ", That is, when the maximum value (MAX value) 53 is reached (" Yes "in step S4 in FIG. 4), the count value is cleared (" 0000 ") and the operation ends.

  If the count value is not the maximum value “FFFFh”, that is, the maximum value (MAX value) 53 (“No” in step S4 in FIG. 4), the process stays at step S4 until the count is increased. On the other hand, it is also possible to return to step S2 from step S4 “Yes” without terminating the operation, and to perform the counting operation again. Therefore, in this case, counting from “0000” to “FFFFh” is completed at 4 CLK (see FIG. 5).

  In the first embodiment, “FFFEh” is exemplified as the second initial value. However, the present invention is not limited to this, and any value that is larger than the first initial value may be set as the second initial value. Can be set as In the first embodiment, a 16-bit counter is used as an example. However, the present invention is not limited to this, and the present invention can be applied to a counter having an arbitrary number of bits.

  As described above, according to the first embodiment of the present invention, since the initial value of the counter can be changed to a value larger than “0”, the count can be quickly rotated. Time can be reduced compared to related technologies.

  That is, according to the first embodiment of the present invention, the counter operation can be freely operated, so that the simulation can be efficiently performed and the time can be greatly reduced. For example, when a test circuit is added to a 16-bit counter, the counter can be rotated once in a normal 1/32768 (when “FFFFh” is loaded). Furthermore, since the counter load value can be determined arbitrarily, it can be used effectively when it is desired to shorten the time to the point to be confirmed by simulation.

  Although the first embodiment has been described with respect to the rapid rotation of the counter, it is possible to reduce the logic simulation time by providing a test circuit other than the counter. In the second embodiment, a case will be described in which the present invention is applied to a circuit that operates based on signals generated in other blocks such as an interrupt signal.

  In a circuit that operates on the basis of a signal created in another block, such as an interrupt signal, the interrupt signal or the like is generated only under certain conditions. Therefore, an interrupt signal or the like is not generated until a certain condition is met. Therefore, when a logic simulation is performed on this circuit, it is necessary to wait until the certain condition is met. Therefore, there is a problem that the time spent for simulation becomes enormous.

  Therefore, in the second embodiment of the present invention, a condition (necessary state and valid data) for generating an interrupt signal or the like is intentionally created using a test interrupt signal, and this is used as a test mode specification section 10-2. Describe. Therefore, when the test mode is selected, an interrupt signal or the like is generated immediately.

  FIG. 6 is a block diagram of the test circuit of the second embodiment of the present invention, and FIG. 7 is a timing chart showing the operation of the second embodiment of the logic simulation target circuit. The test circuit 300 in FIG. 6 corresponds to the counter value test load circuit 100 in FIG. 3 (first embodiment). Also, the circuit corresponding to the counter generation block 200 in FIG. 3 (first embodiment) is a logic simulation target circuit whose operation is shown in FIG.

  Referring to FIG. 6, the test circuit 300 includes a selector 303, AND gates 301 and 302, a test interrupt terminal 304, and a test (TEST) terminal 305. The selector 303 receives the test interrupt signal “1” from the test interrupt terminal 304 and the internal interrupt signal “0” which is the output of the AND gate 301. The output signal of the AND gate 302 is input to the selection input terminal (SEL) of the selector 303.

  The factor A signal is input to one of the two inputs of the AND gate 301, and the factor B signal is input to the other. A test load permission signal from a test-dedicated register (not shown) is input to one of the two inputs of the AND gate 302, and a test signal from a test (TEST) terminal 305 is input to the other.

  The test interrupt terminal 304 is for inputting a test interrupt signal “1” to the selector 303 in order to validate the test circuit. When the test signal and the test load permission signal from the test (TEST) terminal 305 are input to the AND gate 302, the AND condition is satisfied, and the test load signal is input from the AND gate 302 to the selection input terminal (SEL) of the selector 303. The

  On the other hand, the factor A signal and the factor B signal are interrupt generation condition signals, and these signals are input to the AND gate 301. When the factor A signal and the factor B signal are input to the AND gate 301, the AND condition is satisfied, and the internal interrupt signal “0” is input from the AND gate 302 to the selector 303.

  On the other hand, the output from the selector 303 is input to a logic simulation target circuit (not shown). Next, operations of the selector 303 and the logic simulation target circuit will be described with reference to FIG.

  First, the operation in the normal mode will be described. In this case, since at least one of the two input signals of the AND gate 302 is not input to the AND gate 302, the AND condition is not satisfied. Therefore, the selector 303 selects “0” and the signal “0” is output from the selector 303. Is done. Since “0” is a mode in which an interrupt is generated under the conditions of normal factor A and factor B, referring to FIG. 7, an interrupt is generated in the logic simulation target circuit at time T2 when both the conditions of factor A and factor B are satisfied. It will be.

  On the other hand, in the case of the test mode operation, the two input signals of the AND gate 302 are both input to the AND gate 302, so that the AND condition is satisfied. Therefore, the selector 303 selects “1” and the signal “1”. Is output from the selector 303. Since the signal “1” is a mode in which an interrupt is generated by a test interrupt, referring to FIG. 7, when a test interrupt signal “1” is generated, that is, at time T1 (T1 <T2), an interrupt is generated in the logic simulation target circuit. become. Therefore, in the test mode, an interrupt can be generated earlier than in the normal mode.

  As described above, according to the second embodiment of the present invention, a condition (necessary state and valid data) for generating an interrupt signal or the like is intentionally created, and this is generated by the test mode specification section 10-2. Therefore, the logic simulation time can be shortened as compared with the related art.

  The third embodiment relates to a program for a simulation method of a logic simulation apparatus. As described above, the logic simulation apparatus according to the present invention includes the program storage unit 17 (see FIG. 2). The program storage unit 17 stores a simulation method program of the logic simulation apparatus shown in the flowchart of FIG.

  The logic simulation unit 14 of the logic simulation apparatus reads the program from the program storage unit 17 and controls the hardware language description generation unit 11 according to the program. Since the contents of the control have already been described, the description thereof is omitted here.

  As described above, according to the third embodiment of the present invention, it is possible to obtain a program capable of reducing the logic simulation time as compared with the related art.

  The present invention can be applied to a case where a simulation is performed by VHDL (VHSIC Hardware Description Language, VHSIC: Very High Speed Integrated Circuit), Verilog-HDL (Verilog: logic simulator for designing a digital circuit), or the like.

10 Specification part 10-1 Function specification part 10-2 Test mode specification part
11 Hardware language description generator
12 Logic synthesis part
13 Layout section
14 Logic simulation part
15 ASIC Department
16 FPGA part
17 Program storage
52 Data register
53 Maximum counter output
54 clocks
100 Counter value test load circuit
101 AND gate
102 selector
111 Test load terminal
112 Test (TEST) terminal
200 Counter generation block
201 counter
202 Test dedicated register
300 Test circuit 301, 302 AND gate
303 selector
304 Test interrupt terminal
305 Test terminal

Claims (18)

A functional specification part in which a predetermined function is described;
A test mode specification part in which a test function for shortening the execution time of a part of the predetermined function is described;
A hardware language description generation unit for performing a hardware language description for realizing the predetermined function and the test function based on the function specification unit and the test mode specification unit;
A logic simulation unit that performs logic verification of the hardware language description generated by the hardware language description generation unit,
A logic simulation apparatus, wherein logic simulation is performed using the test mode specification unit together with the function specification unit from the design stage of a hardware language.   2. The logic simulation according to claim 1, wherein the logic simulation unit uses the test function described in the test mode specification unit when it is necessary to shorten an execution time of a part of the predetermined function. apparatus.   3. The logic simulation apparatus according to claim 1, wherein the test function is for a counter.   4. The logic simulation apparatus according to claim 3, wherein the test function is operated by changing an initial value set in the counter to a value exceeding a standard value.   3. The logic simulation apparatus according to claim 1, wherein the test function is for a function that operates based on an interrupt signal or the like.   6. The logic simulation apparatus according to claim 5, wherein the test function is for generating an interrupt signal or the like earlier than a preset time. Based on the function specification part in which the predetermined function is described, the test mode specification part in which the test function for reducing the execution time of a part of the predetermined function is described, and the function specification part and the test mode specification part A logic language simulation apparatus including a hardware language description generation unit for performing a hardware language description for realizing the predetermined function and the test function, and a logic simulation unit,
The logic simulation unit includes a logic verification step for performing logic verification of the hardware language description generated by the hardware language description generation unit,
A simulation method characterized in that a logic simulation is performed using the test mode specification unit together with the function specification unit from the design stage of a hardware language.   The simulation method according to claim 7, wherein the logic simulation unit uses a test function described in the test mode specification unit when it is necessary to shorten an execution time of a part of the predetermined function. . 9. The simulation method according to claim 7, wherein the test function is for a counter.   The simulation method according to claim 9, wherein the test function operates by changing an initial value set in the counter to a value exceeding a standard value.   9. The simulation method according to claim 7, wherein the test function is for a function that operates based on an interrupt signal or the like.   12. The simulation method according to claim 11, wherein the test function is for generating an interrupt signal or the like earlier than a preset time. Based on the function specification part in which the predetermined function is described, the test mode specification part in which the test function for reducing the execution time of a part of the predetermined function is described, and the function specification part and the test mode specification part A simulation method of a logic simulation device including a hardware language description generation unit for performing a hardware language description for realizing the predetermined function and the test function, and a logic simulation unit,
For causing the logic simulation unit to execute a logic verification step for performing logic verification of the hardware language description generated by the hardware language description generation unit;
A program in which logic simulation is performed using the test mode specification unit together with the function specification unit from the design stage of a hardware language.   14. The program according to claim 13, wherein the logic simulation unit uses a test function described in the test mode specification unit when it is necessary to shorten an execution time of a part of the predetermined function.   15. The program according to claim 13, wherein the test function is for a counter.   16. The program according to claim 15, wherein the test function is to operate by changing an initial value set in the counter to a value exceeding a standard value.   15. The program according to claim 13, wherein the test function is for a function that operates based on an interrupt signal or the like.   18. The program according to claim 17, wherein the test function is for generating an interrupt signal or the like earlier than a preset time.

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