JP5242736B2 - Semiconductor package mounting structure - Google Patents

Description

The present invention relates to a mounting structure of a semiconductor package and a semiconductor package, constituting the PGA (pin grid array) type semiconductor packages and which is formed by bonding a pin attached substrate to the wiring board by mounting the socket more about the implementation structure of the semiconductor package to be.

  As a PGA type semiconductor package, there is a product formed by bonding a substrate with a pin to a wiring substrate as shown in FIG. 7A shows a state in which the pinned substrate 20 is aligned with the wiring substrate 10, and FIG. 7B shows a semiconductor package 30 formed by bonding the pinned substrate 20 to the wiring substrate 10. FIG. The wiring board 10 in the illustrated example is a build-up board in which a wiring pattern 12 and a via 14 are formed in an inner layer, and a pin connection pad 16 is formed on one surface to which the pinned substrate 20 is bonded, and the other surface is formed. Pads 17 for joining the semiconductor elements are formed.

  The substrate with pins 20 is formed by supporting pins 22 to be bonded to the pads 16 formed on the wiring substrate 10 on a substrate 24 formed in a thin flat plate shape. The head portion 22a of the pin 22 is provided in the same planar arrangement as the pad 16 of the wiring substrate 10, and the semiconductor portion 30 is bonded to the pin connection pad 16 by the solder 18 supplied to the pad 16. Is formed.

In addition, as a PGA type semiconductor package, a semiconductor package in which a substrate with pins is prepared separately from a wiring substrate and the substrate with pins is joined to the wiring substrate has been proposed (for example, see Patent Documents 1 and 2). ).

JP-A-7-169876 JP-A-7-106461

  By the way, when mounting a PGA type semiconductor package on a socket, the semiconductor package is mounted so as to be inserted into a frame-shaped set portion provided on the socket. A base plate is provided on the lower side of the set portion in which contacts that contact the pins are arranged in accordance with the planar arrangement of the pins. When the semiconductor package is mounted on the set part, the semiconductor package is mounted so that the outer position of the semiconductor package is guided by the inner surface of the set part. In some cases, a guide protrusion is provided on the inner side surface of the set portion so as to be in contact with the outer side surface of the semiconductor package.

In this way, when mounting a semiconductor package in a socket, the semiconductor package is mounted on the inner surface of the set part with its outer shape aligned, so in the case of a PGA type semiconductor package, the package body's outer shape (outer dimensions) is accurate. Need to be formed.
In the former PGA type semiconductor package, where the wiring board itself is formed thick and the pins are inserted into the pin mounting holes provided in the wiring board, the semiconductor package is positioned by defining the external dimensions of the wiring board itself. Can do. On the other hand, in the semiconductor package 30 shown in FIG. 7, the external shapes of the wiring substrate 10 and the pinned substrate 20 are matched, the wiring substrate 10 and the pinned substrate 20 are aligned and joined, and the semiconductor package is socketed. When mounted on the board, the outer surface of the wiring substrate 10 and the outer surface of the substrate with pins 20 are mounted as guide positions (positioning positions).
When soldering the wiring substrate 10 and the pinned substrate 20 to each other, the wiring substrate 10 and the pinned substrate 20 are supported by a supporting jig, and the wiring substrate 10 and the pinned substrate 20 are aligned by the supporting jig. In this state, the solder reflow device is transferred and joined. In this soldering operation, the wiring substrate 10 and the pinned substrate 20 are not necessarily displaced. Therefore, even if the outer dimensions of the wiring substrate 10 and the pinned substrate 20 are formed with high accuracy, the outer shape of the semiconductor package 30 is not limited. It is inevitable that the dimensions vary. The variation in the external dimensions of the semiconductor package 30 is a result of superposition of positional deviation due to soldering and manufacturing tolerances of the wiring substrate 10 and the substrate with pins 20.

In recent years, an extremely thin semiconductor package has been provided. In a semiconductor package formed by bonding a substrate with a pin to a wiring substrate, a very thin wiring substrate having a thickness of 1 mm or less is used. It has become like this. If the wiring board is thinned in this way, the strength of the wiring board itself is reduced and the wiring board is warped. Therefore, the wiring board is reinforced by a substrate with pins to suppress warping of the semiconductor package. It is being considered.

An object of the present invention is to provide a thin semiconductor package in which warpage is suppressed and a mounting structure of the semiconductor package including the thin semiconductor package.

In order to achieve the above object, the present invention comprises the following arrangement.
That is, a board with pins to which pins are attached and a wiring board on which pads for connecting pins are formed. The board with pins is provided with the pins standing up integrally with a resin board formed by resin molding. One end of the pin is exposed from one surface of the resin substrate, the other end of the pin extends from the other surface of the resin substrate, and the outer shape of the wiring substrate is the pin Larger than the outer shape of the substrate with a pin, the one end of the pin and the pin connection pad are bonded, the substrate with the pin and the wiring substrate are bonded, and the outer surface of the wiring substrate has the pin The semiconductor package is characterized by extending outward from the outer surface of the substrate.

In addition, a semiconductor package having a substrate with pins to which pins are attached, a wiring substrate on which pads for pin connection are formed, a set recess in which the semiconductor package is accommodated, and the pins and the electrical contacts below the set recess A socket provided with a contact to be connected to the substrate, and the pin-attached substrate is formed by integrally standing the pin on a resin substrate formed by resin molding, and from one surface of the resin substrate One end of the pin is exposed, and the other end of the pin extends from the other surface of the resin substrate. In the semiconductor package, the outer shape of the wiring substrate is larger than the outer shape of the substrate with pins. The one end of the pin and the pad for connecting the pin are joined, the substrate with the pin and the wiring substrate are joined, and the outer surface of the wiring substrate is attached with the pin A semiconductor, wherein the semiconductor package extends outside the outer surface of the substrate and is inserted into the inner surface of the set recess with the outer surface of the wiring substrate being guided and inserted into the socket. This is a package mounting structure.

Here, a head portion is formed at one end portion of the pin, and an end surface of the head portion is exposed flush with one surface of the resin substrate, and the end surface of the head portion and the pin The pad for connection is joined, and the substrate with pins and the wiring substrate are joined.
In addition, the substrate with pins is slid into the other end portion, covers the end face of the one end portion, fills the mold cavity with the pins set therein, and fills the resin substrate with resin. The pins are integrally formed upright.

According to the present invention, it is possible to provide a thin semiconductor package in which warpage is suppressed and a semiconductor package mounting structure including the same.
By using the outer surface of the wiring board for positioning, the wiring board and the board with pins can be accurately positioned regardless of the amount of positional deviation. That is, the semiconductor package can be positioned and inserted into the socket according to the external accuracy of the wiring board.
The inner surface of the set recess for guiding and setting the semiconductor package serves to position the semiconductor package. In addition to simply forming the semiconductor package on a flat surface, guides such as guide protrusions for positioning the outer position of the semiconductor package are provided. Including the case where the part is formed.

It is sectional drawing which shows the structure of 1st Embodiment of a semiconductor package. It is sectional drawing which shows the state which mounts a semiconductor package in a socket. It is sectional drawing which shows the mounting structure of a semiconductor package. It is explanatory drawing which shows the manufacturing method of the board | substrate with a pin used in 1st Embodiment. It is sectional drawing which shows the structure of 2nd Embodiment of a semiconductor package. It is sectional drawing which shows the mounting structure of a semiconductor package. It is sectional drawing which shows the structure of the conventional semiconductor package.

Hereinafter, a semiconductor package mounting structure and a preferred embodiment of a semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings.
(Semiconductor package)
FIG. 1 is a cross-sectional view showing the configuration of a first embodiment of a semiconductor package according to the present invention. The semiconductor package 40 shown in FIG. 1 is formed by bonding the wiring substrate 10 and the pinned substrate 25 in the same manner as the semiconductor package 30 shown in FIG. 7B. A characteristic configuration of the semiconductor package 40 of the present embodiment is that the outer dimension of the substrate 25 with pins is set larger than the outer dimension of the wiring substrate 10, and the outer surface (also referred to as “outer peripheral surface”) of the substrate 25 with pins. Is the planar positional relationship located outside the outer surface (also referred to as “outer peripheral side surface”) of the wiring board 10.

  The configuration of the wiring board 10 is the same as that of the wiring board 10 shown in FIG. 7, and an insulating layer 13 and a wiring pattern 12 (wiring layer) are formed by being laminated in a plurality of layers, and the wiring pattern 12 is electrically connected to the insulating layer 13 between the layers. The vias 14 are connected to each other. One side of the wiring board 10 to which the pinned substrate 25 is bonded is covered with the solder resist layer 15a by exposing the pin connection pad 16 to which the head portion 22a of the pin 22 is bonded. This surface is covered with a solder resist layer 15b with the pads 17 electrically connected to the semiconductor element exposed. The wiring board 10 of the present embodiment is a coreless board formed by a build-up method, but the manufacturing method of the wiring board 10, the number of laminated wiring patterns 12 formed on the wiring board 10 are not limited.

  Similarly to the pinned substrate 20 shown in FIG. 7, the pinned substrate 25 has pins 22 arranged in the same plane arrangement as the pads 16 formed on the wiring substrate 10. The substrate with pins 25 of the present embodiment is formed by standing the pins 22 integrally with a resin substrate 26 formed by resin molding with both surfaces being flat surfaces. The pin 22 is attached so that the end surface (top surface) of the head portion 22a formed at one end is exposed flush with the surface of the resin substrate 26 on the side facing the wiring substrate 10, and the other end of the pin 22 is It extends downward from the resin substrate 26.

  The semiconductor package 40 shown in FIG. 1 supplies the solder 18 to the pin connection pad 16 formed on the wiring substrate 10, aligns the wiring substrate 10 and the pinned substrate 25, and performs the solder reflow process to perform the wiring substrate. 10 and the pinned substrate 25 are formed by soldering. Of course, as a bonding material for bonding the wiring substrate 10 and the pinned substrate 25, a conductive material including a conductive sheet other than solder can be used.

(Semiconductor package mounting structure)
2 and 3 show examples of the mounting structure of the semiconductor package in which the semiconductor device having the semiconductor element 100 mounted on the semiconductor package 40 is mounted in the socket 50. FIG. The semiconductor device shows an example in which a semiconductor element 100 is mounted on a semiconductor package 40 by flip chip connection. The socket 50 includes a set portion 52 that accommodates a main body portion of the semiconductor package 40 and a base plate 56 on which contacts 54 are formed.
The set portion 52 is provided with a set recess 52 a for accommodating the wiring substrate 10 and the pinned substrate 25 of the semiconductor package 40 and a pin insertion hole 52 b for inserting the pin 22. The pin insertion hole 52 b is provided in the same planar arrangement as the pin 22 attached to the semiconductor package 40, and has a diameter slightly larger than the outer diameter of the pin 22. The contact 54 provided on the base plate 56 is electrically connected to the tip of the pin 22 in a state where the semiconductor package 40 is inserted into the set recess 52a.

  FIG. 2 shows a state in which the semiconductor package 40 has started to be inserted into the socket 50. The set recess 52a formed in the set portion 52 of the socket 50 serves to position the semiconductor package 40 by matching the outer shape. In the semiconductor package 40 of the present embodiment, the pinned substrate 25 has a larger outer dimension than the wiring substrate 10, and the outer surface of the pinned substrate 25 is formed to extend outward from the outer surface of the wiring substrate 10. Therefore, the set recess 52a is formed in accordance with the dimension of the outer surface of the pinned substrate 25. That is, the set recess 52 a of the socket 50 is formed in a planar shape that matches the outer shape of the pinned substrate 25, and when the semiconductor package 40 is mounted on the socket 50, the outer surface of the pinned substrate 25 is the set recess 52 a. It is provided so as to be guided and mounted by the inner side surface 52c.

  When the semiconductor package 40 is attached to the socket 50, as shown in FIG. 2, the semiconductor package 40 is inserted and set so that the outer surface of the pinned substrate 25 is in sliding contact with the inner surface 52c of the set recess 52a. When the insertion of the pinned substrate 25 into the set recess 52a is started, the tip of the pin 22 is prevented from reaching the pin insertion hole 52b, and the outer surface of the pinned substrate 25 is guided by the inner surface 52c of the set recess 52a. When it is positioned and further inserted, the tip of the pin 22 is inserted into the pin insertion hole 52b. As a result, the pin 22 is inserted into the pin insertion hole 52b when the substrate 25 with the pin is reliably positioned in the set recess 52a. The pin insertion hole 52b is formed with a slightly larger diameter than the outer diameter of the pin 22 in consideration of variations in the positional accuracy of the pin 22, so that the pin 22 can be reliably inserted into the pin insertion hole 52b.

FIG. 3 shows a state where the semiconductor package 40 is mounted on the socket 50 in a state where the lower surface of the pinned substrate 25 is in contact with the set recess 52 a of the socket 50. The pin 22 passes through the pin insertion hole 52 b and is inserted to a position where it contacts a contact 54 provided on the base plate 56. Since the substrate 25 with pins is guided by the inner side surface 52c of the set recess 52a, the positional deviation of the semiconductor package 40 is prevented, and the pins 22 of the semiconductor package 40 can be reliably brought into contact with the contacts 54.
Since the wiring board 10 is formed to have an outer dimension smaller than that of the substrate 25 with pins, and the outer surface is located on the inner side of the outer surface of the substrate 25 with pins, the inner surface 52c of the set recess 52a and the wiring substrate 10 are There is no interference.

As described above, in the mounting structure in which the semiconductor package 40 of this embodiment is mounted on the socket 50, the outer shape of the substrate 25 with pins, specifically, the outer surface of the resin substrate 26 constituting the substrate 25 with pins is used as a positioning position. Mounted on the socket 50.
According to the method of mounting the semiconductor package 40 on the socket 50 with the position of the outer surface of the pinned substrate 25 as a positioning position (guide position) with respect to the socket 50, the amount of deviation of the pin position of the semiconductor package 40 is determined by It is defined only by tolerances at the time of manufacturing (accuracy of forming the pinned substrate 25, pin position accuracy), and the conventional positional deviation when the wiring substrate 10 and the pinned substrate 20 are joined, and the wiring substrate 10 And the problem that the manufacturing tolerance of the board | substrate 20 with a pin acts on position shift in a superimposed manner is eliminated.

In the semiconductor package 40 of the present embodiment, the outer surface of the pinned substrate 25 is used for positioning the semiconductor package 40. Therefore, even when the wiring substrate 10 and the pinned substrate 25 are joined, the wiring substrate It is necessary that the outer surface of 10 does not protrude outward from the outer surface of the pinned substrate 25. For this reason, when setting the difference between the external dimensions of the substrate with pin 25 and the wiring substrate 10, the difference becomes larger than the maximum amount of positional deviation that can occur when the wiring substrate 10 and the substrate with pin 25 are joined. It is necessary to set as follows.
When the wiring substrate 10 is formed smaller than the pinned substrate 25 as in the semiconductor package 40 of the present embodiment, the wiring substrate 10 can be downsized regardless of the size of the pinned substrate 25. There is also an advantage of being able to.

(Manufacturing method of substrate with pins)
FIG. 4 shows a method of manufacturing the pinned substrate 25 used in this embodiment. As described above, the pin-equipped substrate 25 is formed by integrally standing the pins 22 on the resin substrate 26 formed by resin molding. In order to form the pinned substrate 25 by resin molding, as shown in FIG. 4A, the pins 22 are set on the lower mold 60 of the mold for molding, and as shown in FIG. The pin 22 may be clamped by the mold 62 and the lower mold 60, and the resin may be molded by filling the cavity 66 with resin (FIG. 4C).

  As shown in FIG. 4A, a set hole 60a for setting the pin 22 is formed in the lower mold 60 in accordance with the planar arrangement of the pin 22 in the substrate 25 with the pin. The set hole 60a is formed to have an inner diameter into which the shaft portion of the pin 22 is slid, and the head portion 22a protrudes upward from a molding surface 60b formed on the flat surface of the lower mold 60 with the pin 22 set. The depth of the set hole 60a is set. The protruding portion of the pin 22 protruding upward from the molding surface 60 b of the lower mold 60 is a portion corresponding to the thickness of the resin substrate 26.

  As shown in FIG. 4B, the upper mold 62 is formed with a recess for forming a cavity 66 filled with resin, and the inner bottom surface 62a of the recess (the surface facing the molding surface 60b of the lower mold 60). Is formed on a flat surface. The inner surface of the concave portion of the upper die 62 is covered with a molding film 64, and the cavity 22 is formed by clamping the pin 22 with the upper die 62 and the lower die 60. At this time, the end surface (the end surface of the head portion 22a of the pin 22 ( Set so that the top surface contacts the film 64.

  The mold film 64 has heat resistance that can withstand the heating temperature of the mold, and is easily peeled off from the mold surface and the resin and is easily deformed according to the inner surface of the resin molding recess. In addition, materials having extensibility, such as PTFE, ETFE, PET, FEP film, fluorine-impregnated glass cloth, polypropylene film, polyvinyl chloride, etc. are used. Further, after the film 64 is supported by air adsorbing to the upper mold 62 so as to follow the inner surface of the recess, the cavity 66 is decompressed and filled with the resin 70 to prevent the voids from being mixed into the resin. Resin molding.

  FIG. 4C shows a state in which the cavity 66 is filled with a resin 70 and molded. The resin 70 is filled into the cavity 66 from the gate 62b provided in the upper mold 62 and is thermally cured. The end surface of the head portion 22a of the pin 22 is covered with a molding film 64, and the resin 70 is prevented from entering the end surface of the head portion 22a during resin molding, and the upper surface and surface of the resin substrate 26 formed by resin molding. First, resin molding is performed with the end surface of the head portion 22a exposed.

Like the pinned substrate 25 of the present embodiment, the resin substrate 26 formed by resin molding can define the outer dimensions (outer accuracy) to be equal to or higher than the wiring substrate 10 with high accuracy. Like the semiconductor package 40 of the embodiment, it can be suitably used for a product that is mounted and mounted on the socket 50 on the basis of the outer position of the pinned substrate 25.
The method of manufacturing the pinned substrate 25 using the resin molding method is to mix a filler such as silica or alumina into a resin material having a predetermined strength, for example, an epoxy resin or an epoxy resin for reinforcement. By using the resin material, an effective action of reinforcing the wiring board 10 can be obtained. It is also possible to adjust the strength of the pinned substrate 25 by selecting the thickness of the resin substrate 26. Further, by forming the end surface of the head portion 22a so as to be flush with the outer surface of the resin substrate 26, the pinned substrate 25 can be thinned.

(Other configuration examples of semiconductor packages)
FIG. 5 shows the configuration of the second embodiment of the semiconductor package according to the present invention. Similarly to the semiconductor package 40 shown in FIG. 1, the semiconductor package 41 of this embodiment is configured by bonding a substrate with a pin to a wiring substrate. In the semiconductor package of the first embodiment, the external dimensions of the pinned substrate 25 are set larger than the external dimensions of the wiring substrate 10, and the pinned substrate 25 is bonded to the wiring substrate 10 and the pinned substrate 25. In the semiconductor package 41 of the present embodiment, the outer dimension of the wiring substrate 10 is set to be larger than the zero outer dimension of the pinned substrate 25. The wiring board 10 and the pinned substrate 25 are joined to each other so that the outer surface of the wiring substrate 10 extends outward from the outer surface of the pinned substrate 25.

Since the configurations of the wiring substrate 10 and the pinned substrate 25 in the semiconductor package 41 of the present embodiment are the same as the configurations of the wiring substrate 10 and the pinned substrate 25 in the first embodiment, description of the configuration of each part is omitted. .
In the semiconductor package 41, since the outer surface of the wiring substrate 10 extends outward from the outer surface of the pinned substrate 25, a semiconductor formed by mounting the semiconductor element 100 on the semiconductor package 41 as shown in FIG. When the device is mounted in the socket 50, only the wiring substrate 10 serves to position the semiconductor package 41 with respect to the socket 50.

6 shows that the semiconductor package 41 is positioned in the socket 50 by inserting the outer surface of the wiring substrate 10 into sliding contact with the inner surface 52c of the set recess 52a of the socket 50. FIG. In this case, the outer side surface of the substrate 25 with pins is separated from the inner side surface 52c of the set recess 52a and is in a position where it does not interfere with the inner side surface 52c.
The semiconductor package 41 is inserted with the wiring substrate 10 positioned and inserted into the set recess 52 a, whereby the pin 22 is positioned and inserted into the pin insertion hole 52 b formed in the set portion 52, and the contact 54 provided on the base plate 56. The pin 22 is inserted into the electrical connection to establish electrical continuity.

In the manufacturing process of the wiring substrate 10, after a process of forming a required wiring pattern for a large-sized workpiece, the product is cut out from the workpiece as an individual product. The cutting position when cutting the workpiece is made with reference to the marking position provided on the workpiece, and the side surface position (outside dimension) of the wiring board 10 formed on the individual piece is set in a highly accurate unit such as 100 μm or less. Is possible.
As in the case of the first embodiment, in this embodiment, the semiconductor package 41 is positioned and mounted on the socket 50 with the outer position of the wiring board 10 as a reference position. It is defined by the accuracy of the substrate 10 and can be mounted by eliminating the positional shift caused by the mutual position with the substrate 25 with pins.

  In the first embodiment in which the semiconductor package 40, 41 is mounted on the socket 50 with the pinned substrate 25 as a reference, the positional accuracy of the pin 22 depends on the manufacturing tolerance of the pinned substrate 25. On the other hand, when positioning with respect to the external position of the wiring board 10, the positional deviation of the pins 22 occurs due to the positional deviation that occurs when the wiring board 10 and the substrate 25 with pins are joined. In this respect, the semiconductor package 40 of the first embodiment can be mounted on the socket 50 with higher accuracy than the semiconductor package 41 of the present embodiment. However, in the semiconductor package 41 of this embodiment, the manufacturing tolerance of the pinned substrate 25 does not become a problem, and the wiring substrate 10 is configured by the wiring substrate 10 and the pinned substrate 25 in that the outer shape can be processed with extremely high accuracy. This is effective as a configuration in which a semiconductor package is positioned and mounted in a socket.

  In the above-described embodiment, the example in which the resin substrate 26 and the pin 22 are integrally formed by resin molding is used as the pin-attached substrate 25 to be bonded to the wiring substrate 10. However, the present invention is not limited to the case where one formed by resin molding is used. For example, the present invention is similarly applied to the pinned substrate 20 formed by penetrating the pins 22 through the substrate 24 shown in FIG. In addition, when using the pin-equipped substrate 25 formed by resin molding, it is possible to form the head 22a of the pin 22 in various forms such as by projecting from the outer surface of the resin substrate 26 and resin molding.

The present invention has been specifically described above based on the embodiments. By using the pinned substrate 25 in which the pins 22 are erected integrally with the resin substrate 26 formed by resin molding, even the wiring substrate 10 whose strength has been reduced by thinning is reinforced, and warping is suppressed. The thin semiconductor packages 40 and 41 can be provided.

DESCRIPTION OF SYMBOLS 10 Wiring board 13 Insulation layer 15a, 15b Solder resist layer 16 Pin connection pad 18 Solder 20, 25 Board with pin 22 Pin 22a Head part 26 Resin board 30, 40, 41 Semiconductor package 50 Socket 52 Set part 52a Set recessed part 52b Pin insertion hole 52c Inner side surface 54 Contact 56 Base plate 60 Lower mold 62 Upper mold 70 Resin 100 Semiconductor element

Claims (3)

A semiconductor package having a substrate with pins to which pins are attached and a wiring substrate on which pads for pin connection are formed;
A set recess in which the semiconductor package is accommodated and a socket provided with a contact electrically connected to the pin below the set recess;
The substrate with pins is formed by integrally standing the pins on a resin substrate formed by resin molding, one end of the pin is exposed from one surface of the resin substrate, and the other of the resin substrates is The other end of the pin extends from the surface,
In the semiconductor package, the outer shape of the wiring board is larger than the outer shape of the substrate with pins, and one end of the pin and the pin connection pad are joined to form the pinned substrate and the wiring substrate. Bonded, the outer surface of the wiring board extends outside the outer surface of the substrate with pins,
The semiconductor package mounting structure, wherein the semiconductor package, in which the outer surface of the wiring board is guided and inserted into the inner surface of the set recess, is mounted in the socket. A head portion is formed at one end of the pin,
The end surface of the head part is exposed flush with one surface of the resin substrate,
2. The semiconductor package mounting structure according to claim 1 , wherein an end surface of the head portion and the pin connection pad are joined to each other, and the substrate with pins and the wiring substrate are joined. The substrate with pins covers the end surface of the one end portion, slides into the other end portion, fills a mold mold cavity in which the pins are set, and fills the resin substrate integrally. 3. The semiconductor package mounting structure according to claim 1, wherein the pins are formed upright.

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