JP5251086B2 - Semiconductor integrated circuit verification apparatus, method, and program - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit verification apparatus, method, and program, and more particularly, to a semiconductor integrated circuit verification technique.

  In recent years, large-scale integrated circuits (hereinafter abbreviated as LSI (Large Scale Integrated Circuit)) are increasing in operation speed and more functions are integrated in one LSI due to improvement of microfabrication technology. Therefore, technical improvement, accuracy improvement, productivity improvement, etc. of the test bench for verifying ASIC (Application Specified Integrated Circuit) are important issues.

As a technique relevant to the present invention, there are techniques described in Patent Documents 1 and 2, for example. The technique disclosed in Patent Document 1 uses test data and result data, and uses the information of the result data in the analysis. In addition, the technique described in Patent Document 2 issues an instruction for causing a verification target ASIC to execute a test operation for the purpose of improving the productivity and reusability of the test bench for verifying the ASIC as described above. The present invention provides an invention including a softwareized test scenario and a softwareized bus model.
JP 2004-361171 A JP 2005-093929 A

  When the LSI circuit configuration is connected serially with multiple functional blocks, it is widely used to connect the monitor model to the internal bus on the test bench and perform simulation while checking the output of each functional block to facilitate analysis. Are known.

  At this time, if the functional blocks connected in series are composed of several tens of stages, if the simulation is performed with the monitor model function added to the output of each functional block, the dozens of monitor models simultaneously perform computation processing. As a result, the simulation speed is significantly reduced and the productivity is deteriorated.

  There is also a method of turning off the function of comparing the expected value of the monitor model of each internal bus, saving the data as LOG data, suppressing the deterioration of the simulation speed, and leaving it as data for analysis. However, if several tens of monitor information is simply stored, the system memory prepared in the ASIC verification environment overflows and immediately fails.

  Also, if the memory capacity allowed in the system environment is divided and allocated to each monitor, an error will occur and analysis will include a large amount of LOG information that is not related to the error. In combination, it takes a lot of analysis time to find the data corresponding to the output of each block going back from the final output, and it takes a lot of time to identify the error part, leading to deterioration of productivity. Yes.

  In view of the above circumstances, an object of the present invention is to hold only data in the vicinity of when an error occurs in each monitor.

A first aspect of the present invention for achieving the above object, a verification device for a semiconductor integrated circuit to verify a semiconductor integrated circuit in which a plurality of block circuit are connected in series to correspond to each circuit block expectations and monitor means, storage means for storing the log information before Symbol monitor means to the memory space, the output data from the block circuit of the last stage connected to the series to obtain independently the log information of the block circuit and value comparison, anda operation confirmation means for communicating the results of the expected value comparing to the respective monitor unit, before Symbol each monitoring means, an error in the operation confirmation means of the expected value comparator conveyed from the results If there is a verification device for a semiconductor integrated circuit, characterized in that it is stored over a previous SL memory space then the log information corresponding to each block circuits acquired newly.

A second aspect is a semiconductor integrated circuit verification method by a semiconductor integrated circuit verification device for verifying a semiconductor integrated circuit in which a plurality of block circuits are connected in series, the semiconductor integrated circuit verification device comprising: a plurality of monitoring means, storage means, and a operation confirmation means, the monitoring means comprises a monitoring step of acquiring the log information of the block circuit that corresponds to each circuit block independently, the storage means a step of storing the log information of the monitor step to a dedicated memory space for each of the monitor step, the operation confirmation means, the output data from the block circuit of the last stage connected to the series compared the expected value the operation check step of transmitting the results of the expected value comparing said monitoring means, each of said monitor means, it is an error in the operation confirmation means of the expected value comparator conveyed from the results Case, the log information corresponding to the next the newly acquisition by said respective block circuit verification method of a semiconductor integrated circuit, characterized in that and a step of storing overwritten to the memory space.

The third aspect is a program for verifying a plurality of blocks circuits connected in series, the semiconductor integrated circuit having a plurality of monitoring means, storage means, and an operation confirmation means, It said monitor means, storing a monitor step of acquiring the log information of the block circuit that corresponds to each circuit block independently, the storage means, the log information of the monitor step to a dedicated memory space for each of the monitor step a step of the operation confirmation means, the operation check step of the output data from the block circuit of the last stage are connected in series relative expected values, convey the results of the expected value comparing said monitor means, said each monitor means, wherein when there are no errors in the expected value comparison result transmitted from the operation confirmation means, then the newly acquisition was said log information corresponding to each circuit block A step of storing by overwriting the memory space is a program for causing execution.

  According to the present invention, each monitor can hold only data in the vicinity of when an error occurs.

  Preferred embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, a block circuit, an I / F (interface), a bus model, and a test scenario are shown, but the number is not limited.

  The test bench 100 according to the present embodiment is realized by cooperation between hardware such as a computer and a workstation and software incorporated in the hardware. For example, the present embodiment can be realized by being provided as a test bench program (software), being expanded on a temporary storage of hardware, and being processed and executed by a hardware control device.

  Referring to FIG. 1, a configuration of a test bench 100 according to the present embodiment is shown together with an ASIC 200 to be tested. In the ASIC 200, blocks A, B, C, and D (hereinafter sometimes collectively referred to as “block 201”) are connected in series, that is, in series.

  The test bench 100 includes internal bus monitors A, B, and C (hereinafter sometimes collectively referred to as “internal bus monitor 101”), a CPU model 103, an input I / F (interface) bus model 104, and an output I. / F bus model 105. The CPU model 103 is a software version of a control device that sets and activates the ASIC 200. The internal bus monitor 101 checks the operation of the corresponding block and compares expected values for all blocks except the last block of the block 201.

  The input I / F bus model 104 and the output I / F bus model 105 are software versions of an input I / F bus that inputs data to the ASIC 200 or an output I / F bus that receives data output from the ASIC 200, respectively. is there. The output I / F bus model 105 also has a function of confirming the operation of the last block of the block 201 (block D201d in FIG. 1) and comparing expected values.

  The test bench 100 also has a test scenario 102 that is softwareized. The test scenario 102 activates the CPU model 103 and causes the CPU model 103 to execute setting of the ASIC 200 and operation activation. The test scenario 102 also performs operation setting and operation activation of the input I / F bus model 104.

  The operation of each component shown in FIG. 1 has been described above. Next, the function of each of these components when the test bench 100 performs a single test operation will be described.

  First, the test scenario 102 activates the CPU model 103 to set the ASIC 200 and activate the operation. The test scenario 102 also performs operation setting and operation activation of the input I / F bus model 104.

  When the operation activation of the input I / F bus model 104 is set, the input I / F bus model 104 starts the operation to the ASIC 200 and inputs data to the block A 201a. The input data is transferred to the block B 201b and simultaneously output to the internal bus monitor A 101a of the test bench 100. Then, the internal bus monitor A 101a monitors the output data of the block A 201a and performs operation check and expected value comparison.

  Similarly, in the block B 201b and the block C 201c, the bus monitor corresponding to each block monitors the output data. However, among the blocks 201, the block D201d located at the last stage has the output I / F bus model 105 that receives the output data also functions as a bus monitor. Therefore, the output I / F bus model 105 monitors the output from the block D201d and compares the output data with an expected value.

  Further, when the result of the expected value comparison is OK, the output I / F bus model 105 informs each internal bus monitor 101 of this (hereinafter referred to as “expected value OK information”). Then, each internal bus monitor 101 knows that the data output corresponding to the expected value OK information is OK (no error) at the same time. Therefore, each internal bus monitor 101 does not have to compare expected values every time it receives output data from the corresponding block 201.

  However, if the expected value comparison result of the output data received by the output I / F bus model 105 is not OK, an error has occurred in which part of the block 201 of the ASIC 200 to be verified, and the result is not OK. I need to know what happened. Therefore, each internal bus monitor 101 has a separate memory space, and temporarily stores output data from the monitored block in the memory space, which is useful for verification. Hereinafter, state transitions according to time, such as output data from blocks stored in the memory space by the internal bus monitors 101 of the present embodiment, will be described, and features of the present embodiment will be described.

  Referring to FIG. 2, the relationship between output data obtained by each internal bus monitor 101 and output I / F bus model 105 and time is shown.

  In FIG. 2, the monitor A data represents the output obtained by the internal bus monitor A 101a from the block A 201a along the time axis. A-2, A-3,..., A-7 and output data are sequentially output with time from A-1. These output data A-1 to A-7 are held as LOG information in the memory space used by the internal bus monitor A101a, but not all of them are held as will be described later with reference to FIG. .

  Similarly to the monitor A data, the monitor B data and the monitor C data are output data that are sequentially output from the internal bus monitor B 101b and the internal bus monitor C 101c. “Output data” shown at the bottom in FIG. 2 is data that is output from the block D 201 d and that has undergone expected value comparison in the output I / F bus model 105.

  In FIG. 2, the time T1 of output 1 represents the time when the expected value comparison of output 1 is OK. At this time, in the internal bus monitor A 101a, the outputs of A-1 and A-2 are finished, and the output of A-3 is being held as LOG in the memory space. Similarly, the internal bus monitor B101b is holding B-3 and the internal bus monitor C101c is holding C-2 as LOG.

  In FIG. 2, T2, T3, and T4 indicate the time when the comparison of the expected values of outputs 2, 3, and 4 is OK, and the portions that overlap with the broken line arrows are output by the internal bus monitors 101, respectively. This is data in the middle of holding the stored data as LOG.

  On the other hand, at time T1, it is found that the data of A-1, B-1, and C-1 corresponding to output 1 are OK (no error). Therefore, the data of A-1, B-1, and C-1 may be lost when the time T1 is passed. Therefore, in this embodiment, in order to minimize the required memory size, a configuration in which the next data is overwritten from the next data into the memory space in which the data that may be lost is stored. take. Hereinafter, this configuration will be described in more detail with reference to FIG.

  FIG. 3 shows a flow in which the next data is overwritten on the data that is in the OK state in the memory space. Since the monitor A data and the monitor B data are the same in this example, the flow of the monitor A data and the monitor C data will be described.

  In FIG. 3, at time T1, the memory space holds A-1, A-2 data and data up to the middle of A-3. Since the time T1 is the time when the output I / F bus model 105 issues the expected value OK information to each internal bus monitor 101 with respect to the output 1, the internal bus monitor A101a is A-1 at time T1. It turns out that the data is OK. Therefore, the space in which A-1 is stored in the memory space used by the internal bus monitor A 101a (hereinafter referred to as “A-1 space”) can be overwritten. Therefore, when the internal bus monitor A101a next holds all the A-3 data, it overwrites the A-4 data in the A-1 space.

  Similarly, the internal bus monitor A 101a finds that the A-2 data is OK at the time T2 in the middle of holding the A-4 data. Therefore, when the internal bus monitor A 101a finishes holding the A-4 data, it then overwrites the A-5 data in the A-2 space. Similarly, at time T3 and T4, when the OK data is found, the internal bus monitor A 101a repeats overwriting the next data on the OK data when the next data is held.

  The same applies to the monitor C data. The internal bus monitor C101c holds the middle part of the C-1 data and the C-2 data in the memory space used by the internal bus monitor C101c at the time T1. The internal bus monitor C101c knows that the C-1 data is OK at time T1. Therefore, the C-1 space can be overwritten. Therefore, the internal bus monitor C101c then overwrites the C-1 space with the C-1 space when it finishes holding all the C-2 data.

  Similarly, the internal bus monitor C101c recognizes that the C-2 data is OK at time T2 during the holding of the C-3 data. Therefore, when the internal bus monitor C101c finishes holding the C-3 data, it overwrites the C-4 data in the C-2 space. Similarly, at times T3 and T4, the internal bus monitor C101c repeats overwriting when OK data is found.

  This makes it possible to know the shortest transfer amount information from the own block to the output with the selected function combination without knowing what function combination is in the blocks after the own block, and when an error occurs in the output Only the minimum data necessary for each block can be held. That is, each internal bus monitor can hold only data in the vicinity of when an error occurs. As a result, it does not take time to sequentially determine related data even during analysis. Therefore, the configuration and operation of this embodiment lead to productivity improvement.

  The present embodiment may be further configured as follows. That is, the test scenario 102 sets the data size for the output I / F bus model 105 to output the expected value OK information. The output I / F bus model 105 sets the expected value OK in units of the set output data amount. Information is sent to each internal bus monitor 101. That is, the test scenario 102 functions as a setting unit that sets the operating environment of the output I / F bus model 105. As a result, data can be held with a data size that is easy to analyze according to the function. As a result, the analysis time can be shortened, and productivity can be improved.

  The present embodiment may be further configured as follows. That is, each internal bus monitor 101 shares information with the minimum transfer size of the internal bus, and holds the data amount and time information as performance information of the block in the memory space used by each. Thereby, it becomes possible to confirm the performance in the combination of each block 201 (block circuit).

  The present embodiment may be further configured as follows. That is, the test bench 100 is further provided with a function coverage for confirming the verified contents, and the function coverage additionally verifies the performance information. Thereby, verification with higher quality can be performed and quality can be improved.

  The present embodiment may be further configured as follows. In other words, when there is an error as a result of the expected value comparison of the output data (that is, when an error occurs), the output I / F bus model 105 indicates that as NG information as in the case of the expected value OK information. The information is transmitted to each internal bus monitor 101 to share information. Each internal bus monitor 101 adds error information to the LOG information and holds it in the memory space used by each. Thereby, analysis can be further facilitated.

  The present embodiment may be further configured as follows. That is, when an error occurs, the output I / F bus model 105 transmits information indicating the number of elements in the data array (hereinafter referred to as “array information”) indicating the output data in which the error has occurred. To share information. Each internal bus monitor 101 adds array information to the LOG information and holds it in the memory space used by each. As a result, the position of the output data in which an error has occurred in the data array that has been tested is known, and this is valuable information for narrowing down the error condition.

  The preferred embodiment of the present invention has been described above, but the present invention is not limited to this, and various modifications can be made without departing from the scope of the invention. In addition, any of the above configurations can be implemented in combination.

It is a block diagram which shows the structure containing the test bench and ASIC of verification object which concern on embodiment of this invention. It is a figure for demonstrating the relationship between the data which each internal bus monitor of the test bench which concerns on embodiment of this invention acquires, and time. It is a figure for demonstrating the state transition of each memory space which each internal bus monitor of the test bench concerning embodiment of this invention uses, respectively.

Explanation of symbols

100 Test bench 101 Internal bus monitor 102 Test scenario 103 CPU model 104 Input I / F bus model 105 Output I / F bus model 200 ASIC
201 blocks (block circuit)

Claims (8)

A verification apparatus for a semiconductor integrated circuit that verifies a semiconductor integrated circuit in which a plurality of block circuits are connected in series ,
A monitor means for acquiring the log information of the block circuit that corresponds to each circuit block independently,
Storage means for storing the log information before Symbol monitor means in the memory space,
An operation check means for comparing the output data from the last stage block circuit connected in series with the expected value and transmitting the result of the expected value comparison to each of the monitor means ;
Before SL each monitoring means, if there are no errors in the operation confirmation means of the expected value comparator conveyed from the results, the then acquired newly log information corresponding to each block circuit before Symbol memory space A verification apparatus for a semiconductor integrated circuit, overwritten and stored. A setting unit for setting an operating environment of the operation checking unit;
The setting means sets a data size for the operation check means to check the operation,
2. The semiconductor integrated circuit verification device according to claim 1, wherein the operation check means checks the operation each time output data having a data size set from the last block circuit is obtained.   2. The monitor unit according to claim 1, wherein the monitor unit shares information with a minimum transfer size of an internal bus, and holds data amount and time information as performance information of a corresponding block circuit in the memory space used by each. 3. The semiconductor integrated circuit verification apparatus according to 2. It further has a function coverage to confirm the verified contents,
4. The semiconductor integrated circuit verification device according to claim 3, wherein the functional coverage additionally verifies the performance information. The operation confirmation means, if there is an error in the results of the expected value comparison, tell that to the monitoring means,
5. The semiconductor integrated circuit according to claim 1, wherein the monitoring unit adds error information to log information corresponding to output data having an error and stores the log information in the memory space. 6. Circuit verification device. The operation confirmation means, if there is an error in the results of the expected value comparison, convey the sequence information output data out error indicates what number of elements in the data array to said monitoring means,
6. The apparatus for verifying a semiconductor integrated circuit according to claim 5, wherein the monitoring unit adds the array information to log information corresponding to output data having an error and stores the log information in the memory space. A method for verifying a semiconductor integrated circuit by a semiconductor integrated circuit verification apparatus for verifying a semiconductor integrated circuit in which a plurality of block circuits are connected in series ,
The semiconductor integrated circuit verification device includes a plurality of monitoring means, storage means, and operation checking means,
A monitor step said monitor means, for acquiring the log information of the block circuit that corresponds to each circuit block independently,
The storage means stores log information of the monitoring process in a dedicated memory space for each monitoring process;
The operation check means compares the output data from the last stage block circuit connected in series with an expected value , and transmits the result of the expected value comparison to the monitor means .
Wherein each monitor means, when there is no error in the operation confirmation means of the expected value comparator conveyed from the results, the log information corresponding to the next the newly acquisition by said each circuit block to overwrite the memory space And storing the process,
A method for verifying a semiconductor integrated circuit, comprising: A program for verifying a plurality of blocks circuits connected in series,
In a semiconductor integrated circuit having a plurality of monitor means, storage means, and operation check means ,
A monitor step said monitor means, for acquiring the log information of the block circuit that corresponds to each circuit block independently,
The storage means stores log information of the monitoring process in a dedicated memory space for each monitoring process;
The operation check means compares the output data from the last stage block circuit connected in series with an expected value , and transmits the result of the expected value comparison to the monitor means .
Wherein each monitor means, when there is no error in the operation confirmation means of the expected value comparator conveyed from the results, the log information corresponding to the next the newly acquisition by said each circuit block to overwrite the memory space And storing the process,
Program of the order to the execution.

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