JP5256159B2 - Semiconductor package - Google Patents

Description

  The present invention relates to a resin-encapsulated semiconductor package.

As a conventional semiconductor package, for example, as shown in FIG. 4, a semiconductor chip 101 is fixed to the upper surface of a metal die pad 102 formed in a plate shape by soldering, and the semiconductor chip 101 and the die pad 102 are sealed with a sealing resin 103. (For example, refer to Patent Document 1).
In addition, there is a semiconductor package of this type in which the lower surface of the die pad 102 is exposed outward from the sealing resin 103 in order to efficiently dissipate heat generated in the semiconductor chip 101 outward.

JP 11-31775 A

However, when the semiconductor package is heated and cooled by performing a thermal cycle test, a thermal fatigue test, or a moisture absorption reflow on the conventional semiconductor package, the difference between the two is based on the material difference between the die pad 102 and the sealing resin 103. There is a possibility that the semiconductor chip 101 and the die pad 102 may be separated due to the difference in thermal expansion coefficient.
More specifically, when the semiconductor package is heated and cooled, the difference in the amount of expansion and contraction in the direction along the upper surface of the die pad 102 (surface direction) is particularly significant between the die pad 102 and the sealing resin 103. Therefore, a large shear stress is generated in the solder that joins the semiconductor chip 101 and the die pad 102. As a result, the semiconductor chip 101 and the die pad 102 are peeled off due to, for example, cracks in the solder. This peeling phenomenon is particularly likely to occur in a semiconductor package having a configuration in which the lower surface of the die pad 102 is exposed to the outside.
Conventionally, for example, it has been considered to suppress the peeling phenomenon by forming a groove on the upper surface of the die pad 102 and engaging the sealing resin 103 with the groove. However, in such a configuration, there is a problem that solder fatigue due to repeated heating and cooling of the semiconductor package cannot be sufficiently suppressed, and the peeling phenomenon cannot be sufficiently suppressed. In particular, since the depth dimension of the groove becomes smaller as the thickness dimension of the die pad 102 becomes thinner, sufficient engagement between the groove and the sealing resin 103 cannot be ensured, so that the adhesion between the die pad 102 and the sealing resin 103 is reduced. Is not sufficiently obtained, and the aforementioned peeling phenomenon is likely to occur.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a semiconductor package capable of enhancing the effect of suppressing peeling between a semiconductor chip and a die pad.

In order to solve this problem, a semiconductor package of the present invention includes a die pad portion formed of a plate material, and a semiconductor chip joined to the upper surface of a plate-shaped arrangement plate portion of the die pad portion via solder. And a sealing resin for sealing the die pad part and the semiconductor chip, the die pad part being bent from the arrangement plate part and extending above the upper surface, and the rising part from the upper end of the rising part And a bent portion that is bent in a direction opposite to the portion and extends in a direction away from the arrangement plate portion along the upper surface, and the rising portion faces the upper surface. the bent at an angle of more than 90 degrees to an imaginary extended line from the periphery of the upper surface extending outward of the placement plate portion, the multiple bent portions are sealed by a sealing resin, the upper The height position of the upper end of the rising portion with respect to the semiconductor chip is higher than the upper surface of the semiconductor chip, a pair of the multiple bent portions are formed at the positions sandwiching the semiconductor chip, and the rising portion and the folded portion are arranged in the arrangement It is arranged in one direction with respect to the plate part, and the dimension in the width direction of the rising part and the folded part is equal to the dimension in the width direction of the arrangement plate part.

  In the semiconductor package of the present invention, the rising portion of the multiple bent portion is defined by bending the flat die pad portion at an angle of 90 degrees or more. The space region between the portions is formed in a tapered shape that becomes narrower from the semiconductor chip toward the rising portion along the surface direction of the arrangement plate portion. Furthermore, since the folded portion is also defined by folding the flat die pad portion at an angle of 90 degrees or more, the space region between the rising portion and the folded portion is the space region between the arrangement plate portion and the rising portion. Is formed in a tapered shape in the opposite direction.

  The sealing resin engages with the multiple bent portions by entering the narrow space region between the arrangement plate portion and the rising portion and the narrow space region between the rising portion and the folded portion, respectively. Even if heated and cooled, the difference in the amount of expansion and contraction between the sealing resin and the arrangement plate portion can be greatly reduced. In other words, the expansion and contraction of the sealing resin with respect to the arrangement plate portion can be sufficiently suppressed. In particular, the above-described two spatial regions have shapes that taper in opposite directions in the direction (arrangement direction) in which the semiconductor chips and the multiple bent portions are arranged along the surface of the arrangement plate portion. The difference in the amount of expansion and contraction in the arrangement direction between the resin and the arrangement plate portion can be reduced.

From the above, even when the semiconductor package is heated and cooled, no large shear stress is generated in the solder that joins the semiconductor chip and the placement plate, and solder fatigue due to repeated heating and cooling of the semiconductor package It can be suppressed sufficiently. Therefore, the effect of suppressing peeling between the semiconductor chip and the arrangement plate portion can be enhanced.
In addition, since the multiple bent portion that engages with the sealing resin is formed by bending the die pad portion in a flat plate state, the die pad portion is compared with the case where a groove is formed on the upper surface of the die pad as in the prior art. Even if the thickness dimension is set to be thin, it is possible to easily prevent the semiconductor chip from peeling off.

Further, the sealing resin in which expansion and contraction with respect to the arrangement plate portion is suppressed by the engagement with the multiple bent portions because the height position of the upper end of the rising portion relative to the upper surface of the arrangement plate portion is higher than the upper surface of the semiconductor chip Since this area is expanded to the area above the semiconductor chip, the magnitude of the shear stress applied to the solder joining the semiconductor chip and the placement plate portion can be further reduced.

In addition, by forming a pair of multiple bent portions at a position where the semiconductor chip is sandwiched, a portion of the sealing resin that seals the semiconductor chip between the upper surface of the arrangement plate portion and the upper end of the rising portion (hereinafter referred to as “a”). Is called a chip sealing portion.) Is sandwiched between a pair of multiple bent portions, so that even when the semiconductor package is heated and cooled, the expansion and contraction of the chip sealing portion with respect to the arrangement plate portion in the arrangement direction is further increased. It can be suppressed. As a result, the difference in the amount of expansion and contraction between the sealing resin and the arrangement plate portion can be further reduced. Therefore, the magnitude of the shear stress applied to the solder for joining the semiconductor chip and the arrangement plate portion can be further reduced.

  Furthermore, in addition to the above configuration, when the height of the rising portion is set higher than the upper surface of the semiconductor chip, the region of the chip sealing portion sandwiched between the pair of multiple bent portions expands to the upper side of the semiconductor chip. Therefore, the difference in the amount of expansion and contraction between the chip sealing portion and the arrangement plate portion in the arrangement direction can be significantly reduced. Therefore, the shear stress generated in the solder that joins the semiconductor chip and the arrangement plate portion is remarkably reduced, and the semiconductor chip can be prevented from peeling from the arrangement plate portion.

  And in the said semiconductor package, the height position of the upper end of the said rising part with respect to the said upper surface may mutually differ between a pair of said multiple bending parts.

In the semiconductor package, the bending angle of the rising portion with respect to the upper surface may be different between the pair of the multiple bent portions.
In this case, the degree of taper in the space region between the arrangement plate portion and the rising portion is different between the pair of multiple bent portions.

  According to the present invention, the effect of suppressing the separation between the semiconductor chip and the die pad portion based on the heating and cooling of the semiconductor package can be enhanced by engaging the sealing resin with the multiple bent portions. In particular, the multiple bent portion that contributes to prevention of peeling between the semiconductor chip and the die pad portion is formed by bending the die pad portion, so that it is easy to prevent peeling of the semiconductor chip even if the thickness of the die pad portion is set thin. Can be aimed at.

1 is a schematic plan view showing a semiconductor package according to an embodiment of the present invention. It is AA arrow sectional drawing of FIG. It is an expanded sectional view which shows the die pad part main body which comprises the semiconductor package of FIG. It is a schematic sectional drawing which shows an example of the conventional semiconductor package.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
As shown in FIGS. 1 and 2, the semiconductor package 1 according to this embodiment is generally configured by sealing a semiconductor chip 2, a die pad portion 3, leads 4 and connectors 5 with a sealing resin 6.
The semiconductor chip 2 is a semiconductor element such as a diode or a transistor, for example, and is formed in a plate shape having a rectangular shape in plan view, and has electrodes on its upper surface 2a and lower surface 2b.
The die pad portion 3 and the lead 4 are constituted by a lead frame formed by pressing a conductive plate material such as copper.

The die pad portion 3 includes a die pad portion main body 7 having a rectangular plate shape in plan view and a suspension lead 8 integrally connected to the die pad portion main body 7. Furthermore, the die pad main body 7 includes a flat plate-shaped arrangement plate portion 11, a rising portion 12 that is bent from the arrangement plate portion 11 and extends above the upper surface 11a, and is opposite to the rising portion 12 from its upper end. And a folded portion 13 that is bent.
The semiconductor chip 2 is joined to the central portion of the upper surface 11a of the arrangement plate portion 11 via the solder 14, whereby the semiconductor chip 2 and the die pad portion 3 are electrically connected.

  For example, as shown in FIG. 3, the rising portion 12 is 90 degrees or more with respect to a virtual extension line L <b> 1 extending outward from the peripheral edge of the upper surface 11 a of the arrangement plate portion 11 so as to face the upper surface 11 a of the arrangement plate portion 11. Is bent at an angle of That is, the rising portion 12 is defined by bending the flat die pad portion 3 at an angle of 90 degrees or more. Thus, the angle θ (first bending angle θ) of the rising portion 12 with respect to the upper surface 11a of the arrangement plate portion 11 is set to be less than 90 degrees. In other words, the space region 21 (first space region 21) between the upper surface 11a of the placement plate portion 11 and the rising portion 12 facing the semiconductor substrate is a semiconductor along the surface direction (X-axis direction) of the placement plate portion 11. It is formed in a tapered shape that becomes narrower from the chip 2 toward the rising portion 12.

On the other hand, like the rising portion 12, the folded portion 13 is also defined by bending a flat die pad portion at an angle of 90 degrees or more. The folded portion 13 extends in the surface direction (X-axis direction) of the arrangement plate portion 11 so as to be separated from the arrangement plate portion 11 with respect to the upper end of the rising portion 12. That is, the arrangement plate part 11 and the folded part 13 are parallel to each other. Therefore, the angle φ (second bending angle φ) of the folded portion 13 with respect to the rising portion 12 is set to be less than 90 degrees so as to be equal to the first bending angle θ. Further, the space region 22 (second space region 22) between the rising portion 12 and the folded-back portion 13 facing the rising portion 12 is formed in a tapered shape opposite to the first space region 21. The two bending angles θ and φ described above may be set to be at least greater than 0 degree and less than 90 degrees, but are more preferably set to, for example, 30 degrees or more and 80 degrees or less.
The rising portion 12 and the folded portion 13 constitute a multiple bent portion 15, and a pair of the multiple bent portions 15 are formed at positions where the semiconductor chip 2 is sandwiched. Specifically, a pair is provided at both ends in the direction along one opposite side (X-axis direction) of the placement plate portion 11 formed in a rectangular shape in plan view so as to sandwich the semiconductor chip 2 on the placement plate portion 11. Yes.

In each of the pair of multiple bent portions 15, the height position of the upper end of the rising portion 12 with respect to the upper surface 11 a of the arrangement plate portion 11 is set higher than the upper surface 2 a of the semiconductor chip 2.
However, the height position of the upper end of the rising portion 12 with respect to the upper surface 11a of the arrangement plate portion 11 is different between the pair of multiple bent portions 15A and 15B. Further, the first bending angle θ of the rising portion 12 with respect to the upper surface 11a of the arrangement plate portion 11 is also different between the pair of multiple bent portions 15A and 15B. In other words, the taper degree of the first space region 21 is different between the pair of multiple bent portions 15A and 15B.

In the present embodiment, the upper end of one rising portion 12A provided on one end side in the X-axis direction of the arrangement plate portion 11 is the other rising portion 12B provided on the other end side of the arrangement plate portion 11. It is located higher than the upper end. Further, the first bending angle θA of one rising portion 12A is set larger than the first bending angle θB of the other rising portion 12B. That is, one second bending angle φA is set larger than the other second bending angle φB.
Further, the length dimension of the folded portion 13 along the X-axis direction is also different between the pair of multiple bent portions 15A and 15B. In the present embodiment, the length dimension of one folded portion 13A provided on one end side of the placement plate portion 11 is equal to the length of the other folded portion 13B provided on the other end side of the placement plate portion 11. It is set shorter than the dimension.

As shown in FIG. 1, the suspension lead 8 has an elongated shape as compared with the die pad unit body 7, and the Y axis is the end of one folded portion 13 </ b> A provided on one end side of the arrangement plate unit 11. It is integrally connected to the middle part of the direction. The suspension lead 8 extends in the X-axis direction so as to further extend from the end portion of the one folded portion 13A.
As shown in FIGS. 1 and 2, a plurality of leads 4 (two in the illustrated example) are arranged at intervals with respect to the end portion of one folded portion 13 </ b> A, and are parallel to the suspension leads 8 and die pads. It extends in the X-axis direction so as to be separated from the main part 7. Each lead 4 is arranged at the same height as the suspension lead 8 and one folded portion 13A.

Each connector 5 is joined to both the semiconductor chip 2 and the lead 4, whereby the semiconductor chip 2 and the lead 4 are electrically connected to each other. The connector 5 may be formed of a bonding wire as in the illustrated example, but may be formed of a plate-like member such as a copper material. And when the connector 5 consists of plate-shaped members, the both ends should just be joined to the semiconductor chip 2 and the lead | read | reed 4 via conductive adhesives, such as solder.
The sealing resin 6 is formed so as to embed the semiconductor chip 2, the die pad main body 7 and the connector 5, and only the leading end side in the extending direction of the lead 4 and the suspension lead 8 protrudes outside the sealing resin 6. ing. More specifically, the sealing resin 6 includes a narrow first space region 21 between the arrangement plate portion 11 and the rising portion 12 and a narrow second space region 22 between the rising portion 12 and the folded portion 13. , Respectively, thereby engaging the multiple bent portion 15.

According to the semiconductor package 1 having the above-described configuration, by entering the narrow first space region 21 between the arrangement plate portion 11 and the rising portion 12 and the narrow second space region 22 between the rising portion 12 and the folded portion 13, respectively. Since the multiple bent portion 15 is engaged, even if the semiconductor package 1 is heated and cooled, the difference in the amount of expansion and contraction between the sealing resin 6 and the arrangement plate portion 11 can be greatly reduced. it can. In other words, the expansion and contraction of the sealing resin 6 with respect to the arrangement plate portion 11 can be sufficiently suppressed.
In particular, in the semiconductor package 1 of the present embodiment, a pair of multiple bent portions 15 are formed at positions where the semiconductor chip 2 is sandwiched, and the height positions of the rising portions 12 are set higher than the upper surface 2 a of the semiconductor chip 2. Therefore, the portion of the sealing resin 6 that is located on the placement plate portion 11 and embeds the semiconductor chip 2 (for example, the chip sealing portion 23 including the first space region 21 in FIG. 2) is the placement plate portion 11. In contrast, the expansion and contraction in the arrangement direction (X-axis direction) of the pair of multiple bent portions 15 can be particularly suppressed. That is, the difference in the amount of expansion and contraction in the arrangement direction between the sealing resin 6 and the arrangement plate portion 11 can be significantly reduced.

From the above, even if the semiconductor package 1 is heated and cooled, the shear stress generated in the solder 14 that joins the semiconductor chip 2 and the arrangement plate portion 11 is remarkably reduced, and the heating and cooling of the semiconductor package 1 are repeated. The fatigue of the solder 14 can also be sufficiently suppressed. Therefore, peeling between the semiconductor chip 2 and the die pad portion 3 can be prevented.
In addition, since the multiple bent portion 15 that contributes to prevention of peeling between the semiconductor chip 2 and the die pad portion 3 is configured by bending of the die pad portion 3, even if the thickness dimension of the die pad portion 3 is set thin, the semiconductor chip 2 can be easily prevented from being peeled off.

In the semiconductor package 1 of the present embodiment, the rising portion 12 and the folded portion 13 are defined by bending the flat die pad portion 3 at an angle of 90 degrees or more. For example, even when the sealing resin 6 is about to expand more in the X-axis direction than the arrangement plate portion 11, the bending angles θ and φ of the arrangement plate portion 11 and the folded portion 13 with respect to the rising portion 12 can be reliably held. .
Note that in a semiconductor package in which the placement plate portion 11 and the folded portion 13 are bent at an angle of less than 90 degrees with respect to the rising portion 12, the sealing resin 6 is moved more in the X-axis direction than the placement plate portion 11 by heating and cooling of the semiconductor package. When the expansion resin is greatly expanded, the rising portion 12 is pushed to the outside of the arrangement plate portion 11 by the expanding sealing resin 6, so that the bending angles θ and φ of the arrangement plate portion 11 and the folded portion 13 with respect to the rising portion 12. Will become bigger. For this reason, the relative expansion and contraction between the sealing resin 6 and the arrangement plate portion 11 described above cannot be suppressed.

  In addition, in the said embodiment, although one multiple bending part 15A provided in the one end side of the arrangement | positioning board part 11 was formed only in the die pad part main body 7, it should just be formed in the die pad part 3 at least. . Accordingly, one of the multiple bent portions 15A may be formed only on the suspension lead 8, for example, or may be formed on both the die pad main body 7 and the suspension lead 8, for example. In other words, one rising portion 12A and the folded portion 13A may both be formed on the suspension lead 8, or one rising portion 12A may be formed on both the die pad main body 7 and the suspension lead 8 and folded. The part 13 </ b> A may be formed on the suspension lead 8.

Further, the height position of the upper end of the rising portion 12 with respect to the upper surface 11a of the arrangement plate portion 11, the first bending angle θ of the rising portion 12 with respect to the upper surface 11a of the arrangement plate portion 11, and the length dimension of the folded portion 13 are as follows. The pair of multiple bent portions 15 are different from each other, but may be set equally, for example.
Further, although the pair of multiple bent portions 15 are provided at both ends in the X-axis direction of the placement plate portion 11, both ends in any one direction along the surface of the placement plate portion 11 so as to sandwich at least the semiconductor chip 2 therebetween. It suffices if a pair is provided. That is, the pair of multiple bent portions 15 may be provided, for example, in a direction along the other opposite side of the arrangement plate portion 11 (Y-axis direction). In addition, a pair of multiple bent portions 15 may be provided, for example, at both ends in the X-axis direction and both ends in the Y-axis direction.

Further, in the die pad portion 3, the height position of the upper end of the rising portion 12 with respect to the upper surface 11a of the arrangement plate portion 11 may be equal to, for example, the upper surface 2a of the semiconductor chip 2, or may be lower than, for example, the upper surface 2a. Further, for example, only one multiple bending portion 15 may be provided.
Even in such a configuration, since the sealing resin 6 is engaged with the multiple bent portion 15, the difference in the amount of expansion and contraction between the arrangement plate portion 11 and the sealing resin 6 can be reduced. It can be greatly reduced. In particular, the two space regions 21 and 22 in the multiple bent portion 15 are arranged in the direction in which the semiconductor chip 2 and the multiple bent portion 15 are arranged along the surface of the arrangement plate portion 11 (arrangement direction, X-axis direction in the illustrated example). ), The difference in the amount of expansion and contraction between the sealing resin 6 and the arrangement plate portion 11 in the arrangement direction can be remarkably reduced.

  However, for example, even if the upper end of the rising portion 12 is positioned lower than the upper surface 2 a of the semiconductor chip 2, if the pair of multiple bent portions 15 are provided so as to sandwich the semiconductor chip 2, The portion (chip sealing portion) that seals the lower surface 2 b side of the semiconductor chip 2 in the sealing resin 6 positioned at is located between the pair of multiple bent portions 15. Therefore, when a pair of the multiple bent portions 15 are provided, at least the chip sealing portion is located with respect to the arrangement plate portion 11 even when the semiconductor package 1 is heated and cooled, as compared with the case where only one is provided. Since the pair of multiple bent portions 15 does not expand and contract in the arrangement direction (X-axis direction in the illustrated example), the difference in the amount of expansion and contraction between the sealing resin 6 and the arrangement plate portion 11 in the arrangement direction is determined. It can be further reduced. As a result, the magnitude of the shear stress applied to the solder 14 that joins the semiconductor chip 2 and the placement plate portion 11 can be further reduced.

  Further, for example, even if only one multiple bent portion 15 is provided, if the upper end of the rising portion 12 is positioned higher than the upper surface 2 a of the semiconductor chip 2, the arrangement plate is engaged with the multiple bent portion 15. The region of the sealing resin 6 in which the expansion and contraction with respect to the portion 11 is suppressed is expanded to the region above the semiconductor chip 2. Therefore, when the height position of the upper end of the rising portion 12 is set higher than the upper surface 2a of the semiconductor chip 2, the semiconductor is compared with the case where it is set equal to the lower surface 2a or lower than the upper surface 2a. The magnitude of the shear stress applied to the solder 14 that joins the chip 2 and the placement plate portion 11 can be further reduced.

  Furthermore, in the said embodiment, although the sealing resin 6 embed | buried the whole die pad part main body 7, while sealing the at least upper surface 11a of the arrangement | positioning board part 11 among the die pad part main bodies 7, and 1st space area | region 21 and The multiple bent portion 15 may be sealed so that the second space region 22 is filled and the rising portion 12 and the folded portion 13 are embedded. Therefore, for example, the lower surface 11 b of the arrangement plate portion 11 may be exposed to the outside of the sealing resin 6.

  Further, the semiconductor package of the present invention is not limited to the semiconductor chip 2 having electrodes on the upper surface 2a and the lower surface 2b as in the above embodiment, but is also applied to a semiconductor chip such as an IC or LSI having a plurality of electrode pads on the upper surface, for example. Is possible.

  As mentioned above, although embodiment of this invention was explained in full detail with reference to drawings, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included.

DESCRIPTION OF SYMBOLS 1 Semiconductor package 2 Semiconductor chip 3 Die pad part 4 Lead 5 Connector 6 Sealing resin 11 Arrangement board part 12,12A, 12B Standing part 13,13A, 13B Folding part 14 Solder 15,15A, 15B Multiple bending part 21 1st Space region 22 Second space region L1 Virtual extension lines θ, θA, θB First bending angle (bending angle)
φ, φA, φB Second bending angle

Claims (3)

A die pad portion formed of a plate material, a semiconductor chip bonded to the upper surface of a flat plate-shaped arrangement plate portion of the die pad portion, and a sealing resin for sealing the die pad portion and the semiconductor chip And
The die pad portion bends from the placement plate portion and extends above the upper surface, and bends from the upper end of the rise portion in the opposite direction to the rise portion and is separated from the placement plate portion along the upper surface. A multi-folded part composed of a folded part extending in the direction of
The rising portion is bent at an angle of 90 degrees or more with respect to a virtual extension line extending outward from the periphery of the upper surface of the arrangement plate portion so as to face the upper surface,
The multiple bent portion is sealed with a sealing resin;
The height position of the upper end of the rising portion with respect to the upper surface is higher than the upper surface of the semiconductor chip,
A pair of the multiple bent portions are formed at positions sandwiching the semiconductor chip,
The rising portion and the folded portion are arranged in one direction with respect to the arrangement plate portion,
The semiconductor package according to claim 1 , wherein a dimension in the width direction of the rising part and the folded part is equal to a dimension in the width direction of the arrangement plate part. The semiconductor package according to claim 1 , wherein a height position of an upper end of the rising portion with respect to the upper surface is different between the pair of the multiple bent portions. 3. The semiconductor package according to claim 1 , wherein a bending angle of the rising portion with respect to the upper surface is different between the pair of the multiple bent portions.

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