JP5260935B2 - Source line drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of insufficiency of writing time of a video signal to a source line due to shortening of the pulse width of a sampling pulse with a high-frequency clock signal. <P>SOLUTION: A sampling pulse (sam) is raised synchronously with fall of a start pulse (SP). When the start pulse (SP) is raised, the sampling pulse (sam) falls successively while being lagged from a clock signal (CK, CKB) by a half period per stage, synchronously with the rise of the clock signal (CK, CKB). As a result, a sampling pulse (sam) having a pulse width longer than one cycle of the clock signal (CK, CKB) is produced. A desired video signal (VIDEO) is written in a corresponding source line in a period Ta. Thereby, clock signal half cycle time is ensured for writing in a source line. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

The present invention relates to an active matrix display device and a driving method thereof. In particular, the present invention relates to a method for generating a sampling pulse and a source line driver circuit for generating a sampling pulse.

One of the driving methods of the active matrix display device is a dot sequential method. In the dot sequential driving method, source lines are sequentially selected during a period in which one row of scanning lines is selected, and a video signal is written to a pixel. More specifically, a switch connected to each source line is sequentially turned on by a sampling pulse generated from a source line driver circuit including a shift register, a buffer, and the like. The sampling pulse takes a potential of two levels, high (high) and low (low).

The switch for conducting the video line and the source line is turned on when the sampling pulse is High and turned off when the sampling pulse is Low. When the sampling pulse rises and becomes a high level, the switch is turned on and the video signal is written to the source line. When the sampling pulse falls and becomes low level, the switch is turned off and the potential of the source line is determined. In this way, the switches corresponding to the plurality of source lines arranged in the pixel are sequentially turned on and off, so that the potential of each source line is determined.

The characteristics (representative characteristics) of the transistors that constitute the buffer of the source line driver circuit are the period during which the sampling pulse changes from low to high (write start period, rise period) and the period from high to low (write end period, fall period). Depending on the on-current characteristics, etc., if the transistor is a thin film transistor made of polycrystalline silicon, the time is about 10 to 50 nsec. If the potential of the source line changes due to the influence of noise or the like during the period in which the potential of the source line is determined, display defects such as crosstalk (ghost) may occur. In particular, in the case of a display device having a structure in which one video signal is divided and the video signal is input to the source line via a plurality of video signal lines, the video signal is written to the plurality of source lines at the same time. Display defects are visible, and the display defects become more prominent.

One possible cause of noise in the source line is that it overlaps with the rising period of the sampling pulse for selecting the next source line, as shown in FIG. FIG. 20 is a timing chart of input signals and output signals of a conventional source line driving circuit. CK is a clock signal, SP is a start pulse, and VIDEO is a video signal input to the video signal line. The numbers 1, 2, and 3 of the video signal (VIDEO) indicate that they are signals to be written to the source lines X_1, X_2, and X_3. sam_1, sam_2, and sam_3 are sampling pulses for sampling three adjacent source lines, and T indicates a period during which a video signal is written to the source lines. As indicated by the wavy line 80 in FIG. 20, the falling period of the sampling pulse sam_2 overlaps the rising period of the sampling pulse sam_3, so that noise is generated in the source line.

For this reason, noise is reduced by preventing sampling pulses from overlapping with each other in adjacent sampling pulses (see Patent Document 1 and Patent Document 2). Further, as shown in FIG. 21, a method is used in which the pulse width of the sampling pulse is made shorter than a half cycle of the clock signal using PWC (Pulse width Controller) or the like. In this method, the writing period T is shorter than the writing period T in FIG.
JP 2001-265289 A JP 2003-337320 A

Sampling pulse and video signal timings are as follows: variation in sampling pulse delay time due to the characteristics of the transistors that make up the source line driver circuit (typically on-current characteristics), and the desired source line after the video signal is written It is necessary to consider the time to reach the potential. Methods for improving display quality include increasing the resolution by increasing the number of pixels, and increasing the frame frequency, such as double-speed frame driving. Becomes higher. As shown in FIG. 21, in order to prevent the falling period of the sampling pulse from overlapping the rising period of the next sampling pulse, it is necessary to reduce the pulse width of the sampling pulse. There arises a problem that the writing time is insufficient.

The field sequential driving method is one of the means for increasing the resolution. However, when an image is expressed by the field sequential method, if the pulse width of the sampling pulse is reduced as shown in FIG. Write time may be insufficient. In the field sequential method, a color image is displayed by switching and displaying R, G, and B images with one pixel in time, so that the video signal writing time is a normal color display method ( This is because the unit pixel is composed of three pixels of R, G, and B, and is shorter than a method of spatially mixing light from the three pixels.

If the pulse width of the sampling pulse is reduced, not only the writing time of the source line is insufficient, but even the generation of the sampling pulse becomes difficult. In particular, when a thin film transistor made of a non-single crystal semiconductor is used as a transistor of the source line driver circuit, this problem becomes obvious.

In view of the problems associated with the improvement in display quality described above, it is an object of the present invention to provide a source line driver circuit that secures the writing time of a source line and is suitable for increasing the resolution of a display device. Another object of the present invention is to provide a method for driving a display device for reducing display defects caused by overlapping of adjacent sampling pulses.

First, the writing start period and the writing end period of the sampling pulse will be described with reference to FIG. In the present invention, the sampling pulse is a pulse whose pulse width (writing period T) is determined in a period in which the potential is at a high level as in the pulse (A), and a period in which the potential is in a low level as in the pulse (B). It includes both pulses whose pulse width (writing period T) is determined. In the case of the pulse (A), the writing start period Ts is a period in which the potential changes from low to high, that is, a rising period, and the writing end period Tf is a period in which the potential changes from high to low, that is, a falling period. That is. In the case of the pulse (B), the writing start period Ts is a period in which the potential changes from High to Low, that is, a falling period, and the writing end period Tf is a period in which the potential changes from Low to High, that is, a rising period. It is.

The present invention relates to a source line driving circuit for an active matrix display device having a plurality of scanning lines, a plurality of source lines intersecting with the scanning lines, and a pixel portion including a plurality of pixels connected to the scanning lines and the source lines. A circuit for generating a plurality of sampling pulses, at least one video signal line to which a video signal is input, and a plurality of switches connected to the source line and conducting the source line with the video signal line according to the sampling pulse And have.

In order to solve the shortage of the writing period to the source line, the source line driving circuit according to the present invention overlaps adjacent sampling pulses so that the writing end period is after the writing start period of the sampling pulse of the next stage. Generate.

Specifically, in the source line driver circuit of the present invention, the writing period of the sampling pulse is started before the video signal is switched to the video signal to be written by the sampling pulse, and the video signal is A sampling pulse is generated so as to end before switching to a video signal to be written.

In another source line driver circuit of the present invention, the sampling pulse writing period starts before the video signal to be written by the first stage sampling pulse is input to the video signal line. The sampling pulse is generated so as to end before switching to the video signal to be written by the sampling pulse.

In another source line driver circuit of the present invention, a sampling pulse writing period starts in a period in which a video signal is a video signal to be written by a preceding sampling pulse, and the video signal is to be written by a next sampling pulse. A sampling pulse is generated so as to end before switching to the video signal.

In addition, the present invention provides a plurality of scanning lines, a plurality of source lines intersecting the scanning lines, a pixel portion having a plurality of pixels connected to the scanning lines and the source lines, and at least one input of a video signal. The present invention relates to a method for driving an active matrix display device having a plurality of video signal lines.

A driving method of an active matrix display device according to the present invention generates a plurality of sampling pulses according to a start pulse signal and a clock signal, writes a video signal input to the video signal line to a source line according to the sampling pulse, Holding the potential of the source line to which the video signal is written, inputting the video signal to the pixel connected to the selected scanning line through the source line, and determining the video signal to be displayed on the pixel. It is a driving method.

In order to eliminate the above-described display defect due to noise generated in the source line, the driving method of the present invention generates a plurality of sampling pulses so that the writing end period is after the writing start period of the sampling pulse of the next stage. . In addition, during a period in which a video signal is input to the pixel, the pixel portion is in a non-display state, and after the video signals of all the pixels are determined, the pixel portion is changed from the non-display state to the display state. The sampling pulse writing period is started before the video signal input to the video signal line is switched to the video signal to be written by the sampling pulse, and the video signal input to the video signal line is It ends before switching to the video signal to be written by the sampling pulse.

In another driving method of the present invention, the sampling pulse writing period starts before the video signal to be written by the first sampling pulse is input to the video signal line and is input to the video signal line. A plurality of sampling pulses are generated so that the recorded video signal ends before switching to the video signal to be written by the sampling pulse of the next stage.

According to another driving method of the present invention, the sampling pulse writing period starts when the video signal input to the video signal line is a video signal to be written by the preceding sampling pulse, and is applied to the video signal line. A plurality of sampling pulses are generated so that the input video signal is finished before switching to the video signal to be written by the sampling pulse of the next stage.

By generating overlapping sampling pulses by the source line driver circuit according to the present invention, almost the entire period during which the video signal to be written is input can be used for writing the source line. In this manner, the maximum time can be used for writing the source line, so that the video signal can be reliably written to the source line.

In addition, by adopting the source line driving circuit and driving method of the present invention, it is not necessary to generate a sampling pulse shorter than a half cycle of the clock. The source line driver circuit of the present invention can generate a sampling pulse corresponding to the frequency of a clock signal without degrading display quality and without using a transistor that operates at high speed. As described above, the source line driving circuit and the driving method of the present invention are very suitable for increasing the resolution of a display device.

In addition, by generating a sampling pulse in the source line driver circuit according to the present invention, the generation end period of the sampling pulse does not overlap with the writing start period of the subsequent sampling pulse, so that generation of noise in the source line is avoided. can do.

In addition, the driving method of the active matrix display device according to the present invention determines the video signals of all the pixels even when the video signal corresponding to the source line of another stage is written to the source line in the sampling pulse writing period. After that, since the display period starts, display defects such as crosstalk (ghost) do not occur.

Hereinafter, the sampling pulse generation method of the present invention will be described. In the present invention, as shown in FIGS. 1 and 6, the sampling pulse writing is performed by generating adjacent sampling pulses so that the writing end period is after the writing start period of the next-stage sampling pulse. Increase the period.

1 and 6 are timing charts of input signals and output signals of the source line driving circuit of the present invention. Details of the source line driver circuit will be described in an embodiment. Reference numerals such as CK in FIGS. 1 and 6 are the same as those in FIGS. 20 and 21, and thus the description of FIGS. 20 and 21 is used.

In FIGS. 1 and 6, the present invention will be described by focusing on the second sampling pulse (sam_2). The writing period T_2 of the sampling pulse (sam_2) ends after the writing period T_3 of the sampling pulse (sam_3) of the next stage starts. In this way, adjacent sampling pulses (sam_2) and sampling pulses (sam_3) are overlapped.

Further, the writing period T_2 of the sampling pulse (sam_2) starts before the video signal (VIDEO_1) is switched from the video signal (VIDEO_1) to (VIDEO_2), and the video signal (VIDEO_2) is changed from the video signal (VIDEO_2) to (VIDEO_3). It is finished before switching to.

In this manner, the sampling pulse (sam_2) is overlapped with the adjacent sampling pulses (sam_1) and (sam_3), so that the sampling pulse (VIDEO_2) to be written to the video signal line is input for almost all periods. The video signal (VIDEO_2) can be written to the source line by sam_2). That is, according to the present invention, the writing period of the source line can be maximized.

FIG. 1 shows that a video signal (VIDEO_1) to be written by a first stage sampling pulse (sam_1) is input to a video signal line during a writing period T of all sampling pulses (sam_1, sam_2, sam_3,...). Also shows an example started before.

FIG. 6 shows an example in which the writing period T_2 of the sampling pulse (sam_2) is started in a period in which the video signal (VIDEO_1) to be written by the sampling pulse (sam_1) in the previous stage is input to the video signal line. Yes.

When the sampling pulse is generated by the method of the present invention, the video signal (VIDEO_1) to be written to another source line by the previous sampling pulse (sam_1) before the potential of the source line is determined by the sampling pulse (sam_2). Is written to the source line. Accordingly, when the sampling pulse is generated by the method of the present invention, in order to drive the active matrix display device, the pixel portion is not displayed during the period when the video signal is input to the pixel portion, and the video of all the pixels is displayed. After the signal is determined, the pixel portion is changed from the non-display state to the display state. Thus, even if there is a period in which a video signal that should not be written to the source line by the sampling pulse (sam) is written in the writing period T, the display is not adversely affected.

In the following, with reference to the drawings, a specific configuration of a source line driving circuit and a driving method of an active matrix display device for expanding the pulse width of a sampling pulse and extending a writing period will be described in each embodiment. .

However, the present invention can be implemented in many different modes, and it is easy for those skilled in the art to make various changes in form and details without departing from the spirit and scope of the present invention. Understood. Therefore, the present invention should not be construed as being limited to the description of the embodiments. In addition, the same code | symbol in different drawings shows the same component, and the repeated description is abbreviate | omitted.

First, the configuration of the active matrix display device of the present invention will be described with reference to the drawings.

FIG. 15 is a block diagram illustrating a configuration example of the active matrix display device of the present invention. The active matrix display device of the present invention is connected to a pixel portion 10, a source line driving circuit 11, a scanning line driving circuit 12, a plurality of source lines 13 connected to the source line driving circuit 11, and the scanning line driving circuit 12. And a plurality of scanning lines 14. The configuration of the active matrix display device is common to the other embodiments.

The plurality of source lines 13 are arranged in the column direction, and the plurality of scanning lines 14 intersect with the source lines 13 and are arranged in the row direction. In the pixel portion 10, a plurality of pixels 15 are arranged in a matrix corresponding to the matrix formed by the source line 13 and the scanning line 14. The pixel 15 is connected to the scanning line 14 and the source line 13. The pixel 15 includes a switching element and a display element. The switching element controls whether a pixel is selected or not selected according to a signal input to the scanning line 14. The gradation of the display element is controlled by a video signal input from the source line 13.

A configuration example of the pixel 15 will be described with reference to FIGS. 16 and 17. FIG. 16 shows a configuration example of the pixel 15 when the present invention is applied to an active matrix liquid crystal display device. The pixel 15 includes a switching transistor 21 as a switching element and a liquid crystal element 22 as a display element. The switching transistor 21 has a gate connected to the scanning line 14, one of a source and a drain connected to the source line 13, and the other connected to the liquid crystal element 22.

The liquid crystal element 22 includes a pixel electrode, a counter electrode, and a liquid crystal. The alignment of the liquid crystal is controlled by an electric field generated by the pixel electrode and the counter electrode. Liquid crystal is sealed between two substrates of an active matrix liquid crystal display device. The capacitor 23 is an element for holding the potential of the pixel electrode of the liquid crystal element 22, and is connected to the pixel electrode of the liquid crystal element 22.

FIG. 17 shows a configuration example of the pixel 15 when the present invention is applied to an active matrix electroluminescence display device. The pixel 15 includes a switching transistor 31 as a switching element and a light emitting element 32 as a display element. Further, the pixel 15 includes a driving transistor 33 whose gate is connected to the switching transistor 31. The light-emitting element 32 includes a pair of electrodes and a light-emitting material sandwiched between the pair of electrodes.

Hereinafter, a specific configuration of the source line driver circuit of the present invention will be described with reference to FIG. FIG. 2 is a block diagram of the source line driving circuit of this embodiment. FIG. 2 shows a source line driver circuit in which the number of source lines is n. First, second, third,. . . , Nth source lines are respectively X_1, X_2, X_3,. . . , X_n. Note that in this specification and the drawings, wirings, circuits, signals, and the like are assigned to _1, _2, _3,. . . , _N, the first, second, third,. . . Let us denote the nth order.

The source line driver circuit includes a shift register 201 to which a plurality of flip-flops (FF) 200 are connected, n switches (SW) 203, a clock signal line 204 to which a clock signal (CK) is input, and an inverted clock signal ( Inverted clock signal line 205 to which CKB) is input and video signal line 206 to which a video signal (VIDEO) is input. The clock signal (CKB) is an inverted clock signal obtained by inverting the clock signal (CK).

In this embodiment, the shift register 201 has n stages (n is an integer of 2 or more) of flip-flops 200. The flip-flops 200 at each stage are connected to the clock signal line 204 and the inverted clock signal line 205 so that the inputs of the clock signal (CK) and the inverted clock signal (CKB) are alternately switched.

The switch 203 is connected to each source line X_1, X_2, X_3,. . . , X_n and the video signal line 206, and is provided for each source line. Each of the n flip-flops 200 generates and outputs a sampling pulse (sam). The sampling pulse (sam) is input to the switch 203. The switch 203 is controlled to be turned on and off in accordance with a sampling pulse (sam). When the switch 203 is turned on, the source line and the video signal line 206 are brought into conduction, and a video signal (VIDEO) is input to the source line.

FIG. 3 is a circuit diagram of the flip-flop 200. In is an input unit of the flip-flop 200, and out is an output unit. The output unit out is connected to the input unit in of the next-stage flip-flop 200, and the start pulse (SP) is input to the input unit in of the first-stage flip-flop 200. clk1 and clk2 are clock input units. One of the clock input sections clk 1 and clk 2 is connected to the clock signal line 204 and the other is connected to the inverted clock signal line 205. In the configuration example of the shift register 201 in FIG. 2, the odd-numbered clock input unit clk <b> 1 is connected to the clock signal line 204, and the even-numbered clock input unit clk <b> 2 is connected to the inverted clock signal line 205.

The flip-flop 200 includes a P-type transistor 250, a first N-type transistor 251 and a second N-type transistor 252, an inverter 253, and a clocked inverter 254 connected in series.

The source of the P-type transistor 250 is connected to the high power supply potential Vdd, and the source of the second N-type transistor 252 is connected to the low power supply potential Vss. The gates of the P-type transistor 250 and the first N-type transistor 251 are connected to the input part in of the flip-flop 200, and the gate of the second N-type transistor 252 is connected to the clock input part clk1. That is, the circuit composed of these three transistors 250 to 252 includes a P-type transistor connected to Vdd and controlled by a clock signal from a clocked inverter composed of two P-type transistors and two N-type transistors. It corresponds to the excluded circuit.

The inverter 253 has an input connected to the drain of the P-type transistor 250 and the drain of the first N-type transistor 251, and an output connected to the output unit out of the flip-flop 200. The clocked inverter 254 has an input connected to the output of the inverter 253, and an output connected to the input of the inverter 253, the drain of the P-type transistor 250, and the drain of the first N-type transistor 251.

The clocked inverter 254 is means for holding the potential of the node Sa. The clocked inverter 254 is connected to the clock input units clk1 and clk2, and functions as an inverter in synchronization with the clock signal input from the clock input unit clk2. Note that a storage capacitor may be connected to the node Sa instead of the clocked inverter 254 so that the potential of the node Sa is held.

In the source line driver circuit illustrated in FIG. 2, the sampling pulse (sam) is output from the node Sa or the node Sb of the flip-flop 200. The output of the node Sb has a relationship in which the output of the node Sa is inverted.

FIG. 1 is a timing chart of input signals and output signals of the source line driver circuit shown in FIG. In FIG. 1, when the sampling pulse (sam) is output from the node Sa of the flip-flop 200 and the sampling pulse (sam) is at the high level, the switch 203 makes the source line and the video signal line 206 conductive. It is a timing chart when it is the structure which makes them non-conducting at the level.

When the start pulse (SP) changes from High to Low, the P-type transistor 250 of the first flip-flop 200_1 is turned on while the start pulse (SP) is Low, and the input section (in) of each stage of the flip-flop 200 is turned on. A low level signal is transferred to. Further, the node Sa of the flip-flop 200 at each stage changes from Low to High, and the sampling pulses sam_1, sam_2, sam_3,. . . sam_n is generated and output. That is, the sampling pulses sam_1, sam_2, sam_3,. . . , Sam_n write start period Ts is synchronized with the start pulse (SP).

That is, the sampling pulse (sam) is generated so that the writing period T of the sampling pulse (sam) starts before switching to the video signal to be written. In the example of FIG. 1, before switching to the video signal (VIDEO_1), the writing period T of each sampling pulse (sam) starts.

When the start pulse (SP) changes from Low to High, the potential of the node Sa of the first-stage flip-flop 200_1 is held High for ½ period of the clock signal (CK) (Low level period). . When the clock signal (CK) rises, the potential of the node Sa of the first-stage flip-flop 200_1 becomes Low and the potential of the node Sb becomes High.

Accordingly, in the flip-flop 200 in the second and subsequent stages, the potential of the node Sa changes sequentially from High to Low with a ½ cycle delay of the clock signal (CK, CKB), and the potential of the node Sb changes from Low to High. It changes in order.

Therefore, the sampling pulses sam_1, sam_2, sam_3,. . . As shown in FIG. 1, sam_n includes write periods T_1, T_2, T_3,. . . , T_n ends with a half cycle delay according to the clock signals (CK, CKB). As a result, the writing period T (pulse width) of the sampling pulse (sam) becomes longer than one cycle of the clock signal (CK, CKB) by the source line driver circuit of FIG.

A video signal (VIDEO) is input to the video signal line 206 corresponding to the arrangement of the source lines. The numbers 1, 2, and 3 of the video signal (VIDEO) in FIG. 1 indicate that the signals are to be written to the source lines X_1, X_2, and X_3. The writing start period and the writing end period of the sampling pulse (sam) are delayed from the clock signals (CK, CKB) due to an internal delay of the flip-flop 200 or the like. The video signal (VIDEO) is input to the video signal line 206 in consideration of the delay of the sampling pulse (sam).

Each switch 203_1, 203_2, 203_3,. . . , 203_n, sampling pulses sam_1, sam_2, sam_3,. . . , Sam_n are input, the switches 203_1, 203_2, 203_3,. . . , 203_n are turned on and the source lines X_1, X_2, X_3,. . . , X_n starts writing a video signal (VIDEO).

The writing period (T_1, T_2, T_3,..., T_n) of the sampling pulses (sam_1, sam_2, sam_3,..., Sam_n) ends with a half cycle delay of the clock signal (CK, CKB). , The switches 203_1, 203_2, 203_3,. . . , 203_n are sequentially turned off, and the source lines X_1, X_2, X_3,. . . , X_n is determined. To the pixels connected to the scanning line selected during this period, source lines X_1, X_2, X_3,. . . , X_n, a video signal (VIDEO) is written.

For example, when writing to the source line X_2 is started by the sampling pulse (sam_2), first, the video signal (VIDEO_1) is written, the video signal (VIDEO_2) is written in the period Ta_2, and the potential of the source line X_2 is the video signal. The potential is determined to be (VIDEO_2). That is, the period Ta represents a period in which a video signal (VIDEO) to be written to the source line is written by the sampling pulse (sam).

The minimum period of switching of the video signal (VIDEO) is a half cycle of the clock signal (CK, CKB). By setting the sampling end period Tf of the sampling pulse (sam) immediately before the switching of the video signal (VIDEO), the video signal (VIDEO_2) is input during the period Ta_2 in which the video signal (VIDEO_2) is written to the source line X_2. Can be almost equal to the duration. In other words, the period Ta_2 can be made substantially equal to the half cycle of the clock signal (CK, CKB). As described above, in this embodiment, since the maximum time of a half cycle of the clock signals (CK, CKB) can be used for writing the video signal (VIDEO), the video signal (VIDEO) can be reliably written to the source line. .

Further, since the width of the sampling pulse (write period T) is longer than one cycle of the clock signal (CK, CKB), the source line driver circuit of this embodiment has a wide frequency range of the video signal that can generate the sampling pulse.

Further, since the write start period Ts and the write end period Tf are not overlapped by adjacent sampling pulses (sam), it is possible to eliminate the generation of noise in the source line.

As shown in the timing chart of FIG. 1, the writing period T of the sampling pulse (sam) is longer than the period Ta in which the video signal to be written is written, and the video signal to be written in the previous column is also written in the source line. . Therefore, when the display device including the source line driver circuit in FIG. 2 is operated, the pixel unit 10 is in a non-display state during a period in which a video signal is written to the pixel in the pixel portion (hereinafter referred to as an “address accumulation period”). After the accumulation period, the pixel unit 10 is set in a display state, and gradation is displayed in each pixel in accordance with the written video signal data.

A driving method of the active matrix display device of the present invention will be described with reference to FIG. FIG. 18A is a diagram illustrating the scanning line scanning and the relationship between the display period of the pixel portion 10 and the address accumulation period. As shown in FIG. 18A, the address accumulation period τ is included in the non-display period Tnd. In the non-display period Tnd, the m scanning lines Y_1 to Y_m are sequentially selected, and the source lines X_1, X_2,. . . , X_n, the video signal (VIDEO) is written to the pixel 15. After the elapse of the address accumulation period τ, the display period Tdis is started.

FIG. 18B is a diagram illustrating scanning line scanning in the case of performing display by the field sequential method, and the relationship between the display period of the pixel portion 10 and the address accumulation period. In one frame period, the display period is divided into a display period Tdis_R for displaying a red image, a display period Tdis_G for displaying a green image, and a display period Tdis_B for displaying a blue image. Data is accumulated in the pixel 15 in the non-display period Tnd before each display period Tdis_R, Tdis_G, and Tdis_B. In the field sequential method, the frequency of the video signal (VIDEO) increases, but by using the source line driver circuit of FIG. 2, the sampling pulse (sam) can be generated following the frequency of the video signal (VIDEO), Further, the writing period Ta to the source line can be secured.

As shown in FIGS. 18A and 18B, in order to have a non-display period Tnd and a display period Tdis in one frame, in the case of a liquid crystal display device, the backlight is not turned on during the non-display period Tnd. The backlight may be turned on during the display period Tdis. In the case of an electroluminescence display device, the light emitting element 32 (see FIG. 17) may be turned off in the non-display period Tnd and turned on in the display period Tdis. The non-lighting state and the lighting state of the light emitting element 32 can be controlled, for example, by controlling the voltages of both electrodes of the light emitting element 32.

In the source line driver circuit of the present invention, a video signal corresponding to another source line is written to the source line in the address accumulation period τ. After the potentials of all the source lines are determined as shown in FIG. Since the display period Tdis is started, display defects such as crosstalk (ghost) do not occur.

In the source line driver circuit of FIG. 2, the output from the flip-flop 200 is connected to the switch 203, but the output of the flip-flop 200 is connected to the buffer (Buff) 209 as shown in FIG. A sampling pulse (sam) can also be input to the switch 203. An equivalent circuit diagram of the buffer 209 in this case is shown in FIG. For example, the buffer 209 can be composed of an even number of inverters 210 connected in series. FIG. 5 shows an example constituted by two inverters 210 connected in series.

In the timing chart of FIG. 1, the example in which the sampling pulse (sam) is output from the node Sa of the flip-flop 200 has been described, but the sampling pulse (sam) can also be output from the node Sb of the flip-flop 200. In this case, in the source line driver circuit of FIGS. 2 and 4, the switch 203 may be configured to be turned on when the sampling pulse (sam) is Low and turned off when the sampling pulse (Sam) is High. Alternatively, when the switch 203 is a switch that is turned on when the sampling pulse (sam) is High and turned off when the sampling pulse (sam) is Low, a buffer 209 is provided as shown in FIG. It can also be inverted and input to the switch 203. In this case, the buffer 209 may be configured by an odd number of inverters connected in series.

As described above, in the source line driver circuit of FIG. 2, the sampling pulse (sam) can be output from the node Sa or the node Sb of the flip-flop, and the switch 203 or the buffer 209 is adjusted in accordance with the output of the flip-flop 200. The other logic circuits may be added.

In this embodiment, a source line driver circuit having a configuration different from that of Embodiment 1 will be described. In this embodiment, a configuration of a source line driver circuit that generates a sampling pulse having a pulse width longer than a half cycle of a clock signal and shorter than one cycle of a clock will be described.

FIG. 7 is a block diagram of the source line driving circuit of this embodiment. The source line driver circuit includes two-phase shift registers 401 and 402, n switches (SW) 403, n buffers (Buff) 404 connected to the switches 403, and pulses or shift registers output from the shift register 401 The logic circuit 405 includes n logic circuits 405 that perform a logical operation of pulses output from 402. Further, the source line driver circuit includes a clock signal line 406 to which a clock signal (CK1) is input, an inverted clock signal line 407 to which an inverted clock signal (CKB1) is input, and a clock signal line 408 to which a clock signal (CK2) is input. , An inverted clock signal line 409 to which an inverted clock signal (CKB2) is input, and a video signal line 410 to which a video signal (VIDEO) is input. The clock signal (CKB1) is an inverted clock signal obtained by inverting the clock signal (CK1), and the clock signal (CKB2) is an inverted clock signal obtained by inverting the clock signal (CK2).

The shift registers 401 and 402 have a plurality of flip-flops 400. The flip-flops 400 of the shift registers 401 and 402 are circuits having the same configuration. In the shift register 401, the flip-flop 400 in each stage is connected to the clock signal line 406 and the inverted clock signal line 407 so that the inputs of the clock signal (CK1) and the inverted clock signal (CKB1) are alternately switched. In the shift register 402, the flip-flop 400 at each stage is connected to the clock signal line 408 and the inverted clock signal line 409 so that the inputs of the clock signal (CK2) and the inverted clock signal (CKB2) are alternately switched.

The switch 403 is a circuit for conducting the source line and the video signal line 410, and is provided for each source line. A buffer 404 is connected to the sampling pulse input of the switch 403, and the switch 403 is controlled to be turned on and off in accordance with the sampling pulse (sam). When the switch 203 is turned on, the source line and the video signal line 410 are brought into conduction, and a video signal (VIDEO) is input to the source line. The shift registers 401 and 402 share a start pulse (SP).

FIG. 8 is a circuit diagram of the flip-flop 400. The flip-flop 400 is a circuit having the same configuration as the flip-flop 200 of FIG. In FIG. 8, 450 is a P-type transistor, 451 is a first N-type transistor, 452 is a second N-type transistor, 453 is an inverter, and 454 is a clocked inverter. Needless to say, similarly to the flip-flop 200, instead of the clocked inverter 454, a storage capacitor can be connected to the node Sa to hold the potential of the node Sa. In both the shift registers 401 and 402, the output unit out is connected to the input unit in of the next flip-flop 400, and the start pulse (SP) is input to the input unit in of the first flip-flop 400.

In the shift register 401, a clock signal (CK1) is input to the clock input portion clk1 of the odd-numbered flip-flop 400, and a clock signal (CKB1) is input to the clock input portion clk1 of the even-numbered flip-flop. In the shift register 402, the clock signal (CK2) is input to the clock input unit clk1 of the odd-numbered flip-flop 400, and the clock signal (CKB2) is input to the clock input unit clk1 of the even-numbered flip-flop 400. The

The logic circuit 405 is connected to the outputs of two adjacent flip-flops 400. The logic circuit 405 performs a logical operation of the two input pulses. A pulse input to the logic circuit 405 is extracted from either the node Sa or the node Sb of the flip-flop 400. The operation result of the logic circuit 405 is input to the switch 403 through the buffer 404 as a sampling pulse (sam).

In the shift register 401, the flip-flop 400 is connected to the same logic circuit 405 by two stages from the first stage. In the shift register 402, the flip-flop 400 is connected to the same logic circuit 405 by two stages from the second stage. Yes. That is, the output of the 2k-1 stage and 2k stage flip-flop 400 of the shift register 401 is connected to the 2k-1st logic circuit 405, and the 2k stage logic circuit 405 is connected to the output of the shift register 402. The outputs of the 2k stage and 2k + 1 stage flip-flops 400 are connected.

The logic circuit 405 connected to the shift register 401 is connected to the odd-numbered switch 403, and the logic circuit 405 connected to the shift register 402 is connected to the even-numbered switch 403.

FIG. 6 is a timing chart of input signals and output signals of the source line driver circuit of FIG. The timing chart in FIG. 6 uses a NAND circuit for the logic circuit 405, a buffer that inverts and outputs a signal input to the buffer 404, and a switch that is turned on when the sampling pulse (sam) is High. 6 is a timing chart in the case of the source line driving circuit. A circuit diagram of the buffer 404 in this case is shown in FIG. 9, and a circuit diagram of the switch 403 is shown in FIG.

As shown in FIG. 9, the buffer 404 is composed of an odd number of inverters 455 connected in series. FIG. 9 shows an example in which three stages of inverters 455 are connected in series. As shown in FIG. 10, the switch 403 includes an inverter 458 and an analog switch 459.

The operations of the shift registers 401 and 402 are the same as those of the shift register 201 of the first embodiment. That is, the change in the potential of the node Sa of the flip-flop 400 is the same as the sampling pulse (sam) shown in FIG.

The logic circuit 405 of each stage is connected to the output of two adjacent flip-flops. In the timing chart of FIG. 6, a pulse is taken out from the node Sb from the preceding flip-flop, and the subsequent flip-flop. A case where a pulse is extracted from the node Sa from the group 400 is shown. In the logic circuit 405, the two input pulses are NANDed, input to the buffer 404 as a sampling pulse (sam), inverted by the buffer 404, and then input to the switch 403.

In the present embodiment, unlike the first embodiment, the duty ratio of the clock signal (CK1) is not 50%, and the clock signals (CK1, CK2) are High periods (hereinafter referred to as “High periods”) or Low. One of the periods (hereinafter referred to as “Low period”) is longer than ½ period. Further, the clock signal (CK1) and the clock signal (CK2) are input with a phase shift.

The clock signals (CK1, CKB1, CK2, CKB2) can be generated by modulating a reference clock signal having a duty ratio of 50% (pulse width is ½ period). The high period and low period of the clock signals (CK1, CK2) are modulated as shown in FIG. 6 and input to the source line driver circuit, and the logic circuit 405 takes the NAND of the pulse output from the flip-flop 400, thereby A sampling pulse (sam) having the same pulse width as that of the longer period (longer pulse width) of the low period or high period of the signals (CK1, CK2) can be extracted. As a result, the writing period T of the sampling pulse (sam) is longer than ½ period of the clock signals (CK1, CK2) and shorter than one period.

Therefore, in the odd-stage logic circuit 405, a pulse having the same pulse width as that of the Low period of the first clock signal is generated as the odd-stage sampling pulse (sam) in synchronization with the clock signal (CK1). In the even-stage logic circuit 405, a pulse having the same pulse width as the High period of the second clock signal is generated as the even-stage sampling pulse (sam) in synchronization with the clock signal (CK2).

Note that since a NAND circuit is used for the logic circuit 405, the potential of the sampling pulse (sam) output from the logic circuit 405 is at a low level, so that the sampling pulse (sam) is inverted by the buffer 404 and input to the switch 403. ing. FIG. 6 shows a sampling pulse (sam) input to the switch 403.

In the shift register 401 and the shift register 402, the pulse output from the flip-flop 400 at each stage has a pulse width longer than one cycle of the clock signal as in the sampling pulse (sam) of the first embodiment, and 1 Each time the stage shifts, the end period of the pulse is delayed by the same period as the higher period of the clock signal (CK1, CK2) or the longer period. That is, the pulses output from the adjacent flip-flops 400 have a period in which the pulses do not overlap. Therefore, in the source line driving circuit of this embodiment, the logic circuit 405 performs a logical operation on the pulses output from the two adjacent flip-flops 400, thereby extracting a portion where the two pulses do not overlap as a sampling pulse (sam). ing.

In the source line driver circuit of this embodiment, as shown in the timing chart of FIG. 6, by inputting a start pulse (SP) and clock signals (CK1, CK2), the clock signal High is output from the output of the flip-flop 400. A pulse having the same width as that of the longer period or Low period can be taken out as a sampling pulse, and the width of all sampling pulses (sam) can be made longer than a half period of the clock signals (CK1, CK2) and shorter than one period. it can.

Needless to say, due to the characteristics of the transistors of the shift registers 401 and 402 and the logic circuit 405, the width of the sampling pulse extracted from the logic circuit 405 deviates from the same width as the longer one of the high period or the low period of the clock signal. However, the present invention includes such a case. As described above, since the logic circuit 405 performs a logical operation on the pulses output from the two adjacent flip-flops 400, a portion where the two pulses do not overlap is extracted as a sampling pulse (sam). Can be determined based on the longer of the High period or Low period of the clock signals (CK1, CK2).

Further, in the source line driver circuit of this embodiment, sampling pulses (sam) are alternately extracted from the shift register 401 and the shift register 402, so that the subsequent write start period is adjacent to the previous write end period. Sampling pulses (sam) are superimposed. Therefore, it is possible to eliminate the generation of noise on the source line due to the overlap of the sampling pulses (sam).

A video signal (VIDEO) is input to the video signal line 410 corresponding to the arrangement of the source lines. The writing start period of the sampling pulse (sam) is delayed from the clock signals (CK1, CK2) due to an internal delay of the flip-flop 400 or the like. The video signal (VIDEO) is input to the video signal line 410 in consideration of the delay of the sampling pulse (sam).

Also in the source line driver circuit of this embodiment, the writing period of the sampling pulse (sam) at each stage starts before the video signal is switched to the video signal to be written. The minimum period of switching of the video signal (VIDEO) is ½ cycle of the clock signal (CK1, CK2). Also in this embodiment, the period Ta in which the video signal to be written is written to the source line is a half cycle of the clock signal (CK1, CK2), and is substantially synchronized with the period in which the video signal (VIDEO) to be written is input to the video signal line 410. Can be made. Therefore, since the maximum time can be used for writing the video signal (VIDEO) to the source line, the video signal (VIDEO) can be reliably written to the source line.

Also in this embodiment, as in Embodiment 1, the writing period T of the sampling pulse (sam) is longer than the writing period Ta of the video signal to be written, and the video signal to be written in the previous column is also written in the source line. Therefore, in the display device having the source line driver circuit of this embodiment, as in the first embodiment, as shown in FIG. The pixel unit 10 is set in a display state, and gradation is displayed in each pixel according to the written data.

Although the NAND circuit is used for the logic circuit 405 in the source line driver circuit of FIG. 7, other arithmetic circuits can be used. A NOR circuit can also be used for the logic circuit 405. When the logic circuit 405 is a NOR circuit, the output of the node Sa is input to the logic circuit 405 from the flip-flop 400 in the previous stage, and the output of the node Sb is input to the logic circuit 405 from the flip-flop 400 in the subsequent stage. Since the potential of the sampling pulse (sam) output from the NOR circuit is high, the buffer 404 is omitted or the buffer 404 is configured by a circuit in which even-numbered inverters are connected in series, and the input signal is not inverted. What should I do?

In the source line driver circuit of FIG. 7, the switch 403 can be turned on when the sampling pulse (sam) is Low. In the case where a NAND circuit is used for the logic circuit 405, the buffer 404 is omitted or the buffer 404 is configured by a circuit in which an even number of inverters are connected in series, and an input signal is output without being inverted. In the case where a NOR circuit is used for the logic circuit 405, the buffer 404 may be configured by a circuit in which odd-numbered inverters are connected in series, and an input signal may be inverted and output.

As described above, in the source line driver circuit in FIG. 7, the logic of the switch 403, the buffer 404, and the logic circuit 405 may be determined in accordance with the pulse input from the flip-flop 400 to the logic circuit 405.

In the first embodiment, the source line driving circuit (see FIG. 2) in which the video signal line is one system has been described. In the present embodiment, an example will be described in which the video signal lines are k systems (k is an integer of 2 or more) in the source line driving circuit of the first embodiment.

FIG. 12 shows a block circuit diagram of the source line driver circuit of this embodiment. FIG. 12 shows an example in which a video signal is divided into two systems (k = 2). FIG. 11 shows a timing chart of the source line driver circuit of FIG.

Hereinafter, changes from the first embodiment will be described. As shown in FIG. 12, the source line driver circuit of this embodiment has a video signal line 261 for inputting one video signal (VIDEO_A) divided into two systems and a video signal for inputting the other video signal (VIDEO_B). It has a line 262. The video signal (VIDEO_A) is made up of every second video signal (VIDEO_1, 3, 5,...) From the first stage, and every two video signals (VIDEO_B) are arranged from the second stage. Video signals (VIDEO_2, 4, 6,...). The switching of the video signals (VIDEO_A, VIDEO_B) is a half cycle of the clock signals (CK, CKB).

Two switches 203 are connected to the output of one flip-flop 200. Different video signal lines 261 and 262 are connected to the two switches 203 to which the output of the same flip-flop 200 is connected.

As shown in FIG. 11, the sampling pulse (sam) generated by the shift register 201 is the same as that in the first embodiment. In this embodiment, writing of two adjacent source lines X_1 and X_2 is controlled by the first stage sampling pulse (sam_1), and two adjacent source lines X_3 are controlled by the second stage sampling pulse (sam_2). , X_4 writing is controlled, and writing of two adjacent source lines X_2n-1 and X_2n is controlled by the nth sampling pulse (sam_n).

Therefore, by using two video signal lines, the number of source lines can be doubled, that is, the number of pixels in the horizontal direction can be doubled without shortening the writing period Ta to the source lines. it can.

In order to divide a video signal into k and make k video signal lines (the number of video signal lines is k), the i-th (i is an integer of 1 to k) video signal lines are Video signals arranged every kth are input. For example, video signals are input to the first video signal line in the order of VIDEO_1, VIDEO_1 + k, and VIDEO_1 + 2k.

K switches 203 are connected to the output of one flip-flop 200. The k switches 203 to which the outputs of the same flip-flop 200 are connected, in other words, the k switches 203 controlled by the same sampling pulse (sam) are connected to different video signal lines. Similarly to the source line driver circuit of FIG. 4, in the source line driver circuit of FIG. 12, the output of the flip-flop 200 is connected to the buffer (Buff) 209, and the sampling pulse (sam) is sent via the buffer 209. It is also possible to input to the switch 203.

  By using k video signal lines, the number of source lines can be increased k times and the number of pixels in the horizontal direction can be increased k times without shortening the writing period Ta of the source lines.

In the second embodiment, the source line driving circuit (see FIG. 7) has been described as an example in which one video signal line is used. In the present embodiment, an example will be described in which the video signal lines are k systems (k is an integer of 2 or more) in the source line driving circuit of the second embodiment.

FIG. 14 shows a block circuit diagram of the source line driver circuit of this embodiment. FIG. 14 shows an example in which a video signal is divided into two systems (k = 2). FIG. 13 is a timing chart of the source line driver circuit in FIG.

Hereinafter, changes from the second embodiment will be described. As shown in FIG. 14, a video signal line 461 for inputting one video signal (VIDEO_A) divided into two systems and a video signal line 462 for inputting the other video signal (VIDEO_B) are provided. The video signal (VIDEO_A) is made up of every second video signal (VIDEO_1, 3, 5,...) From the first stage, and every two video signals (VIDEO_B) are arranged from the second stage. Video signals (VIDEO_2, 4, 6,...). Further, the switching of the video signals (VIDEO_A, VIDEO_B) is the half cycle of the clock signals (CK, CKB) as in the third embodiment.

In addition, although the buffer 404 is connected to the output of the logic circuit 405, in this embodiment, two switches 403 are connected to the output of one logic circuit 405 (buffer 404). Different video signal lines 461 and 462 are connected to the two switches 403 connected to the output of the same logic circuit 405 (buffer 404). FIG. 13 is a timing chart when the logic circuit 405 is a NAND circuit as in the second embodiment. Of course, in this embodiment, as in the second embodiment, an arithmetic circuit other than the NAND circuit can be used. A NOR circuit can also be used for the logic circuit 405. When the logic circuit 405 is a NOR circuit, the output of the node Sa is input to the logic circuit 405 from the flip-flop 400 in the previous stage, and the output of the node Sb is input to the logic circuit 405 from the flip-flop 400 in the subsequent stage. Since the potential of the sampling pulse (sam) output from the NOR circuit is high, the buffer 404 is omitted or the buffer 404 is configured by a circuit in which even-numbered inverters are connected in series, and the input signal is not inverted. What should I do?

The sampling pulse (sam) generated by the source line driving circuit of this embodiment is the same as that of the second embodiment. In this embodiment, writing of two adjacent source lines X_1 and X_2 is controlled by the first stage sampling pulse (sam_1), and two adjacent source lines are controlled by the second stage sampling pulse (sam_2). Writing of X_3 and X_4 is controlled, and writing of two adjacent source lines X_2n-1 and X_2n is controlled by the nth sampling pulse (sam_n).

Therefore, by using two video signal lines, the number of source lines can be doubled, that is, the number of pixels in the horizontal direction can be doubled without shortening the writing period Ta to the source lines.

In order to divide a video signal into k and make the video signal into k systems (the number of video signal lines is k), the i-th video signal line (i is an integer from 1 to k) The video signal arranged every other is input. For example, video signals are input to the first video signal line in the order of (VIDEO_1), (VIDEO_1 + k), and (VIDEO_1 + 2k).

K switches 403 are connected to the output of one logic circuit 405 (buffer 404). The k switches 403 to which the same logic circuit 405 (buffer 404) is connected, in other words, the k switches 403 controlled by the same sampling pulse (sam) are connected to different video signal lines. By using the k video signal lines, the number of source lines can be increased k times and the number of pixels in the horizontal direction can be increased k times without shortening the writing period Ta of the source lines.

In the source line drive circuits of the second and fourth embodiments, the logic circuit 405 performs a logical operation on the pulses output from two adjacent flip-flops 400, thereby sampling a portion where the two pulses do not overlap with each other as a sampling pulse (sam). Therefore, the writing period T (pulse width) of the sampling pulse (sam) can be determined based not only on the longer one of the high period or the low period of the clock signal (CK1, CK2) but also on the shorter one. it can. In the timing charts of FIGS. 6 and 13, by changing the input waveform of the clock signal (CK1, CK2), the writing period T of the sampling pulse (sam) is set to the High period or Low period of the clock signal (CK1, CK2). The shorter one can be used as a reference.

Accordingly, in the source line driver circuits of Embodiments 2 and 4, the writing pulse T of the sampling pulse (sam) is changed to the clock signals (CK1, CK2) by changing the High period or Low period of the clock signals (CK1, CK2). ) Within a range smaller than one cycle.

By generating a sampling pulse (sam) based on the shorter of the High period or Low period of the clock signals (CK1, CK2), the writing period T is shorter than ½ period of the clock signal, so that they are adjacent to each other. Sampling pulses can be generated without overlapping the pulses. In this case, the address storage interval τ can be overlapped with the display period Tdis as in the conventional driving method of the active matrix display device.

As described above, the source line drive circuits according to the second and fourth embodiments generate the sampling pulses in an overlapping manner by changing the duty ratio of the reference clock signal without changing the circuit configuration (overlapping). And a non-overlapping (non-overlapping) generation, and is a highly versatile circuit.

In this embodiment, an electronic device including the active matrix display device of the present invention as display means will be described. As electronic devices in which the display device of the present invention is used, a television receiver, a camera such as a video camera or a digital camera, a goggle type display, a navigation system, a sound reproduction device (such as a car audio component), a computer, a game device, a portable information terminal (Mobile computer, mobile phone, portable game machine, electronic book, etc.), image playback apparatus (specifically, Digital Versatile Disc (DVD)) provided with a recording medium, and playing back audio data stored in a recording medium such as a digital medium, And an apparatus provided with a display capable of displaying the image data stored therein.

By using the active matrix display device of the present invention for various electronic devices, a high-resolution video can be displayed. Hereinafter, specific examples of these electronic devices will be described with reference to FIGS. 22A to 22E and FIG.

FIG. 22A illustrates a television device, which includes a housing 501, a support base 502, a display portion 503, and the like. In this television device, an active matrix display device having the source line driver circuit of Embodiments 1 to 5 is used for the display portion 503.

  FIG. 22B illustrates a laptop computer, which includes a main body 511, a housing 512, a display portion 513, a keyboard 514, an external connection port 515, a pointing device 516, and the like. As the display unit 513 of the notebook computer, an active matrix display device having the source line driver circuit of Embodiments 1 to 5 is used.

FIG. 22C illustrates a portable computer, which includes a main body 521, a display portion 522, a switch 523, operation keys 524, an infrared port 525, and the like. An active matrix display device having the source line driver circuit of Embodiments 1 to 5 is used for the display portion 522 of the portable computer.

FIG. 22D illustrates a portable game machine including a housing 531, a display portion 532, speaker portions 533, operation keys 534, a recording medium insertion portion 535, and the like. As the display unit 532 of the portable game machine, the active matrix display device having the source line driver circuit of Embodiments 1 to 5 is used.

FIG. 22E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 541, a housing 542, a display portion 543, a display portion 544, a recording medium reading portion 545 ( DVD), operation keys 546, speaker unit 547, and the like. The display unit 543 mainly displays image information, and the display unit 544 mainly displays character information. For at least one of the display portion 543 and the display portion 544, an active matrix display device having the source line driver circuit of Embodiments 1 to 5 is used. In particular, the present invention is suitable for the display unit 543 for image information.

FIG. 23 is an exploded perspective view of the mobile phone. As the display module 550, an active matrix display device having the source line driver circuit of Embodiments 1 to 5 is used. The display module 550 is detachably incorporated in the housing 551. The shape and dimensions of the housing 551 can be changed as appropriate in accordance with the size of the display module 550. A printed circuit board 552 is fitted in the housing 551 to which the display module 550 is fixed.

The display module 550 is connected to the printed circuit board 552 through the FPC 553. A signal processing circuit 558 including a speaker 555, a microphone 556, a transmission / reception circuit 557, a CPU, a controller, and the like is attached to the printed board 552. The display module 550 and the like, the input unit 559, the battery 560, and the antenna 561 are combined and housed in a housing 562. The pixel portion of the display module 550 is arranged so as to be visible from an opening window formed in the housing 562.

Timing chart of input signal and output signal of source line driving circuit of embodiment 1 Block diagram of source line driving circuit of Embodiment 1 Circuit diagram of the flip-flop of FIG. 1 is a block diagram of a source line driving circuit having a buffer according to Embodiment 1. FIG. Circuit diagram of the buffer of FIG. Timing chart of input signal and output signal of source line driving circuit of embodiment 2 Block diagram of source line drive circuit of embodiment 2 Circuit diagram of the flip-flop of FIG. Circuit diagram of the buffer of FIG. Circuit diagram of the switch of FIG. Timing chart of input signal and output signal of source line driving circuit of embodiment 3 Block diagram of source line drive circuit of embodiment 3 Timing chart of input signal and output signal of source line driving circuit of embodiment 4 Block diagram of source line driving circuit of Embodiment 4 FIG. 2 is a block diagram illustrating a configuration example of an active matrix display device of the present invention. The circuit diagram which shows the structural example of the pixel at the time of applying this invention to an active matrix liquid crystal display device The circuit diagram which shows the structural example of the pixel at the time of applying this invention to an active-matrix electroluminescent display apparatus (A) A diagram for explaining a driving method of an active matrix display device of the present invention, (B) a diagram for explaining a driving method when the present invention is applied to a field sequential system. The figure explaining the writing start period of the sampling pulse of this invention, the writing end period, and the writing period Timing chart of input signal and output signal of source line drive circuit of conventional example Timing chart of input signal and output signal of source line drive circuit of conventional example External view of electronic apparatus provided with active matrix display device of present invention 1 is an exploded perspective view of a mobile phone including an active matrix display device of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Pixel part 11 Source line drive circuit 12 Scan line drive circuit 13 Source line 14 Scan line 15 Pixel 21 Switching transistor 22 Liquid crystal element 23 Capacitor 31 Switching transistor 32 Light emitting element 33 Driving transistor 80 Wave line 200 Flip-flop (FF)
201 Shift register 203 Switch (SW)
204 clock signal line 205 inverted clock signal line 206 video signal line 250 P-type transistor 251 first N-type transistor 252 second N-type transistor 253 inverter 254 clocked inverter 261 video signal line 262 video signal line 400 flip-flop (FF )
401 Shift register 402 Shift register 403 Switch (SW)
404 Buffer (Buff)
405 Logic circuit 406 Clock signal line 407 Inverted clock signal line 408 Clock signal line 409 Inverted clock signal line 410 Video signal line 455 Inverter 458 Inverter 459 Analog switch 461 Video signal line 462 Video signal line 501 Housing 502 Support base 503 Display unit 511 Main body 512 Case 513 Display portion 514 Keyboard 515 External connection port 516 Pointing device 521 Main body 522 Display portion 523 Switch 524 Operation key 525 Infrared port 531 Case 532 Display portion 533 Speaker portion 534 Operation key 535 Recording medium insertion portion 541 Main body 542 Case Body 543 Display unit 544 Display unit 545 Recording medium reading unit 546 Operation key 547 Speaker unit 550 Display module 551 Housing 552 Printed circuit board 553 PC
555 Speaker 556 Microphone 557 Transmission / reception circuit 558 Signal processing circuit 559 Input means 560 Battery 561 Antenna 562 Case

CK, CK1, CK2 Clock signal CKB, CKB1, CKB2 Clock signal (inverted clock signal)
SP start pulse VIDEO, VIDEO_A, VIDEO_B Video signal sam_1, sam_2, sam_3, sam_n Sampling pulse X_1, X_2, X_3, X_n Source line Y_1, Y_2, Y_3, Y_n Scan line T Write period (pulse width of sampling pulse)
Ta writing period (period in which video signal to be written is written)
Ts Write start period Tf Write end period Tdis Display period Tnd Non-display period τ Address accumulation period clk1, clk2 Clock input part in Flip-flop input part out Flip-flop output part Vdd High power supply potential Vss Low power supply potential Sa, Sb Node

Claims (1)

A first shift register circuit, a second shift register circuit, n (n is a natural number) logic circuits, n switches, a first wiring, and n second wirings. Have
The 2k−1 (k is a natural number) th logic circuit among the n logic circuits is electrically connected to the 2k−1th output of the first shift register circuit, and the first shift register. Electrically connected to the 2k output of the circuit,
The 2k-th logic circuit of the n logic circuits, the 2 k th output and the second shift register circuit is electrically connected, and 2k +1 th output of the second shift register circuit Electrically connected with
Of the n logic circuits, the i-th logic circuit (i is any one of 1 to n) is electrically connected to the i-th switch of the n switches,
Each of the n switches is electrically connected to the first wiring,
The i-th switch of the n switches, the i-th second wiring of the n second wiring of the present and are electrically connected,
The i-th switch among the n switches is selected from the first wiring and the n second wirings according to an output signal of the i-th logic circuit among the n logic circuits. a function of controlling conduction or non-conduction with the i-th second wiring;
The first shift register receives a first clock signal in which one of the high period or the low period is longer than ½ cycle,
The second shift register receives a second clock signal in which one of the high period or the low period is longer than a half cycle and is out of phase with the first clock signal.
The output signal of the i-th logic circuit of the n logic circuits overlaps with the output signal of the i-1th logic circuit of the n logic circuits, and A source line driver circuit including a period overlapping with an output signal of the (i + 1) th logic circuit .

Images