JP5267566B2 - Multiprocessor count value correction apparatus and multiprocessor having the same - Google Patents

Description

  The present invention relates to a multiprocessor count value correction device and the like, and more specifically, when analyzing a clock cycle count value for each of a plurality of processors driven independently or in cooperation, for example, analyzing a driving state of a multiprocessor. The present invention relates to a multiprocessor count value correction device and the like for correction so that it can be easily used.

  Conventionally, when performing debugging, performance analysis, optimization, etc. of a computer program, the execution status of the program is tracked, and typically the execution of the corresponding part in the program is detected. An execution program is embedded by explicitly joining or implementing a breakpoint mechanism of a processor or the like.

  In the execution program, for example, trace data such as register and memory information corresponding to the address and variable value of the program being executed is generated and saved in a predetermined recording area so as to be traceable. . Further, when performing performance analysis or processing time measurement, for example, it is a typical process to enable analysis by recording the time at which the probe has passed through as trace data.

  As time data at this time, time information acquired from a timer or a real-time clock device or a count value of a clock cycle counter provided in a processor is generally used. In particular, a clock cycle counter is often used when precise time information is required such as directly measuring the execution time of each routine without sampling.

  When such tracking processing, performance analysis, and processing time measurement are performed by a multiprocessor equipped with a plurality of processors, time data obtained by exchanging information via the bus is obtained. The delay is not negligible. In addition, a normal multiprocessor does not have a device with an accuracy of microseconds or less, so the resolution is not sufficient.

  For this reason, Patent Document 1 proposes a method for synchronizing time data for each processor without fixing the processors in a master-slave relationship. This reference 1 calculates the average value of the difference between the received time data from other processors and its own time data by sending its own time data to all of the selected processors. The correction of time data is described.

  Patent Document 2 describes a technique for correcting a clock between terminals connected to a communication line to be common. Patent Document 3 describes a technique for synchronizing an internal clock of an information processing apparatus connected via a communication network.

Japanese Patent Laid-Open No. 01-114964 Japanese Patent Laid-Open No. 07-160358 JP 2000-285038 A

  However, recent multiprocessors are not limited to being driven with the clock frequency (operating frequency) of the processor kept constant. For example, in order to reduce power consumption, for example, each processor is appropriately triggered by a predetermined trigger. Some of them are driven by changing the clock frequency.

  For this reason, as trace data, even if the clock cycle count value, which is the time data when the clock frequency for each processor is changed in this way, is recorded as it is, the count rate is different if the clock frequency is different. It cannot be used as it is when performing tracking processing, performance analysis, or processing time measurement.

  By the way, although the size of one routine depends on the presence or absence of a loop, it may be less than 100 instructions if it is small. In such a case, a processor that operates at several hundred MHz to several GHz. The execution time at can be less than 1 microsecond.

  On the other hand, since the clock cycle counter operates so as to increase as the processor clock advances, the clock cycle counter has a resolution that satisfies even the above-described high-definition applications. Further, since the clock cycle counter directly reads the count value from the processor register or the like, the delay required for the reading is considerably smaller than that of the device connected via the bus. For example, in an Intel IA-32 architecture processor, the clock cycle counter can obtain the value using an instruction (RDTSC: Read Time Stamp Counter) for reading a time stamp counter register, and a delay at the time of reading Is about several tens of cycles.

  In the case of a multiprocessor, since a clock cycle counter is usually prepared for each processor, it is preferable to use this as a time counter of the processor in order to share time data.

  However, in the multiprocessor, if the processors are different, the value of the counter may be deviated from the beginning. Especially when the multiprocessor is equipped with a power management function and the operating speed of each processor is changed by changing the clock frequency according to the power consumption and processing volume trends, Sometimes it is driven by.

  For this reason, in a multiprocessor, for example, when executing an application program that has been multithreaded for the purpose of using a plurality of processors in order to increase performance, the multiprocessor performs parallel processing across the plurality of processors. In this case, since the way of the time of the reference clock differs depending on the processor that performs the execution process, accurate measurement cannot be performed. Further, in the case of a program that executes parallel processing, such as an OS (Operating System) kernel, if there is a bottleneck that delays processing by a specific function, the performance of the entire system deteriorates.

  That is, in such a program, it is necessary to share the elapsed time measured by the clock cycle counter for each processor in the multiprocessor when performing debugging, performance analysis, or optimization.

  The present invention has been made in view of the above circumstances. When a multiprocessor has a function capable of changing the operating frequency for each processor, the clock cycle count value for each processor is corrected to a common elapsed time. Another object of the present invention is to provide a multiprocessor count value correction device and the like that can easily perform tracking processing, performance analysis, optimization processing, and the like.

  In order to solve the above-described problem, a first configuration of the present invention relates to a multiprocessor count value correction apparatus, a change detecting means for detecting a change in operating frequency for each processor constituting the multiprocessor, and the operating frequency. For each processor that counts based on the operating frequency, a changed processor identification information acquiring unit that acquires the identification information of the processor that has changed the operating frequency, an operating frequency acquiring unit that acquires the operating frequency after the operating frequency is changed Change count value acquisition means for acquiring a change count value when the operation frequency of the clock cycle counter is changed, and history information by associating the acquired operation frequency and the change count value with identification information of the corresponding processor Change history holding means to hold as the identification information It is characterized in that it comprises a time derivation means for deriving the virtual time of each of the processors on the basis of the history information of the work frequency and the change at the time count value.

  The second configuration of the present invention relates to a count value correction method for a multiprocessor, and monitors whether or not the operating frequency of each processor constituting the multiprocessor is changed, and detects a change in the operating frequency of the processor. When the operating frequency of the clock cycle counter for each processor that counts based on the operating frequency is changed, and the operating frequency at the time of the change are acquired together with the identification information of the processor. It is stored as history information in association with identification information, and a virtual time for each processor is derived based on the history information of the operating frequency and the change count value associated with the identification information. It is said.

  The third configuration of the present invention relates to a multiprocessor count value correction program, which is executed by one of the processors while holding the necessary information in the memory by being read by a computer equipped with the multiprocessor. As a step, a change detection step for monitoring the presence or absence of a change in operating frequency for each processor and detecting a change in the operating frequency; a changed processor identification information acquiring step for acquiring identification information of the processor whose operating frequency has been changed; An operating frequency acquisition step for acquiring the operating frequency after the change of the operating frequency, and a count value at the time of changing the operating frequency of the clock cycle counter for each processor that counts based on the operating frequency The change count value acquisition step and the acquired A change history holding step for holding the operating frequency and the change count value in association with the identification information of the processor as history information, and the operating frequency and the change count value associated with the identification information. And a time deriving step for deriving a virtual time for each processor based on history information.

  According to the configuration of the present invention, the changed operating frequency and the clock cycle count value at the time of the change are held as history information for each processor, and the virtual time is derived from the history information as appropriate. Each clock cycle count value can be shared as a virtual time. Therefore, the clock cycle count value for each processor in the multiprocessor is set to a virtual time that is not affected by the change of the operating frequency, and a desired analysis process or the like can be easily and efficiently performed based on the virtual time.

1 is a block diagram schematically showing an electrical configuration of a multiprocessor according to an embodiment of the present invention. It is a graph explaining the clock cycle count value used in the embodiment. It is a flowchart which shows the operation processing procedure of the multiprocessor of the embodiment. 4 is a flowchart showing a processing procedure for acquiring an operating frequency and a clock cycle count value of the multiprocessor according to the embodiment. It is a conceptual diagram which shows the acquisition result of the operating frequency and clock cycle count value of the multiprocessor of the embodiment. 4 is a flowchart showing a correction processing procedure of a clock cycle count value of the multiprocessor according to the embodiment. 7 is a flowchart subsequent to FIG. 6, illustrating a correction processing procedure for a clock cycle count value of the multiprocessor according to the first embodiment. It is a block diagram which shows schematically the electric structure of the multiprocessor which concerns on the apparatus which can be added to the same embodiment. It is a conceptual diagram which shows the clock cycle count value and its processing result which are used with the same apparatus. It is a flowchart which shows the synchronous processing procedure of the clock cycle count value as a reference | standard processor in the same apparatus. It is a flowchart which shows the synchronous processing procedure of the clock cycle count value as a response processor in the same apparatus. It is a flowchart which shows the operation processing procedure of the multiprocessor of the same apparatus.

  A multi-processor including a plurality of processors capable of changing the operating frequency, a change detecting unit that detects a change in the operating frequency for each processor, a changed processor identification information acquiring unit that acquires the identification information of the processor that has changed the operating frequency, The operating frequency acquisition means for acquiring the operating frequency after the change of the operating frequency and the count value at the time of changing the operating frequency of the clock cycle counter for each processor that counts based on the operating frequency are acquired The change count value acquisition means, the change history holding means for holding the acquired operating frequency and the change count value in association with the identification information of the corresponding processor and holding it as history information, and the identification information Based on the history information of the operating frequency and the count value at the time of change Time deriving means for deriving a virtual time for each processor, and the time deriving means corrects the change count value for each processor with the corresponding operation frequency, and before and after the change of the operation frequency. Thus, it is configured to derive a virtual time to increase at a common constant speed.

  The best mode for carrying out the invention will be described below with reference to the drawings.

Embodiment

  FIGS. 1 to 7 show a multiprocessor equipped with a multiprocessor count value correction apparatus that implements a multiprocessor count value correction method by causing a computer to read and execute a multiprocessor count value correction program according to the present invention. FIG. 4 illustrates an embodiment of a processor. FIG. 1 is a conceptual configuration diagram showing a schematic overall configuration of the multiprocessor count value correction device, FIG. 2 is a graph for explaining clock cycle count values when the operating frequency is changed for each processor in the multiprocessor, and FIG. FIG. 4 is a flowchart for explaining the acquisition of the clock cycle count value for each processor in the program executed by the multiprocessor. FIG. 4 is a flowchart for explaining the operation frequency changed by the processor of the multiprocessor and the acquisition of the clock cycle count value at that time. FIG. 5 is a conceptual diagram illustrating the acquisition and retention of the operating frequency and the clock cycle count value at the time of the change, and FIGS. 6 and 7 illustrate the correction processing of the clock cycle count value counted at the different operating frequency. It is a flowchart to do.

  In FIG. 1, a multiprocessor 100 can be used as a work area by a ROM (Read Only Memory) 111 in which first to n-th processors 101 to 10n (n is a natural number of 2 or more) that stores a processing program or the like in advance. A RAM (Random Access Memory) 112 and a bus 113 are commonly connected and mounted in the computer. The first to n-th processors 101 to 10n individually process each role while identifying each other based on the processor ID (identifier: identification information) held by the processor ID holding unit 11, or It is constructed so as to function as a multiprocessor that cooperates by processing the roles assigned to each other in parallel.

  The first to n-th processors 101 to 10n are constructed so as to be driven while being synchronized at a speed corresponding to a clock frequency (operation frequency) set in advance in the clock frequency setting unit 12, respectively. The clock cycle count value at a speed corresponding to the clock frequency is counted and held by the clock cycle count value holding unit 13 to achieve synchronization. That is, the first to n-th processors 101 to 10n can directly acquire the clock cycle count value without using the bus 113 (without delay) by incorporating the clock cycle count value holding unit 13. it can. For this reason, for example, it is possible to provide a resolution that satisfies even a high-definition application that counts an execution time of 1 microsecond or less that executes a routine that is less than 100 instructions.

  Furthermore, the first to n-th processors 101 to 10n are provided with instructions / commands from the computer main body (first to n-th processors 101 to 10n themselves) based on the processing program in the ROM 111 in order to reduce power consumption. Accordingly, the clock frequency as the driving speed can be individually changed and set in each clock frequency setting unit 12. Here, in this embodiment, the program itself stored in the ROM 111 is simply referred to as the program 111 and will be briefly described.

  For example, as shown in FIG. 2, the first processor 101 is driven by changing / setting (updating) the clock frequency in order of 100 MHz, 50 MHz, and 150 MHz. On the other hand, the second processor 102 is driven by changing and setting the clock frequency in order of 25 MHz, 100 MHz, and 150 MHz. In this case, the clock cycle count value of the first processor 101 is 150 M cycles (C1), while the clock cycle count value of the second processor 102 is 50 M, despite the same timing T1. Cycle (C2). In addition, 150 M cycles (C1) is counted as the clock cycle count value at a timing different from the timing T2 for the second processor 102 while the first processor 101 is at the timing T1.

  From this, the multiprocessor 100 corrects the clock cycle count value for each of the first to n-th processors 101 to 10n to, for example, an elapsed time that is increased at the same speed as real time without being affected by the change of the clock frequency. A common function is derived by deriving the virtual time. Accordingly, the multiprocessor 100 complicates processing such as software debugging, performance analysis, and optimization because the clock cycle count value is counted at a different clock frequency for each of the first to n-th processors 101 to 10n. Therefore, it is possible to realize an easy process that simply uses the corrected virtual time. Note that the virtual time is not limited to a constant speed. For example, the virtual time may be corrected to an elapsed time that progresses in common on the basis of the clock cycle count value of the first processor 101. Since correction is simple, it is preferable to perform correction processing as in this embodiment as will be described later.

  Specifically, the multiprocessor 100 detects a change in the clock frequency executed by the first to nth processors 101 to 10n by a power management event or the like, and the clock cycle count value at that time and the changed clock frequency Keep the record. Then, the multiprocessor 100 can calculate (derived) the virtual time by performing a correction for making the held clock cycle count value common to the first to n-th processors 101 to 10n and integrating them. For example, since the first processor 101 shown in FIG. 2 operates at 100 MHz (cycles / second) between 0 and 100 M cycles, a typical actual elapsed time is 100 M cycles / 100 MHz = 1.0. This means that 1.0 second has passed. Similarly, since it was operating at 50 MHz between 100 and 150 M cycles, (150-100) /50=1.0, and 1.0 second has elapsed. Furthermore, since it was operating at 150 MHz between 150 and 300 M cycles, (300−150) /150=1.0, and 1.0 second has elapsed. For this reason, in this case, these are integrated and 3.0 seconds have elapsed. That is, the multiprocessor 100 performs the correction processing on the clock cycle count values of the first to n-th processors 101 to 10n in the same manner to calculate the virtual time, whereby various trace data corresponding to the clock cycle count values are obtained. Can be generalized and shared to facilitate measurement and analysis.

  For example, when the multiprocessor 100 calls and executes the performance measurement software execution probe 111a stored in the program 111 by the first to nth processors 101 to 10n, the multiprocessor 100 makes the clock cycle count value common. A virtual time is derived by performing processing. That is, when the execution probe 111a is executed, the first to n-th processors 101 to 10n collect trace data such as clock cycle count values, write them in the trace data storage unit 112a secured in the RAM 112, and store and hold them. Performance measurement. In the execution of the execution probe 111a at this time, the performance measurement is efficiently performed by correcting the trace data collected by the first to n-th processors 101 to 10n to the virtual time using the performance measurement software as a target program. Can also be done easily.

  Specifically, the multiprocessor 100 allows the processor ID acquisition unit 21, the clock cycle count value acquisition unit 22, and the clock frequency change when the first to n-th processors 101 to 10 n execute the execution probe 111 a while using the RAM 112. The unit 23, the clock frequency change detection unit 24, and the clock cycle count value correction unit 25 are configured to function. The multiprocessor 100 is configured such that the RAM 112 functions as the clock frequency change history holding unit 26.

  The processor ID acquisition unit 21 obtains the processor ID from the processor ID holding unit 11 for each of the first to n-th processors 101 to 10n, for example, when executing performance measurement of the target program based on an instruction / command at a predetermined opportunity. Take out and get. That is, the processor ID acquisition unit 21 constitutes a changed processor identification information acquisition unit that acquires the ID of the processor whose clock frequency has been changed.

  Similarly, the clock cycle count value acquisition unit 22 confirms a clock frequency change in the first to n-th processors 101 to 10n by, for example, a clock frequency change detection unit 24 to be described later, based on an instruction / command at a predetermined timing. When (detected), the clock cycle count value held by the clock cycle count value holding unit 13 for each of the first to n-th processors 101 to 10n is extracted and acquired. In other words, a change count value acquisition unit that acquires a clock cycle count value (change count value) when the clock cycle count value acquisition unit 22 detects a change in clock frequency (operation frequency) is configured.

  The clock frequency changing unit 23 changes the clock frequency set in the clock frequency setting unit 12 for each of the first to n-th processors 101 to 10n according to a predetermined trigger such as an instruction from the power management mechanism or the like. To update.

  The clock frequency change detection unit 24 refers to and acquires the clock frequency set in the clock frequency setting unit 12 for each of the first to n-th processors 101 to 10n and updates the setting (clock frequency by the clock frequency changing unit 23). (Rewriting of) is detected and a change in the clock frequency is detected. That is, the clock frequency change detecting unit 24 constitutes an operating frequency obtaining unit that obtains the changed clock frequency (operating frequency), and also constitutes a change detecting unit that detects a change in the clock frequency (operating frequency).

  The clock frequency change history holding unit 26 acquires the clock cycle count value acquired by the clock cycle count value acquisition unit 22 together with the changed clock frequency acquired when the clock frequency change detection unit 24 detects the change of the clock frequency. Is stored in association with each processor ID of the corresponding first to n-th processors 101 to 10n as a change history. In other words, a change history holding means for holding the clock frequency and the clock cycle count value (change time count value) when the clock frequency change history holding unit 26 detects a change in the clock frequency as history information for each change is configured. .

  The clock cycle count value correction unit 25 calculates a common virtual time for advancing at a constant speed from the change history information (the changed clock frequency and the changed clock cycle count value) stored and held by the clock frequency change history holding unit 26. For example, the RAM 112 is temporarily recorded and held so that it can be used for performance measurement execution processing. That is, the clock cycle count value correcting unit 25 constitutes time deriving means for deriving the virtual time based on the history information of the clock frequency and the change count value.

  Thereby, for example, the multiprocessor 100 associates the changed clock frequency and the changed clock cycle count value for each processor ID for each of the first to n-th processors 101 to 10n that perform performance measurement. It can be stored and retained as change history information. Then, the clock cycle count value for each of the first to n-th processors 101 to 10n is corrected and made common to, for example, a virtual time that is increased at the same constant speed as the actual time lapse based on the change history information. It can be used later for performance measurement.

  Next, performance measurement during execution of the target program will be described with reference to the flowcharts shown in FIGS. 3, 4, 6, and 7 and the conceptual diagram of the change history information shown in FIG.

  For example, when the first processor 101 measures the performance of a target program that is executed by the other second to n-th processors 102 to 10n in cooperation, processing according to the flowchart of FIG. 3 is executed. First, it repeats in the middle of the execution of the target program, and program control shifts to the execution probe 111a (step S11). In the program control by the execution probe 111a, collection and recording of trace data necessary for performance measurement other than the virtual time deriving process by correcting the clock frequency is executed (step S12). Next, for each of the first to n-th processors 101 to 10n, the processor ID acquisition unit 21 acquires the processor ID from the processor ID holding unit 11 (step S13), and the clock cycle count value acquisition unit 22 holds the clock cycle count value. A clock cycle count value is acquired from the unit 13 (step S14). Thereafter, the execution probe 111a associates the acquired clock cycle count value with the processor ID and stores it in the trace data storage unit 112a as trace data (step S15), and then stores it in the target program for performance measurement. The program control is shifted to end this execution program (step S16). Here, in the following, the program control of the execution probe 111a will be simply described as the execution probe 111a.

  At this time, the execution probe 111a performs the process according to the flowchart of FIG. 4 in the execution program which the 1st-nth processors 101-10n process in parallel. First, for each of the first to n-th processors 101 to 10n, the clock frequency change detection unit 24 refers to the clock frequency set in the clock frequency setting unit 12 and compares it with the previously acquired clock frequency. Whether or not the clock frequency has been changed is repeatedly confirmed during the execution of the target program (step S21). If the change in the clock frequency cannot be detected, this process is terminated as it is, and the process returns to the target program for performance measurement by the execution program. On the other hand, when the change of the clock frequency is detected, the processor ID acquisition unit 21 extracts and acquires the processor ID from the processor ID holding unit 11 of the corresponding processor (step S22). Next, the clock cycle count value acquisition unit 22 extracts and acquires the clock cycle count value held in the clock cycle count value holding unit 13 of the corresponding processor (step S23). At the same time, the clock frequency change detection unit 24 acquires again the changed clock frequency set in the clock frequency setting unit 12 of the processor (step S24). After this, after the clock frequency and clock cycle count value acquired by the clock frequency change history holding unit 26 are associated with the processor ID and added to the end of the previous change history information as a change history and stored (step S29). This processing is terminated, and the process returns to the target program for performance measurement by the execution program.

  For example, the clock frequency change history of the first and second processors 101 and 102 shown in FIG. 2 includes a clock cycle count value (CC) and a clock frequency (frequency) for each processor ID as shown in FIG. Are stored in the clock frequency change history holding unit 26 in association with each other.

  Here, as a process for recording the change of the clock frequency, the case where it is configured in the execution probe 111a as described above has been described as an example. However, the present invention is not limited to this, and the following configuration is also possible. . First, apart from the execution probe and the target program, a program for writing a clock frequency change history is prepared as a part of the clock frequency change detection unit 24. Next, triggered by an interrupt caused by a power management event or the like, the clock frequency change detection unit 24 checks whether the clock frequency of the interrupted processor has been changed. If the clock frequency has been changed, the change history of the processor is written to the clock frequency change history holding unit 26 according to the procedure described above. After the writing is completed, the interrupt processing routine is ended, and the processing is returned to the normal program execution. By adopting such a configuration, the clock frequency change history accumulation process can be implemented independently of the target program and the execution probe.

  When analyzing the performance measurement when executing the target program, the first to n-th processors 101 to 10n are singly or cooperate to efficiently and easily perform the performance measurement (analysis). Therefore, the execution probe 111a corrects the clock cycle count value stored and held as the trace data in the trace data storage unit 112a to obtain a virtual time that is a common elapsed time among the first to n-th processors 101 to 10n. The derivation process to calculate is started.

  For example, the execution probe 111a executes processing according to the flowcharts of FIGS. First, after resetting the variable m to be prepared in the RAM 112 (m = 0) (step S31), the variable m is incremented (m = m + 1) (step S32), and the mth is stored in the trace data storage unit 112a. It is confirmed whether or not the trace data is stored and held (step S33).

  In the initial step S33, at least one or more pieces of trace data exist at the start of the performance measurement analysis. Therefore, the clock cycle count value of the first trace data in the trace data storage unit 112a and the processor ID associated therewith are read out and stored in the RAM 112 (step S34).

  Next, the processor ID of the trace data stored and held in the RAM 112 is confirmed and specified (step S35), and the unprocessed information associated with the processor ID as history information in the clock frequency change history holding unit 26 is confirmed. The earliest change history entry of the clock frequency and clock cycle count value with the oldest time is read out and stored in the RAM 112 (step S36).

  Thereafter, it is confirmed whether or not the change history entry is stored and held in the RAM 112 (step S37). If the change history entry cannot be confirmed because the clock frequency has not been changed, as will be described later. The end process in this performance measurement analysis is executed as it is.

  On the other hand, if the clock frequency has been changed at least once in this step S37 and the change history entry has been confirmed, the clock cycle count value of the earliest change history entry held in the RAM 112 (hereinafter referred to as change) The history count value is also compared with the clock cycle count value of the trace data (hereinafter also referred to as the trace data count value) (step S41). That is, here, the first change history count value with the oldest time is compared with the trace data count value (step S41).

  In this step S41, when the earliest change history count value is larger than the trace data count value, the clock frequency is not changed when the trace data count value is obtained, so that the performance measurement is performed as described later. A termination process for the trace data count value in the analysis is executed.

  On the other hand, if the earliest change history count value is smaller than the trace data count value in this step S41, the clock frequency has been changed before the trace data count value is acquired, so The change history count value before change is subtracted from the previous change history count value (step S42). That is, here, the increment is calculated by subtracting the change history count value before change that does not exist from the earliest change history count value (step S42). After this, the increment count value of the increment is obtained by dividing the clock frequency before the change, that is, the clock frequency that has not been changed, that is, the default clock frequency set in the clock frequency setting unit 12 in advance. Thus, the first elapsed time can be calculated (step S43). Then, the first elapsed time is added (integrated) to the accumulated elapsed time in the RAM 112 and stored (step S44).

  Next, as in the previous step S 36, the next clock frequency and clock cycle count value (subsequent change history entry) associated with the same processor ID is read as history information in the clock frequency change history holding unit 26. It is stored and held in the RAM 112 (step S45).

  After this, similarly, it is confirmed whether or not the subsequent change history entry is stored and held in the RAM 112 (step S46), and the correction processing up to the final clock frequency change is completed and the subsequent change is completed. If the history entry cannot be confirmed, the end processing for the trace data count value in the performance measurement analysis is executed as it is, as will be described later.

  On the other hand, when the clock frequency is continuously changed and the subsequent change history entry can be confirmed in step S46, the process returns to step S41 and the subsequent change history count value and trace data count held in the RAM 112 are returned. Compare the value.

  Also in this second step S41, if the subsequent change history count value is larger than the trace data count value, the clock frequency is not changed when the trace data count value is acquired, and will be described later. As described above, the end processing for the trace data count value in the performance measurement analysis is executed as it is.

  On the other hand, also in this second step S41, if the subsequent change history count value is smaller than the trace data count value, the clock frequency has been changed again before the trace data count value is acquired, so The same process is executed. That is, an increment is calculated by subtracting the previous earliest change history count value from the subsequent change history count value (step S42), and the second elapsed time is calculated by dividing the increment count value by the clock frequency before the change. The second elapsed time is calculated (step S43), added (integrated) to the accumulated elapsed time (first elapsed time) in the RAM 112, and stored (step S44).

  After this, there is a subsequent change history entry that has not been read from the clock frequency change history holding unit 26, the subsequent change history count value is smaller than the trace data count value, and the clock is acquired before the trace data count value is acquired. As long as the frequency is changed again, steps S41 to S46 are repeated. Thus, the accumulated elapsed time is calculated by adding the k-1 elapsed time obtained by dividing the increment up to the last subsequent change history count value by the clock frequency before the change until the clock frequency is changed. The accumulated elapsed time is stored and held in the RAM 112.

  On the other hand, when it is confirmed in step S41 that the subsequent change history count value is larger than the trace data count value and the clock frequency is changed after the trace data count value is obtained, The process ends.

  In this end processing, the final subsequent change history count value is subtracted from the trace data count value to calculate an increment (step S51), and the increment count value is divided by the final clock frequency to obtain the final k-th elapsed time. After calculating the time (step S52), the final k-th elapsed time is added (integrated) to the accumulated elapsed time in the RAM 112 and stored (step S53). Next, the accumulated elapsed time corresponding to the first trace data count value stored and held in the RAM 112 is used as a virtual time common to the other second to n-th processors 102 to 10n, and the processor ID is associated with the trace data count value. Then, it is transferred to the performance measurement (analysis) of the target program (step S43). Thereafter, the derivation process for the trace data count value is terminated, and the process returns to step S32.

  Thereafter, by incrementing the variable m (m = m + 1), the total elapsed time corresponding to the trace data count value is calculated for all m pieces of trace data stored and held in the trace data storage unit 112a. The correction process (steps S32 to S54) for the virtual time can be repeated, and the clock cycle count value of the trace data to be corrected does not exist in the trace data storage unit 112a, and the correction process is completed. When it has been confirmed (step S33), a series of correction processing ends.

  By the way, when it is confirmed in step S46 that the subsequent change history entry cannot be confirmed in the RAM 112 and the clock frequency change itself has been completed, the trace data count value in the performance measurement analysis is confirmed. The process proceeds to the end process (steps S51 to S54). In this termination process, similarly, the final k-th elapsed time calculated by dividing the increment count value from the trace data count value to the final subsequent change history count value by the final clock frequency is stored in the RAM 112. Is added (integrated) to the accumulated elapsed time to obtain a virtual time, which is transferred to the performance measurement (analysis) of the target program in association with the processor ID together with the trace data count value, and returns to step S32.

  In the case of a processor in which the first change history entry cannot be confirmed in the RAM 112 and the clock frequency itself has not been changed in step S37, the clock frequency set in the clock frequency setting unit 12 in advance. Is acquired and stored in the RAM 112 (step S38), and the process proceeds to the end process in the performance measurement analysis (steps S51 to S54). Similarly, in this termination processing, the virtual time calculated by dividing the increment count value (trace data count value itself) up to the trace data count value by the default clock frequency is calculated together with the trace data count value. The data is transferred to the performance measurement (analysis) of the target program in association with the ID, and the process returns to step S32.

  As described above, according to this embodiment, the clock frequency after the change and the clock cycle count value at the time of the change are acquired and retained as history information, and the trace used when performing the performance measurement analysis of the target program, etc. Virtual time according to the data count value (actual timing) can be calculated and integrated (derived). Therefore, the trace data count value can be corrected and shared with a virtual time that is separated from the clock frequency at which the first to n-th processors 101 to 10n operate and increases at a constant speed that is the same as the actual elapsed time. . As a result, for example, the performance measurement of the target program can be processed simply, easily and efficiently without complicating the clock frequency of the first to n-th processors 101 to 10n.

  This correction processing of the trace data count value acquires only the clock frequency and clock cycle count value at the time of change together with the processor IDs of the first to n-th processors 101 to 10n during the performance measurement execution process of the target program 111. Therefore, the scan and calculation processing of the clock frequency and the clock cycle count value at the time of change necessary for calculating the virtual time are not burdened, and the execution probe 111a can be comfortably operated. Trace data etc. can be collected while being executed.

  Next, FIGS. 8 to 12 show a multiprocessor that implements the multiprocessor count value correction method by causing a computer to read and execute a multiprocessor count value correction program that can be added to the above-described embodiment. It is a figure which shows an example of a count value correction apparatus. Here, since an example of this multiprocessor is configured in substantially the same manner as in the above-described embodiment, the same reference numerals are given to the same configurations and the characteristic portions will be described using the drawings. FIG. 8 is a conceptual configuration diagram showing a schematic overall configuration of a count value correction device that synchronizes the count start timing of the clock cycle count value for each processor, and FIG. 9 is a conceptual diagram illustrating the exchange between the processors and the processing results thereof. 10 and 11 are flowcharts for explaining the synchronization processing of the count start timing of the clock cycle count value for each processor. FIG. 12 is a flowchart for explaining the correction of the clock cycle count value in the program executed by the processor. .

  In FIG. 8, a multiprocessor 200 includes first to n-th processors 101 to 10n that are commonly connected to a bus 113 together with a ROM 111 and a RAM 112 and are mounted in a computer, like the multiprocessor 100 in the above-described embodiment. . The first to n-th processors 101 to 10n function as multiprocessors based on the processor IDs in the respective processor ID holding units 11. The first to n-th processors 101 to 10n are synchronized by counting and holding a count value of a speed corresponding to a clock frequency preset in the clock frequency setting unit 12 by a clock cycle count value holding unit 13. I take the. That is, in the multiprocessor 200, each of the first to n-th processors 101 to 10n counts the clock cycle count at a fixed clock frequency without changing the clock frequency as in the above-described embodiment.

  The multiprocessor 200 includes a processor ID acquisition unit 21 and a clock cycle count value acquisition unit 22 as in the above-described embodiment, and trace data when performing performance measurement is stored in the trace data storage unit 112a in the RAM 12. Accumulate and hold on.

  In addition, the multiprocessor 200 includes a clock difference measurement unit 31 that functions when the first to nth processors 101 to 10n execute the execution probe 111a using the RAM 112, and the RAM 112 includes the order count value holding unit 32. The clock difference holding unit 33 is configured. The multiprocessor 200 includes these units, and performs, for example, synchronization processing for resetting the clock cycle count value used when performing performance measurement or the like so that the count start timing of the clock cycle count value is the same timing. The trace data for each of the nth processors 101 to 10n is corrected so as to be processed with higher accuracy.

  Here, since the first to n-th processors 101 to 10n are sequentially activated and started to drive in high definition, the count start of the built-in clock cycle count value holding unit 13 is also delayed. For example, as shown in FIG. 9, when the second processor 102 starts driving after the first processor 101 starts driving, the clock cycle count value in the clock cycle count value holding unit 13 starts counting. There is a shift of the delay amount d.

  Therefore, the first to n-th processors 101 to 10n match the count start timing of the clock cycle count value with the other processors, respectively, and use the clock cycle count value with high reliability and easily for analysis. To be able to.

  Specifically, the first to n-th processors 101 to 10n are controlled by the execution probe 111a so that one of them is a reference processor and the other is a corresponding processor of a cooperating partner. By exchanging these signals, the shift of the clock cycle count value due to the start timing between the first to n-th processors 101 to 10n is reset. For example, as shown in FIG. 9, the execution probe 111a exchanges predetermined signals between the reference processor 101 and the response processor 102, and acquires the clock cycle count value at each, thereby starting timing between them. The synchronization process for resetting the deviation of the clock cycle count value due to is executed according to the following procedure. First, under the control of the execution probe 111a executed by the reference processor 101, the processor ID acquisition unit 21 acquires and specifies the processor ID in the processor ID holding unit 11. Also, the clock cycle count value acquisition unit 22 uses the first clock cycle count value A of the reference processor 101, the second clock cycle count value B of the response processor 102, and the third clock cycle count value of the reference processor 101 as the order count value. C is sequentially acquired and stored in the order count value holding unit 32. After this, on the contrary, under the control of the execution probe 111a executed by the response processor 102, the response processor 102 responds to the reference processor 101 in parallel with the response processor 102 acting as the reference processor. By responding as a processor, the first to third clock cycle count values a, b, and c that are sequentially acquired are stored and held in the order count value holding unit 32 as the reverse order count value. That is, the execution probe 111a constitutes an order count value acquisition unit that exchanges between the reference processor 101 and the corresponding processor 102 to acquire an order count value.

By the way, assuming that there is no deviation in the count start timing of the clock cycle count value holding unit 13 between the reference processor 101 and the response processor 102, the forward path and the return path in the exchange of predetermined signals when the reference processor 101 functions as the reference processor. Can be calculated by the following equation:
S = (C + A) / 2−B
On the contrary, the transmission delay s between the forward path and the return path in the exchange of a predetermined signal when the reference processor 101 functions as a response processor can be calculated by the following equation.
s = (c + a) / 2−b

The transmission delays S and s between the reference processor 101 and the response processor 102 can be offset because the transmission speeds in the forward path and the return path are the same. However, there is actually a difference in the count start timing of the clock cycle count value holding unit 13. From this, after the cancellation, the delay count value d corresponding to the difference in the count start timing of the clock cycle count value holding unit 13 in the reference processor 101 and the response processor 102 can be calculated as a difference, The count value d can be derived from the following equation.
d = S−s = (C−c) / 4 + (A−a) / 4− (B−b) / 2

  Then, the first to n-th processors 101 to 10n use the clock cycle count values A to C and a to c in the order count value holding unit 32 acquired by operating as the reference processor and the corresponding processor, and use the clock difference. The measurement unit 31 derives a count value d, which is a difference (difference) in the count start timing of the clock cycle count value holding unit 13, for each response processor corresponding to the reference processor. Then, the clock difference holding unit 33 stores and holds the processor ID and the count value correction value d (synchronization correction value) for each response processor in association with the processor ID of the reference processor. That is, the clock difference measuring unit 31 constitutes a correction value deriving unit, and the clock difference holding unit 33 constitutes a correction value holding unit.

  For example, as shown in FIG. 9, when the first processor 101 cooperates with the response processor 102 as a reference processor, the first clock cycle count value A = 75, the second clock cycle count value B = 125, the third clock By acquiring the cycle count value C = 225 and having the second processor 102 operate as the reference processor, the first clock cycle count value a = 275, the second clock cycle count value b = 425, It is assumed that the clock cycle count value c = 425 is acquired and held in the order count value holding unit 32. Then, the clock difference measuring unit 31 substitutes these count values A to C and a to c into the above formulas, so that the count value d due to the shift in the count start timing of the clock cycle count value holding unit 13 of the response processor 102 is obtained. = 50 is calculated (derived), and the clock difference holding unit 33 stores and holds the count value correction value d. As a result, the reference processor 101 stores and holds its own clock cycle count value t1 = 825 in the trace data storage unit 112a as it is when the performance measurement analysis of the target program is executed, whereas the clock cycle of the response processor 102 The count value correction value = 50 stored and held in the clock difference holding unit 33 is added to the count value t2 = 875 as the delay count value, and the clock cycle count value t2 = 925 is accumulated and held in the trace data accumulation unit 112a. . As a result, the first and second processors 101 and 102 can execute the analysis and the like by accurately correcting the processing time even in the performance measurement analysis and the like in cooperation.

  Next, performance measurement during execution of the target program will be described with reference to the flowcharts shown in FIGS.

  First, when performing performance measurement when executing a target program, for example, when the first processor 101 executes the target program in cooperation with the other second to n-th processors 102 to 10n, Before starting the execution process, in other words, before each of the processors 101 to 10n starts driving under the control of the execution probe 111a, the execution probe 111a responds with the first processor 101 as a reference processor. The synchronization processing shown in FIGS. 10 and 11 is executed for each of the second to n-th processors 102 to 10n of the processor. The synchronization processing in the reference processor 101 is shown in the flowchart of FIG. 10, while the synchronization processing in the response processor 102 is shown in the flowchart of FIG.

  Specifically, the reference processor 101 first resets the variable p prepared in the RAM 112 (p = 0) (step S110). Thereafter, the processor ID acquisition unit 21 acquires its own processor ID in the processor ID holding unit 11 and the clock cycle count value acquisition unit 22 counts and holds the clock cycle count value holding unit 13 in the first clock cycle count. The value A is acquired and stored in the order count value holding unit 32 in association with the processor ID (step S111). Next, the reference processor 101 instructs the response processor 102 to acquire and return the processor ID together with the second clock cycle count value B (step S112), and the clock processor count value B and the processor ID are received from the response processor 102. Wait until it is sent (step S113). Here, in the following, various information is acquired by performing internal processing for each of the first and second processors 101 and 102, and similarly, the processor ID is acquired by the processor ID acquisition unit 21 in the same way. Since the clock cycle count value is acquired from each clock cycle count value holding unit 13 as well as the clock cycle count value from each processor ID holding unit 11 for each 102, in the following description, for example, the processor It will be briefly described that an ID is acquired.

  On the other hand, the response processor 102 waits for an instruction to acquire and return the second clock cycle count value B and the processor ID from the reference processor 101 in parallel with the processing of the reference processor 101. (Step P211) When the instruction is confirmed, like the reference processor 101, the second clock cycle count value B and the processor ID are acquired and transmitted to the reference processor 101 (Step P212), and the next instruction is the reference processor. It waits until it is sent from 101 (step P213).

  Next, when the reference processor 101 receives the second clock cycle count value B and the processor ID sent from the response processor 102 (step S113), the reference processor 101 stores the second clock cycle count value B and the processor ID in the order count value holding unit. 32, the third clock cycle count value C and the processor ID are acquired and stored in association with the order count value holding unit 32 in the same manner as in step S111. (Step S115).

  Thereafter, the reference processor 101 operates as the reference processor and transmits a drive instruction to execute the same processing as steps S111 to S115 to the response processor 102 (step S116), and the response processor 102 operates as the response processor. It waits for an instruction to be sent (step S117).

  On the other hand, when the response processor 102 receives the drive instruction to operate as the reference processor from the reference processor 101 (step P213), the response processor 102 acquires the first clock cycle count value a and the processor ID and stores them in the order count value holding unit 32. After associating and storing (step P214), the reference processor 101 is instructed to acquire and return the second clock cycle count value b and the processor ID (step P215), and the second clock cycle count value. Wait until b and the processor ID are sent from the reference processor 101 (step P216).

  On the other hand, the reference processor 101 waits for an instruction to acquire and return the second clock cycle count value b and the processor ID from the response processor 102 (step S117), and confirms the instruction. The second clock cycle count value b and the processor ID are acquired and transmitted to the response processor 102 (step S118), and the first to third clock cycle count values a to c and the processor ID collected from the response processor 102 are transmitted. Wait until it is received (step S119).

  On the other hand, when the response processor 102 receives the second clock cycle count value b and the processor ID sent from the reference processor 101 (step P216), the response processor 102 stores the second clock cycle count value b and the processor ID in the order count value holding unit. After the third clock cycle count value c and the processor ID are acquired and stored in association with each other in the order count value holding unit 32 (step P218). Then, the series of first to third clock cycle count values a to c and the processor ID are associated with each other and transmitted to the reference processor 101 (step P219), thereby completing one process as the response processor. .

  When the reference processor 101 receives the first to third clock cycle count values a to c and the respective processor IDs transmitted from the response processor 102 (step S119), the acquired and held clock cycle count values A to C are received. C, a to c are identified by the processor ID and the storage order, and are substituted into the above formula to calculate the count value correction value d for the cooperating response processor 102, and the processor is stored in the clock difference holding unit 33. It is stored in association with the ID and its derivation count p (step S120).

  After this, the reference processor 101 increments the variable p in the RAM 112 (p = p + 1), counts the number of derivations p of the count value correction value d for the response processor 102 (step S121), and then derives the number of derivations p Is reached (step S122). If the derivation number p has not reached the set number, the process returns to step S111 and the same process is repeated.

  On the other hand, when it is confirmed that the derivation number p has reached the set number, the average value of the count value correction values d for the set number of times is calculated and the clock difference is held as the average count value correction value d for the response processor 102. The unit 33 stores the information in association with the processor ID (step S123), and completes a series of processes as the reference processor.

  When executing the performance measurement of the target program, for example, in the first processor 101, as shown in FIG. 12, the program control shifts to the execution probe 111a (step S311), and the above-described synchronization processing (step After executing S110 to S123) for each of the second to n-th processors 102 to 10n cooperating (step S312), collection and recording of trace data necessary for performance measurement is performed (step S313). Thereafter, the processor ID acquisition unit 21 acquires and acquires the processor IDs of the second to n-th processors 102 to 10n that cooperate with each other (step S314), and is associated with the processor ID. Then, the average count value correction value d stored and held in the clock difference holding unit 33 is read and acquired (step S316). As a result, the clock cycle count value collected for use in performance measurement and stored as trace data in the trace data storage unit 112a is corrected by the average count value correction value d corresponding to the processor ID, The trace data accumulating unit 112a can be stored and held (step S317), and thereafter, program control is transferred to the target program to be measured for performance and the execution program is terminated (step S318).

  Thus, according to this additional device, it is possible to correct and share the trace data count value having the same count start timing for each of the first to n-th processors 101 to 10n. Therefore, the analysis of the performance measurement of the target program and the like can be performed with high accuracy without the accuracy being lowered due to the difference in the count start timing counted by the clock cycle count value holding unit 13 of the first to n-th processors 101 to 10n. Can be executed.

  Needless to say, the additional device described above can be used alone, but when mounted together with the above-described first embodiment, the clock can be changed for each of the first to n-th processors 101 to 10n. The virtual time to be shared by correcting the trace data count value counted by frequency can be matched with the count start time, and the analysis of the performance measurement of the target program can be executed more reliably. .

  The synchronization processing of the clock cycle count value count start timing is not limited to immediately after the start of execution of the target program. For example, if the clock frequency is changed repeatedly, errors that can be ignored are accumulated and calculated. There is a possibility that the reliability will be lost at the virtual time. From this, the clock frequency of the first to n-th processors 101 to 10n is fixed to a constant value at every preset interval or time, or according to an instruction command at an arbitrary timing, and the above-mentioned synchronization By executing the process, it is possible to reset the reliability decrease of the derived virtual time.

  As described above, the embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and there are design changes and the like without departing from the gist of the present invention. However, it is included in this invention.

  For example, in the above-described embodiment, the virtual time is derived by repeating the process of accumulating the elapsed time calculated from the increment of the clock cycle count value until the clock frequency is changed for each trace data count value. This is not a limitation. For example, the integrated value up to the nth elapsed time in the correction processing of the previous trace data count value is held, and the integrated value up to the nth elapsed time is calculated from the increment of the trace data count value to be corrected next. The accumulated elapsed time that is the virtual time may be derived by integrating the (n + 1) th elapsed time.

  Further, in the above-described embodiment, when a plurality of processors are mounted, a case has been described in which a virtual time that is not affected by a change in clock frequency is derived and the elapsed time is shared, but the present invention is not limited thereto. . For example, even a device equipped with a single processor can be applied when the increasing tendency of the clock cycle count value changes due to the change of the clock frequency, and the elapsed time of the clock cycle count value is generalized by virtual time. Thus, analysis and the like can be facilitated.

  In the above-described embodiment, the target program for performance measurement has been described as an example. However, the present invention is not limited to this. For example, the processing time and the like can be individually reset and reset at the reference time without using statistical calculation. Since it can be performed, it can be applied to general programs. For example, it can also be used to create high-performance programs that efficiently use computing resources.

  The present invention can be widely applied to high-performance programs that operate on a multiprocessor and efficiently use computational resources.

11 processor ID holding unit 12 clock frequency setting unit 13 clock cycle count value holding unit 21 processor ID acquisition unit (changed processor identification information acquisition unit, corresponding processor identification information acquisition unit)
22 Clock cycle count value acquisition unit (count value acquisition means at change)
23 Clock frequency change unit 24 Clock frequency change detection unit (change detection means, operating frequency acquisition means)
25 Clock cycle count correction unit (time deriving means)
26 Clock frequency change history holding unit (change history holding means)
31 Clock difference measuring unit (correction value deriving means)
32 Order count value holding unit 33 Clock difference holding unit (correction value holding means)
100, 200 Multiprocessors 101 to 10n First to nth processors 101 Reference processor 102 Response processor 111 ROM (target program)
111a execution probe (order count value acquisition means)
112 RAM
112a Trace data storage unit

Claims (16)

Change detection means for detecting a change in operating frequency for each processor that constructs a multiprocessor;
Changed processor identification information acquisition means for acquiring identification information of the processor that has changed the operating frequency;
Operating frequency acquisition means for acquiring the operating frequency after the change of the operating frequency;
A change count value acquisition means for acquiring a change count value when the operation frequency of the clock cycle counter for each processor that counts based on the operation frequency is changed;
Change history holding means for holding the acquired operating frequency and the count value at the time of change as history information in association with identification information of the corresponding processor;
A time deriving unit for deriving a virtual time for each processor based on the history information of the operating frequency and the change count value associated with the identification information. Correction device.   The time deriving means corrects the change count value for each processor with the corresponding operating frequency, and derives a virtual time to increase at a common constant speed before and after the change of the operating frequency. The multiprocessor count value correction apparatus according to claim 1.   The time deriving means corrects and adds the increment of the change count value during the period before the change of the operating frequency in the history information by the corresponding operating frequency, and then adds the final of the operating frequency. The virtual time to the derivation target count value for each processor is derived by correcting and accumulating the increment increased from the change in the derivation target count value by the corresponding operating frequency. The multiprocessor count value correction apparatus according to claim 1 or 2. A predetermined order count value in the reference processor and the corresponding processor by exchanging in a predetermined order between the processors, with any one as a reference processor and any other as a corresponding processor Order count value acquisition means for acquiring
Corresponding processor identification information acquisition means for acquiring identification information of at least the corresponding processor;
Correction value derivation for deriving a synchronization correction value necessary for resetting a deviation of the count value of the clock cycle counter for the corresponding processor from the count value of the clock cycle counter for the reference processor based on the order count value Means,
2. The correction value holding means for holding the synchronization correction value for resetting a deviation of the count value of the corresponding processor with respect to the count value of the reference processor in correspondence with identification information of the corresponding processor. The multiprocessor count value correction apparatus according to 2 or 3. The sequence count value acquisition means acquires the second sequence count value B returned in response to the request to the corresponding processor after acquiring the first sequence count value A of the reference processor. The sequence processing for obtaining the third sequence count value C of the reference processor is executed again, and then the sequence processing is executed by reversing the reference processor and the corresponding processor to perform the reverse first to third sequence count values a. , B, c
The correction value deriving means calculates the synchronization correction value d using the following equation:
d = (C−c) / 4 + (A−a) / 4− (B−b) / 2
5. The multiprocessor count value correction apparatus according to claim 4, wherein the correction value holding means holds the calculated synchronization correction value d in association with the identification information of the corresponding processor.   A multiprocessor comprising the multiprocessor count value correction apparatus according to claim 1.   The operating frequency of the clock cycle counter for each processor that counts based on the operating frequency when a change in the operating frequency of the processor is detected by monitoring whether or not the operating frequency of each processor constituting the multiprocessor is changed. The change count value at the time of the change and the operating frequency at the time of the change are acquired together with the identification information of the processor, stored as history information in association with the identification information, and associated with the identification information. A multiprocessor count value correction method, comprising: deriving a virtual time for each processor based on the history information of the operating frequency and the change count value.   8. The multi-time according to claim 7, wherein the change count value for each processor is corrected by the corresponding operating frequency to derive a virtual time for increasing at a common constant speed before and after the change of the operating frequency. Processor count value correction method.   The derivation target after the last change of the operating frequency after correcting and accumulating the increment of the count value at the time of change increased in the history information before the change of the operating frequency by the corresponding operating frequency 9. The virtual time to the derivation target count value for each processor is derived by correcting and accumulating the increment increased up to the count value of the processor by the corresponding operating frequency. The multiprocessor count value correction method described. A predetermined order count value in the reference processor and the corresponding processor by exchanging in a predetermined order between the processors, with any one as a reference processor and any other as a corresponding processor And after obtaining at least the identification information of the corresponding processor,
Deriving a synchronization correction value necessary for resetting a deviation of the count value of the clock cycle counter for the corresponding processor with respect to the count value of the clock cycle counter for the reference processor based on the order count value; 10. The multiprocessor count value correction method according to claim 7, wherein the synchronization correction value is held in correspondence with identification information of the corresponding processor. After obtaining the first order count value A of the reference processor as the order count value, the second order count value B returned in response to the request to the corresponding processor is obtained again after obtaining the second order count value B. An order process for obtaining the third order count value C of the reference processor is executed, and thereafter, the order process in which the reference processor and the corresponding processor are inverted is executed, and the reverse first to third order count values a, b , After obtaining c
The synchronization correction value d is calculated using the following equation:
d = (C−c) / 4 + (A−a) / 4− (B−b) / 2
11. The multiprocessor count value correction method according to claim 10, wherein the synchronization correction value d is held in correspondence with the identification information of the corresponding processor. As a step executed by any of the processors while holding necessary information in the memory by being read by a computer equipped with a multiprocessor,
A change detection step for monitoring the presence or absence of a change in operating frequency for each processor and detecting the change in the operating frequency;
A changed processor identification information acquisition step for acquiring identification information of the processor whose operating frequency has been changed;
An operating frequency acquisition step of acquiring the operating frequency after the change of the operating frequency;
A change count value acquisition step of acquiring a change count value at the time of change of the operation frequency of the clock cycle counter for each processor that counts based on the operation frequency;
A change history holding step for holding the acquired operating frequency and the count value at the time of change as history information in association with identification information of the corresponding processor;
A time derivation step for deriving a virtual time for each processor based on the history information of the operating frequency and the change count value associated with the identification information. Correction program.   In the time deriving step, the virtual time that is increased at a common constant speed before and after the change of the operating frequency is derived by correcting the change count value for each processor by the corresponding operating frequency. The multiprocessor count value correction program according to claim 12.   In the time deriving step, the increment of the count value at the time of change increased within a period before the change of the operating frequency in the history information is corrected and integrated with the corresponding operating frequency, and then the final of the operating frequency The virtual time to the derivation target count value for each processor is derived by correcting and accumulating the increment increased from the change in the derivation target count value by the corresponding operating frequency. 14. The multiprocessor count value correction program according to claim 12 or 13. A predetermined order count value in the reference processor and the corresponding processor by exchanging in a predetermined order between the processors, with any one as a reference processor and any other as a corresponding processor Order count value acquisition step to acquire,
A corresponding processor identification information obtaining step for obtaining at least identification information of the corresponding processor;
Correction value derivation for deriving a synchronization correction value necessary for resetting a deviation of the count value of the clock cycle counter for the corresponding processor from the count value of the clock cycle counter for the reference processor based on the order count value Steps,
13. A correction value holding step for holding the synchronization correction value for resetting a shift in the count value of the corresponding processor with respect to the count value of the reference processor in correspondence with identification information of the corresponding processor. 15. A multiprocessor count value correction program according to claim 13 or 14. In the order count value obtaining step, after obtaining the first order count value A of the reference processor, the second order count value B returned in response to the request to the corresponding processor is obtained. The sequence processing for obtaining the third sequence count value C of the reference processor is executed again, and then the sequence processing is executed by reversing the reference processor and the corresponding processor to perform the reverse first to third sequence count values a. , B, c
In the correction value deriving step, the synchronization correction value d is calculated using the following equation:
d = (C−c) / 4 + (A−a) / 4− (B−b) / 2
16. The multiprocessor count value correction program according to claim 15, wherein in the correction value holding step, the calculated synchronization correction value d is held in correspondence with the identification information of the corresponding processor.

Images