JP5276282B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device including a nonvolatile memory cell having a tunnel diffusion layer.

  2. Description of the Related Art A FLOTOX (Floating Gate Tunnel Oxide) type EEPROM (Electrically Erasable and Programmable ROM) is a semiconductor memory in which a non-volatile memory cell is configured by a stacked gate type memory cell transistor and a selection transistor connected in series to the stacked gate type memory cell transistor. In an EEPROM, a memory cell portion in which a plurality of memory cells are integrated, a peripheral circuit portion in which row / column decoders and other peripheral circuits are integrated, and an input / output portion in which input / output pads are arranged are formed on a single semiconductor substrate. Configured.

  A plurality of nonvolatile memory cells as described above are arranged in the memory cell portion. A logic circuit composed of MOS transistors and other circuit elements is formed in the peripheral circuit portion. The input / output unit includes a plurality of input / output pads arranged on the periphery of the semiconductor substrate, and an electrostatic discharge (ESD) countermeasure transistor for countermeasures against element destruction caused by a surge from these pads. .

FIG. 4 is a cross-sectional view for explaining a configuration example of a nonvolatile memory cell, a MOS transistor constituting a peripheral circuit, and an electrostatic breakdown countermeasure transistor. The nonvolatile memory cell 70, the MOS transistor 80, and the electrostatic breakdown countermeasure transistor 90 are formed on the p-type semiconductor substrate 60 in common.
The nonvolatile memory cell 70 has a stacked gate type memory cell transistor 71 and a selection transistor 72. The memory cell transistor 71 is a floating element disposed so as to face the n-type source region 73 and the n-type tunnel diffusion layer 74 formed at a distance in the surface layer portion of the semiconductor substrate 60 and the channel region 75 therebetween. A gate 76 and a control gate 77 stacked on the floating gate 76 are provided. The n-type tunnel diffusion layer 74 functions as the drain region of the memory cell transistor 71. On the other hand, the select transistor 72 uses the n-type tunnel diffusion layer 74 as its source region, and an n-type drain region 78 formed in the semiconductor substrate 60 with a predetermined interval therebetween, and the tunnel diffusion layer 74 and the drain region 78. And a gate 79 arranged so as to face the channel region therebetween.

  A gate insulating film 61 is interposed between the semiconductor substrate 60 and the floating gate 76 and the gate 79. The floating gate 76 and the control gate 77 are insulated by the insulating film 62. In the gate insulating film 61, a thin film portion is formed between the tunnel diffusion layer 74 and the floating gate 76. This thin film portion is a tunnel window 65 for allowing electrons to pass between the tunnel diffusion layer 74 and the floating gate 76 by FN (Fowler-Nordheim) tunneling.

  The MOS transistor 80 forming the peripheral circuit has an LDD (Lightly Doped Drain) structure in order to suppress the hot electron effect. That is, the MOS transistor 80 includes an n-type source region 81 and an n-type drain region 82 formed at a distance in the surface layer portion of the semiconductor substrate 60, and a gate insulating film 61 so as to face the channel region therebetween. And an n-type low concentration layer 85 disposed in a region between the edge of the gate 84 and the source / drain regions 81 and 82. The impurity concentration of the low concentration layer 85 is lower than that of the source / drain regions 81 and 82. In order to secure the low concentration layer 85, sidewalls 86 are provided along both side surfaces of the gate 84. That is, after the low concentration ion implantation (LDD implantation) for the low concentration layer 85 is performed, the high concentration ion implantation for the source / drain regions 81 and 82 is performed by using the sidewall 86 as a mask, whereby the LDD structure is formed. Is formed.

The electrostatic breakdown countermeasure transistor 90 includes a source region 91 and a drain region 92 formed in the semiconductor substrate 60, and a gate 94 disposed through a gate insulating film 61 so as to face the channel region therebetween. It has a single drain structure. Side walls 95 formed simultaneously with the formation of the MOS transistor 80 are formed on both side surfaces of the gate 94. The source / drain regions 91 and 92 are formed to extend to a region immediately below the sidewall 95. That is, the source / drain regions 91 and 92 are respectively formed by performing ion implantation (ESD implantation) in advance before the sidewall 95 is formed. After the sidewall 95 is formed, high concentration layers 91a and 92a are formed in the source / drain regions 91 and 92 in the same process as the ion implantation for the source / drain regions 81 and 82 of the MOS transistor 80. . The source / drain regions 91 and 92 have an impurity concentration higher than that of the low concentration layer 85 of the MOS transistor 80. As a result, the ESD protection transistor 90 has a single drain structure instead of an LDD structure, thereby solving the problem of soft leakage after applying an electrostatic pulse (see Patent Document 1).
Japanese Patent Laid-Open No. 6-132489

In the ESD implantation, in order to make the ESD protection transistor 90 have a single drain structure, it is necessary to perform ion implantation at a higher concentration than the LDD implantation. Therefore, LDD injection and ESD injection must be separate processes.
Therefore, in order to fabricate an EEPROM having the above-described configuration, ion implantation for the tunnel diffusion layer, ESD implantation, LDD implantation, and ion implantation for the source / drain regions of the MOS transistor must be performed. Thus, since many ion implantation processes are required, there is a problem that the production process of the EEPROM is long and the production efficiency is poor.

  Further, the EEPROM may be provided with a high breakdown voltage MOS transistor in the peripheral circuit. In this case, the high breakdown voltage MOS transistor has a DDD (Double Diffused Drain) structure as a countermeasure against hot carriers. . In order to form the DDD structure, it is necessary to perform low-concentration ion implantation to a deep position of the semiconductor substrate with high energy, and thus the number of ion implantation steps is further increased.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device in which the production efficiency is improved by reducing the number of impurity introduction steps.

According to a first aspect of the present invention, there is provided a non-volatile memory cell having a tunnel diffusion layer and a MOS transistor having a low concentration layer having a lower impurity concentration than the drain region on the channel portion side of the drain region. And an electrostatic breakdown countermeasure transistor on a common semiconductor substrate, wherein the MOS transistor region is a region for the nonvolatile memory cell in a plan view of the semiconductor substrate. And a region disposed between the region for the ESD protection transistor and a first concentration in the region for the non-volatile memory cell and the region for the ESD protection transistor in the semiconductor substrate. The tunnel diffusion layer is formed in the region for the non-volatile memory cell by selectively introducing impurities in the step, and at the same time the static A first impurity introduction step for forming a source region and a drain region of the breakdown countermeasure transistor, and selectively introducing an impurity at a second concentration lower than the first concentration into the MOS transistor region in the semiconductor substrate. To selectively introduce impurities at a third concentration higher than the second concentration (preferably higher than the first concentration) in the MOS transistor region; And a third impurity introduction step of forming a source region and a drain region of the MOS transistor by introducing the MOS transistor.

  According to this method, in the first impurity introduction step, the source region and the drain region of the ESD protection transistor are formed simultaneously with the formation of the tunnel diffusion layer. Therefore, the dedicated impurity introduction step for forming the source region and the drain region of the ESD protection transistor can be omitted, and the number of impurity introduction steps can be reduced. Thus, the number of impurity introduction steps can be reduced when manufacturing a semiconductor device including a nonvolatile memory cell, a MOS transistor having a low concentration layer, and an electrostatic breakdown countermeasure transistor on a common semiconductor substrate. Thereby, the production process of a semiconductor device can be shortened and production efficiency can be improved.

  According to a second aspect of the present invention, the third impurity introduction step selectively introduces impurities at the third concentration into the MOS transistor region and the electrostatic breakdown countermeasure transistor region, A step of forming a source region and a drain region of a MOS transistor, and simultaneously forming a high-concentration layer having a higher impurity concentration than the source region and the drain region in the source region and the drain region of the ESD protection transistor, respectively; A method for manufacturing a semiconductor device according to claim 1. With this configuration, simultaneously with the formation of the source / drain regions of the MOS transistor, a high-concentration layer for making the source / drain regions of the ESD protection transistor ohmic contact with the electrode can be formed simultaneously.

  According to a third aspect of the present invention, a floating gate facing the tunnel diffusion layer is formed in the non-volatile memory cell region, and a gate is formed in each of the MOS transistor region and the electrostatic breakdown countermeasure transistor region. And a sidewall forming step of forming a sidewall made of an insulator on the side wall of the gate, and the first impurity introduction step is performed before the gate forming step, The second impurity introduction step is performed after the gate formation step and before the sidewall formation step, and the third impurity introduction step is performed after the sidewall formation step. 2. A method for producing a semiconductor device according to 2.

  The floating gate needs to be formed so as to face the tunnel diffusion layer. Therefore, the first impurity introduction step for forming the tunnel diffusion layer must be performed before the formation of the floating gate. Therefore, the gate of the ESD protection transistor formed in the same process as the floating gate is formed in a process after the formation of the source / drain regions. The gate length of the ESD protection transistor is longer than that of a fine MOS transistor constituting a peripheral circuit in the memory cell region. Therefore, the gate of the electrostatic breakdown countermeasure transistor has a large width so as to overlap the source / drain region in consideration of mask misalignment between the mask for the first impurity introduction step and the mask for gate formation. It is preferable to form as follows.

  On the other hand, if the second impurity introduction step is performed after the gate of the MOS transistor is formed, and the third impurity introduction step is performed after the sidewall is formed on the side wall of the gate, a low concentration layer region is secured immediately below the sidewall. it can. Thus, the MOS transistor can surely have a low concentration layer on the channel region side of the drain region. Since the first impurity introduction step is performed prior to the formation of the sidewalls, in the ESD protection transistor, the first concentration source / drain regions extend to the region immediately below the sidewalls. As a result, the ESD protection transistor can have a single drain structure.

The second impurity introduction step may be a step of introducing impurities in a self-aligned manner with respect to each gate of the MOS transistor and the electrostatic breakdown countermeasure transistor.
In the gate forming step, it is preferable that a selection gate is simultaneously formed in the nonvolatile memory cell region at a position separated from the floating gate by a predetermined distance so that an edge portion overlaps the tunnel diffusion region. In this case, further, a step of forming a source region in a region partially overlapping with the floating gate, facing the tunnel diffusion layer with a predetermined distance, and facing the tunnel diffusion layer with a predetermined distance Preferably, the method further includes a step of forming a drain region in a region partially overlapping with the selection gate. Thereby, a memory cell having a structure in which the memory cell transistor and the selection transistor are connected in series can be formed.

The method may further include a control gate forming step of forming a control gate so as to be stacked on the floating gate via an insulating film. Thereby, the memory cell transistor can be formed as a stacked gate type transistor.
The invention according to claim 4 is the method of manufacturing a semiconductor device according to claim 3, wherein the third impurity introducing step includes a step of introducing impurities into the semiconductor substrate in a self-aligned manner with respect to the sidewall. . By this method, in the MOS transistor region, the low concentration layer can be left only directly under the side wall, and a so-called LDD structure can be formed.

  According to a fifth aspect of the present invention, the second impurity introduction step includes a step of forming a low concentration layer extending to a region deeper than the source region and the drain region of the MOS transistor, and the third impurity introduction step includes the step of introducing the third impurity. It is a manufacturing method of the semiconductor device as described in any one of Claims 1-4 including the process of forming the said source region and drain region in a low concentration layer. By this method, a so-called DDD structure can be formed in the MOS transistor region. When the MOS transistor has a high breakdown voltage specification, this DDD structure is preferable.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic plan view for explaining the configuration of an EEPROM which is a semiconductor device according to an embodiment of the present invention. The semiconductor device includes a p-type semiconductor substrate 1 made of, for example, silicon, a memory cell region 2 set in the central portion of the semiconductor substrate 1, and peripheral circuit regions 3 and 4 arranged around the memory cell region 2. , 5 and 6 and an input / output region 7 arranged at the peripheral edge of the semiconductor substrate 1.

In the memory cell region 2, a plurality of nonvolatile memory cells are arranged in a matrix. The memory cell region 2 is formed in a substantially rectangular shape, a peripheral circuit region 3 is disposed along one side thereof, and another peripheral circuit region 4 is disposed along another side orthogonal to the one side. Yes.
The peripheral circuit regions 3 and 4 are decoder circuits for selectively performing write, read, and erase operations on the nonvolatile memory cells in the memory cell region 2. Since the nonvolatile memory cell has a high breakdown voltage specification, a high breakdown voltage specification MOS transistor constituting a decoder is arranged in the peripheral circuit regions 3 and 4. As will be described later, this high breakdown voltage MOS transistor has a DDD structure.

The other peripheral circuit regions 5 and 6 are circuits for processing an input signal from the outside and an output signal to the outside, and are configured by normal withstand voltage MOS transistors. These MOS transistors are transistors having an LDD structure which will be described later.
In the input / output region 7, a plurality of input / output pads 9 are arranged along the peripheral edge of the semiconductor substrate 1. Corresponding to each input / output pad 9, an electrostatic breakdown countermeasure transistor for suppressing or preventing electrostatic breakdown of the memory cell region 2 and the peripheral circuit regions 3 to 6 by absorbing a surge current caused by electrostatic discharge 10 (shown by hatching in FIG. 1) is provided on the semiconductor substrate 1.

  FIG. 2 is a cross-sectional view for explaining a configuration of a nonvolatile memory cell, a high voltage MOS transistor, a normal voltage MOS transistor, and an electrostatic breakdown countermeasure transistor. A non-volatile memory cell 20 is formed in the memory cell region 2 on the semiconductor substrate 1, a high-voltage DDD-MOS transistor 40 is formed in the peripheral circuit regions 3 and 4, and a normal circuit region in the peripheral circuit regions 5 and 6. A breakdown voltage LDD-MOS transistor 50 is formed, and an electrostatic breakdown countermeasure transistor 10 is formed in the input / output region 7.

  The nonvolatile memory cell 20 has a configuration in which a stacked gate type memory cell transistor 21 and a selection transistor 22 are connected in series. More specifically, the memory cell transistor 21 is opposed to the n-type source region 23 and the n-type tunnel diffusion layer 24 formed at a distance in the surface layer portion of the semiconductor substrate 1 and the channel region 25 therebetween. And a control gate 27 stacked on the floating gate 26. A contact region 37 (high concentration layer) formed by diffusing n type impurities at a high concentration is formed inside the n type source region 23. A source electrode (not shown) is in ohmic contact with the contact region 37.

  The n-type tunnel diffusion layer 24 is formed in a region facing a part of the floating gate 26 and functions as a drain region of the memory cell transistor 21. On the other hand, the select transistor 22 has an n-type tunnel diffusion layer 24 as its source region, an n-type drain region 28 formed in the semiconductor substrate 1 at a predetermined interval from the source region, and the tunnel diffusion layer 24 and the drain region 28. And a gate 29 (selection gate) arranged so as to face the channel region therebetween.

  A gate insulating film 31 made of, for example, silicon oxide is interposed between the semiconductor substrate 1 and the floating gate 26 and the gate 29. The floating gate 26 and the control gate 27 are insulated by an insulating film 32. The insulating film 32 is made of, for example, a film having an ONO (oxide film-nitride film-oxide film) structure in which a silicon nitride film is sandwiched between a pair of silicon oxide films. In the gate insulating film 31, for example, a thin film portion having a thickness of 50 to 100 mm is formed at a portion between the tunnel diffusion layer 24 and the floating gate 26. This thin film portion is a tunnel window 35 for passing electrons between the tunnel diffusion layer 24 and the floating gate 26 by FN (Fowler-Nordheim) tunneling.

  In this embodiment, the control gate 27 has an upper portion facing the upper surface of the floating gate 26 and a pair of side portions depending from both side edges of the upper portion so as to face both side surfaces of the floating gate 26. It is formed in a substantially inverted U shape. Both side surfaces of the control gate 27 are covered with sidewalls 34 made of an insulator such as silicon oxide.

  Similarly, both side surfaces of the gate 29 of the selection transistor 22 are covered with sidewalls 36 made of an insulator such as silicon oxide. In the drain region 28 of the selection transistor 22, a contact region 38 (high concentration layer) formed by diffusing n-type impurities at a high concentration is formed. A drain electrode (not shown) is in ohmic contact with the contact region 38.

  For example, electrons are injected into the floating gate 26 while the source is open and a high voltage is applied to the gate 29 to turn on the selection transistor 22. In this state, when a high voltage is applied to the control gate 27 and the drain is set to the ground potential, electrons are injected from the tunnel diffusion layer 24 into the floating gate 26 by FN tunneling through the tunnel window 35.

  Extraction of electrons from the floating gate 26 is performed, for example, by opening the source and applying a high voltage to the gate 29 to turn on the selection transistor 22. In this state, when the control gate 27 is set to the ground potential and a high voltage is applied to the drain, electrons are extracted from the floating gate 26 to the tunnel diffusion layer 24 by FN tunneling via the tunnel window 35.

  When electrons are injected into the floating gate 26, the threshold voltage to be applied to the control gate 27 in order to make the memory cell transistor 21 conductive when the floating gate 26 is charged increases. Therefore, the read voltage to be applied to the control gate 27 can be conducted between the source region 23 and the tunnel diffusion layer 24 when the floating gate 26 is in an uncharged state (a state in which electrons are extracted), and the floating gate 26 The value is set such that the space between the source 23 and the tunnel diffusion layer 24 is kept in a cut-off state when the state 26 is in a charged state (a state where electrons are injected). Then, the gate 29 of the selection transistor 22 is set to the high level, the drain is set to the high level, and the read voltage is applied to the control gate 27. At this time, whether or not electrons are injected into the floating gate 26 can be distinguished by examining whether or not current flows on the source side.

In this manner, information writing, erasing, and reading operations can be performed on the nonvolatile memory cell 20.
On the other hand, the DDD-MOS transistor 40 includes an n-type source region 41 and an n-type drain region 42 that are formed in the surface layer region of the semiconductor substrate 1 with a space therebetween. A gate 44 is formed across the gate insulating film 31 so as to face the channel region 43 between the source region 41 and the drain region 42. Both side surfaces of the gate 44 are covered with sidewalls 45 made of an insulator such as silicon oxide.

  The source region 41 and the drain region 42 are respectively formed in the n-type low concentration layers 46 and 47 extending from directly below the sidewall 45, thus forming a double diffused drain (DDD) structure. The n-type low concentration layers 46 and 47 are regions formed at a lower concentration than the source / drain regions 41 and 42 and are formed by implanting impurity ions deeper than these. The n-type low concentration layers 46 and 47 are formed in a self-aligned manner with respect to the gate 44. The source / drain regions 41 and 42 are formed in a region away from the sidewall 45. The n-type low concentration layers 46 and 47 alleviate the electric field in the vicinity of the drain region 42 and suppress the hot electron effect.

  The LDD-MOS transistor 50 includes an n-type source region 51 and an n-type drain region 52 that are formed in the surface layer region of the semiconductor substrate 1 with a space therebetween. A gate 54 is formed across the gate insulating film 31 so as to face the channel region 53 between the source / drain regions 51 and 52. Both side surfaces of the gate 54 are covered with sidewalls 55 made of an insulator such as silicon oxide.

  N-type low concentration layers 56 and 57 are formed between the source region 51 and drain region 52 and the gate 54, that is, in a region immediately below the sidewall 55. Thus, the LDD structure is formed. The low concentration layers 56 and 57 are regions formed at a lower concentration than the source / drain regions 51 and 52 and implanted by impurity ions shallower than these. The n-type low concentration layers 56 and 57 are formed in a self-aligned manner with respect to the gate 54, and the source / drain regions 51 and 52 are formed in a self-aligned manner with respect to the sidewall 55. The n-type low concentration layers 56 and 57 alleviate the electric field in the vicinity of the drain region 52 and suppress the hot electron effect.

  The ESD protection transistor 10 includes an n-type source region 11 and an n-type drain region 12 formed at a distance in a surface layer region of the semiconductor substrate 1 and a channel region 13 therebetween, and a gate insulating film 31. And a single drain structure having a gate 14 disposed therebetween. Side walls 15 made of an insulator such as silicon oxide are formed on both side surfaces of the gate 14. The source / drain regions 11 and 12 are formed to extend to a region immediately below the sidewall 15. More specifically, each of the source / drain regions 11 and 12 is formed by performing ion implantation (ESD implantation) in advance before forming the sidewall 15. Further, in the inner regions of the source / drain regions 11, 12, contact regions 18, 19 (high concentration layers) having a higher impurity concentration than the source / drain regions 11, 12 are self-connected to the sidewall 15. It is formed consistently. These contact regions 18 and 19 are regions for forming an ohmic junction with the source electrode and the drain electrode, and are the same as the ion implantation for the source / drain regions of the MOS transistors 40 and 50 after the sidewall 15 is formed. It is formed in the process.

  The source / drain regions 11 and 12 have a lower impurity concentration than the contact regions 18 and 19, but have a higher impurity concentration than the low concentration layers 46 and 56 of the MOS transistors 40 and 50. Thereby, the electrostatic breakdown countermeasure transistor 10 has a single drain structure instead of the DDD structure or the LDD structure, and solves a so-called soft leak problem that occurs after electrostatic pulse application.

  3A to 3J are cross-sectional views for explaining the main part of the manufacturing process of the EEPROM having the above-described configuration. First, as shown in FIG. 3A, a field oxide film 17 is formed on the semiconductor substrate 1 by a LOCOS (Local Oxidation of Silicon) method, and an element isolation process for isolating an element formation region is performed. Thereby, the region 20R for each non-volatile memory cell 20, the region 40R for each individual DDD-MOS transistor 40, the region 50R for each individual LDD-MOS transistor 50, and the individual electrostatic breakdown countermeasure transistor 10 are provided. Each region 10R is secured.

Next, as shown in FIG. 3B, ion implantation (tunnel implantation is performed (first impurity introduction step) for forming the n-type tunnel diffusion layer 24. Specifically, a predetermined pattern is formed on the semiconductor substrate 1. The resist film 101 is formed, and n-type impurity ions are implanted into the semiconductor substrate 1 using the resist film 101 as a mask.The resist film 101 is formed in the n-type source region 23 and the n-type in the non-volatile memory cell region 20R. Openings 101a and 101b are respectively provided in regions where the type tunnel diffusion layer 24 is to be formed, and the resist film 101 covers both the MOS transistor regions 40R and 50R. Reference numeral 101 denotes an opening 10 that exposes a region other than the region where the gate 14 is to be formed in the electrostatic breakdown transistor region 10R. c, and a 101d. For example, As ⁺ ions or ^{P +} ions are used as the n-type impurity ions, the dose is a ^{1 × 10 14 ~1 × 10 15} / cm 2 ( first concentration) The implantation energy is set to 100 keV to 200 keV Thus, in the same step as the ion implantation for forming the n-type tunnel diffusion layer 24, ions for the source / drain regions 11 and 12 of the electrostatic breakdown protection transistor 10 are used. An injection is performed.

  The next step is formation of the gate insulating film 31 having the tunnel window 35 as shown in FIG. 3C. That is, after the resist film 101 is peeled off, the surface of the semiconductor substrate 1 is thermally oxidized to form, for example, a silicon oxide film having a thickness of 100 to 200 mm, which becomes the gate insulating film 31. At this time, the n-type impurity ions implanted in the step of FIG. 3B are simultaneously activated, and the n-type source region 23 and the n-type tunnel diffusion layer 24 are formed in the nonvolatile memory cell region 20R. N-type source / drain regions 11 and 12 are formed in the use region 10R.

  The tunnel window 35 is formed by a known method. That is, a resist film having an opening is formed in a predetermined region (the region where the tunnel window 35 is to be formed) on the tunnel diffusion layer 24, and the gate insulating film 31 in the region is selectively formed by etching using the resist film as a mask. Removed. After removing the resist film, an oxide film is grown by a predetermined thickness (50 to 100 mm) that allows electrons to be FN tunneled by thermal oxidation. Thereby, a thin tunnel window 35 having the thickness is formed, and the gate insulating film 31 is also thickened by the same thickness. The final film thickness of the gate insulating film 31 in the region other than the tunnel window 35 is, for example, 200 to 300 mm. Thus, the gate insulating film 31 having the tunnel window 35 which is a local thin film portion (a portion having a smaller film thickness than the remaining portion) is formed into the nonvolatile memory cell region 20R, the MOS transistor regions 40R and 50R, and the static electricity. It is formed on the surface of the semiconductor substrate 1 in the electric breakdown countermeasure transistor region 10R.

  Next, as shown in FIG. 3D, a gate formation step is performed. That is, in the nonvolatile memory cell region 20R, a floating gate 26 is formed on the gate insulating film 31 in a region extending from the n-type source region 23 to the n-type tunnel diffusion layer 24. The floating gate 26 is spaced apart from the floating gate 26. Thus, the gate 29 of the selection transistor 22 is formed. The floating gate 26 has a region overlapping the n-type tunnel diffusion layer 24 on the side opposite to the n-type source region 23, and is formed so as to face the n-type tunnel diffusion layer 24 across the tunnel window 35 in this region. Is done. The gate 29 is formed to match the edge of the n-type tunnel diffusion layer 24 opposite to the floating gate 26. Further, in the MOS transistor regions 40R and 50R, the gates 44 and 54 are formed on the gate insulating film 31 at substantially the center of each region, respectively. Then, in the electrostatic breakdown countermeasure transistor region 10R, the gate 14 is formed on the gate insulating film 31 so as to overlap both edges of the n-type source / drain regions 11 and 12.

  The floating gate 26 and the gates 29, 44, 45, and 14 are formed by, for example, forming a polysilicon film to which an impurity (for example, phosphorus) for conductivity is added on the entire surface of the semiconductor substrate 1, and patterning the film by photolithography. You can do that. That is, a resist film pattern is formed on the polysilicon film formed on the entire surface. This resist film pattern is a pattern that selectively covers the region where the floating gate 26 and the gates 29, 44, 45, and 14 are to be formed, and exposes other regions. By performing etching using the resist film as a mask, the floating gate 26 and the gates 29, 44, 45, and 14 made of a conductive polysilicon film can be formed.

  Next, as shown in FIG. 3E, an insulating film 32 for the nonvolatile memory cell 20 is formed. The insulating film 32 is formed on the entire surface of the semiconductor substrate 1 by, for example, a CVD (chemical vapor deposition) method. Specifically, first, a silicon oxide film having a thickness of about 100 mm is formed, then a silicon nitride film having a thickness of about 100 mm is formed, and subsequently, a silicon oxide film having a thickness of about 100 mm is formed. Thus, an insulating film 32 having an oxide film / nitride film / oxide film structure (ONO structure) is formed.

  The next step is a control gate forming step shown in FIG. 3F. More specifically, a polysilicon film to which an impurity (for example, phosphorus) for conductivity is added is formed on the entire surface of the semiconductor substrate 1, and the control gate 27 is formed by patterning the polysilicon film. Patterning is performed by photolithography. That is, a resist film pattern is formed on the polysilicon film so as to cover the upper portion of the floating gate 26 and reach a region extending a predetermined distance to the side of the floating gate 26. In the resist film pattern, the region other than the region in the vicinity of the floating gate 26 is exposed. In this state, dry etching is performed, and then the resist film is peeled off, whereby the control gate 27 is formed. The control gate 27 has a pattern that covers the floating gate 26 from the upper surface and both side surfaces through the insulating film 32. In dry etching for patterning the polysilicon film, the insulating film 32 is removed by etching in a region other than the region covered with the control gate 27. As a result, the gates 29, 44, 45, and 14 are exposed.

Next, the DDD implantation step shown in FIG. 3G is performed (second impurity introduction step). That is, n-type impurity ions are selectively implanted toward the surface of the semiconductor substrate 1 using the resist film 102 as a mask. The resist film 102 has an opening 102a in a region corresponding to the n-type drain region 28 in the nonvolatile memory cell region 20R, and an opening 102b corresponding to the n-type low concentration layers 46 and 47 in the DDD-MOS transistor region 40R. And covers the remaining area. By implanting n-type impurity ions using the resist film 102 as a mask, an n-type drain region 28 is formed in the nonvolatile memory cell region 20R. In the DDD-MOS transistor region 40R, n-type drain regions 28R are formed on both sides of the gate 44. Low concentration layers 46 and 47 are formed, respectively. For example, As ⁺ ions or P ⁺ ions are used as n-type impurity ions, the dose is 1 × 10 ¹² to 1 × 10 ¹³ / cm ² (second concentration), and the implantation energy is 50 keV to 100 keV. Is done. In this way, in the same process as the ion implantation for forming the n-type drain region 28 of the selection transistor 22, ion implantation is performed on the region including the region directly under the sidewall 34 of the DDD-MOS transistor 40, and the n-type low concentration layer 46 is formed. , 47 are formed.

After removing the resist film 102, an LDD implantation step shown in FIG. 3H is then performed (second impurity introduction step). That is, n-type impurity ions are selectively implanted toward the surface of the semiconductor substrate 1 using the resist film 103 as a mask. The resist film 103 covers the nonvolatile memory cell region 20R and the DDD-MOS transistor region 40R, and has an opening 103a that exposes the LDD-MOS transistor region 50R and the electrostatic breakdown transistor region 10R. ing. As a result, n-type impurity ions are selectively implanted into the LDD-MOS transistor region 50R and the ESD protection transistor region 10R. As a result, n-type low concentration layers 56 and 57 are formed on both sides of the gate 54 in the LDD-MOS transistor region 50R. For example, As ⁺ ions or P ⁺ ions are used as n-type impurity ions, the dose is 1 × 10 ¹² to 1 × 10 ¹³ / cm ² (second concentration), and the implantation energy is 20 keV to 50 keV. Is done. The implantation energy is made smaller than that in the case of DDD implantation, whereby n-type low concentration layers 56 and 57 are formed in regions shallower than the n-type low concentration layers 46 and 47 of the DDD-MOS transistor 40.

  At this time, the n-type impurity is also introduced into the source / drain regions 11 and 12 on both sides of the gate 14 in the electrostatic breakdown transistor region 10R. However, since n-type impurity ions are implanted at a higher concentration in the tunnel implantation step (see FIG. 3B), there is no substantial change in the electrostatic breakdown transistor region 10R. Therefore, the resist film 103 may be formed in a pattern that covers the electrostatic breakdown countermeasure transistor region 10R.

  After removing the resist film 103, a sidewall forming step is performed as shown in FIG. 3I. That is, for example, after an insulating film such as a silicon oxide film is formed on the entire surface of the semiconductor substrate 1 by the CVD method, the insulating film is etched back by dry etching. When this etch back is performed until the control gate 27 and the gates 29, 44, 54, and 14 are exposed, sidewalls 34, 45, 55, and 15 are formed on both side surfaces thereof.

Next, as shown in FIG. 3J, a source-drain implantation step is performed (third impurity introduction step). That is, n-type impurity ions are selectively implanted toward the surface of the semiconductor substrate 1 using the resist film 104 as a mask. In the resist film 104, openings 104a, 104b, 104, 104d, and 104e are formed. The opening 104a exposes the source region 23 in the nonvolatile memory cell region 20R, and the opening 104b similarly exposes a partial region inside the drain region 28 in the nonvolatile memory cell region 20R. The openings 104c and 104d expose portions of the inner regions of the low-concentration layers 46 and 47 (corresponding regions corresponding to the source / drain regions 41 and 42) in the DDD-MOS transistor region 40R, respectively. The opening 104e exposes the LDD-MOS transistor region 50R and the electrostatic breakdown countermeasure transistor region 10R. Therefore, by implanting n-type impurity ions using the resist film 104 as a mask, contact regions 37 and 38 of the nonvolatile memory cell 20 are formed, source / drain regions 41 and 42 of the DDD transistor 40 are formed, and LDD− Source / drain regions 51 and 52 of the MOS transistor 50 are formed, and contact regions 18 and 19 of the ESD protection transistor 10 are formed. For example, As ⁺ ions or P ⁺ ions are used as the n-type impurity ions, and the dose amount is larger than that in the ion implantation for the tunnel diffusion layer 24 (FIG. 3B), for example, 1 × 10 ¹⁵ −1 × 10 ¹⁶ / cm ² (third concentration). Alternatively, the implantation energy is smaller than that for the tunnel diffusion layer 24 (FIG. 3B) and DDD implantation (FIG. 3G) and larger than that for LDD implantation (FIG. 3H), for example, 40 keV to 70 keV. It is said.

Thereafter, the resist film 104 is peeled off, and a protective film (not shown) covering the entire surface is formed. A plurality of contact holes are formed in the protective film to expose the contact regions 37, 38; 18, 19 and the source / drain regions 41, 42; 51, 52, respectively. A plurality of electrodes in contact with each other are formed.
As described above, according to this embodiment, ion implantation for forming the source / drain regions 11 and 12 of the electrostatic breakdown countermeasure transistor 10 forms the n-type tunnel diffusion layer 24 of the nonvolatile memory cell 20. Are simultaneously performed in the ion implantation step (FIG. 3B). Thereby, since the number of ion implantation processes can be reduced, a manufacturing process can be shortened and it can contribute to improvement in productivity.

  As mentioned above, although one Embodiment of this invention was described, this invention can also be implemented with another form. For example, in the above-described embodiment, the configuration in which both the DDD-MOS transistor 40 and the LDD-MOS transistor 50 are formed on the semiconductor substrate 1 has been described, but only one of them is formed on the semiconductor substrate 1. The present invention can also be applied to such configurations. Moreover, the numerical values such as the dose amount shown in the above-described embodiment are examples, and other values may be applied according to the required specifications.

  In addition, various design changes can be made within the scope of matters described in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view for explaining a configuration of an EEPROM which is a semiconductor device according to an embodiment of the present invention. It is sectional drawing for demonstrating the structure of a non-volatile memory cell, a high voltage | pressure-resistant MOS transistor, a normal voltage | pressure-resistant MOS transistor, and an electrostatic breakdown countermeasure transistor. It is sectional drawing for demonstrating the principal part of the manufacturing process of EEPROM, and shows an element isolation process. It is sectional drawing for demonstrating the principal part of the manufacturing process of EEPROM, and shows a tunnel ion implantation process. It is sectional drawing for demonstrating the principal part of the manufacturing process of EEPROM, and shows a tunnel window formation process. It is sectional drawing for demonstrating the principal part of the manufacturing process of EEPROM, and shows a gate formation process. It is sectional drawing for demonstrating the principal part of the manufacturing process of EEPROM, and shows an insulating film formation process. It is sectional drawing for demonstrating the principal part of the manufacturing process of EEPROM, and shows a control gate formation process. It is sectional drawing for demonstrating the principal part of the manufacturing process of EEPROM, and shows a DDD injection | pouring process. It is sectional drawing for demonstrating the principal part of the manufacturing process of EEPROM, and shows a LDD injection | pouring process. It is sectional drawing for demonstrating the principal part of the manufacturing process of EEPROM, and shows a sidewall formation process. It is sectional drawing for demonstrating the principal part of the manufacturing process of EEPROM, and shows a source-drain implantation process. It is sectional drawing for demonstrating the structural example of a non-volatile memory cell, the MOS transistor which comprises a peripheral circuit, and an electrostatic breakdown countermeasure transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Memory cell area 3-6 Peripheral circuit area 7 Input / output area 9 Input / output pad 10 Electrostatic breakdown countermeasure transistor 10R Electrostatic breakdown countermeasure transistor area 11 n-type source area 12 n-type drain area 13 channel area 14 gate 15 Sidewall 17 Field oxide film 18, 19 Contact region 20 Non-volatile memory cell 20R Non-volatile memory cell region 21 Memory cell transistor 22 Select transistor 23 n-type source region 24 n-type tunnel diffusion layer 25 channel region 26 floating gate 27 control Gate 28 n-type drain region 29 Gate 31 Gate insulating film 32 Insulating film 34 Side wall 35 Tunnel window 36 Side wall 37, 38 Contact region 40 DDD-MOS transistor Star 40R DDD-MOS transistor region 41 n-type source region 42 n-type drain region 43 channel region 44 gate 45 sidewall 46, 47 n-type low concentration layer 50 LDD-MOS transistor 50R LDD-MOS transistor region 51 n-type source Region 52 n-type drain region 53 channel region 54 gate 55 sidewall 56, 57 n-type low concentration layer 101-104 resist film

Claims (5)

A non-volatile memory cell having a tunnel diffusion layer, a MOS transistor having a low concentration layer having a lower impurity concentration than the drain region on the channel portion side of the drain region, and an electrostatic breakdown countermeasure transistor are provided on a common semiconductor substrate. A method for manufacturing a semiconductor device comprising:
The region for the MOS transistor has a portion arranged between the region for the non-volatile memory cell and the region for the electrostatic breakdown countermeasure transistor in a plan view of the semiconductor substrate,
In the semiconductor substrate, the tunnel diffusion layer is introduced into the non-volatile memory cell region by selectively introducing an impurity at a first concentration into the non-volatile memory cell region and the anti-electrostatic breakdown transistor region. Forming a source region and a drain region of the ESD protection transistor at the same time,
A second impurity introduction step of forming the low concentration layer by selectively introducing an impurity at a second concentration lower than the first concentration into the region for the MOS transistor in the semiconductor substrate;
A third impurity introduction step of forming a source region and a drain region of the MOS transistor by selectively introducing an impurity at a third concentration higher than the second concentration into the region for the MOS transistor. Device manufacturing method.   The third impurity introduction step selectively introduces impurities at the third concentration into the region for the MOS transistor and the region for the electrostatic breakdown countermeasure transistor, so that the source region and the drain region of the MOS transistor The semiconductor according to claim 1, wherein a high concentration layer having a higher impurity concentration than the source region and the drain region is formed in the source region and the drain region of the ESD protection transistor at the same time. Device manufacturing method. Forming a floating gate facing the tunnel diffusion layer in the non-volatile memory cell region, and forming a gate in each of the MOS transistor region and the ESD protection transistor region; and
A sidewall forming step of forming a sidewall made of an insulator on the side wall of the gate,
The first impurity introduction step is performed before the gate formation step;
The second impurity introduction step is performed after the gate formation step and before the sidewall formation step;
The method for manufacturing a semiconductor device according to claim 1, wherein the third impurity introduction step is performed after the sidewall formation step.   The method of manufacturing a semiconductor device according to claim 3, wherein the third impurity introducing step includes a step of introducing impurities into the semiconductor substrate in a self-aligned manner with respect to the sidewall. The second impurity introduction step includes a step of forming a low concentration layer extending to a region deeper than a source region and a drain region of the MOS transistor;
5. The method of manufacturing a semiconductor device according to claim 1, wherein the third impurity introduction step includes a step of forming the source region and the drain region in the low concentration layer.

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